2021-07-01 05:07:37 -05:00
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# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
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# Configuration file for running experiments
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# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
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# timeout_each_job : FPGA Task script splits fpga flow into multiple jobs
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# Each job execute fpga_flow script on combination of architecture & benchmark
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# timeout_each_job is timeout for each job
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# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
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[GENERAL]
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run_engine=openfpga_shell
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power_tech_file = ${PATH:OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.xml
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power_analysis = true
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spice_output=false
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verilog_output=true
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timeout_each_job = 20*60
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fpga_flow=yosys_vpr
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arch_variable_file=${PATH:TASK_DIR}/design_variables.yml
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[OpenFPGA_SHELL]
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openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_shell_scripts/generate_fabric_example_script.openfpga
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openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k6_frac_N10_40nm_openfpga.xml
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openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml
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# Use a absolute path for the Verilog netlists to be generated
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# This is designed to allow the test case 'basic_tests/generate_testbench'
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# to use the Verilog netlists along with testbenches in HDL simulation
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openfpga_verilog_output_dir=${PATH:OPENFPGA_PATH}/openfpga_flow/tasks/basic_tests/generate_fabric/latest/k6_frac_N10_tileable_40nm/and2/MIN_ROUTE_CHAN_WIDTH
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[ARCHITECTURES]
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arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k6_frac_N10_tileable_40nm.xml
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[BENCHMARKS]
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bench0=${PATH:DESIGN_PATH}
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[SYNTHESIS_PARAM]
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2022-01-17 02:21:29 -06:00
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bench_read_verilog_options_common = -nolatches
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2021-07-01 05:07:37 -05:00
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bench0_top =${PATH:DESIGN_TOP}
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#bench0_act = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.act
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#bench0_verilog = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.v
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[SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH]
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