OpenFPGA/libs/EXTERNAL/libtatum/test/basic/simplest.single_clock.blif

13 lines
116 B
Plaintext
Raw Normal View History

2020-01-03 21:42:17 -06:00
.model top
.inputs a clk
.outputs b
.latch a l_a re clk 0
.names l_a buf_l_a
1 1
.latch buf_l_a b re clk 0
.end