33 lines
1.4 KiB
Bash
33 lines
1.4 KiB
Bash
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#! /bin/csh -f
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# Example of how to run vpr
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# Set variables
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# For FPGA-Verilog ONLY
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set spice_output_dirname = sram_fpga_hetero
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set spice_output_dirpath = $PWD
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# VPR critical inputs
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#set arch_xml_file = ARCH/k6_N10_MD_tsmc40nm_chain_TT.xml
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#set arch_xml_file = ARCH/ed_dev.xml
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set arch_xml_file = ARCH/k6_N10_SC_tsmc40nm_chain_TT.xml
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#set arch_xml_file = ARCH/k6_N10_SC_tsmc40nm_chain_TT_yosys.xml
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#set arch_xml_file = ARCH/k6_N10_sram_chain_SC_gf130_2x2.xml
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set blif_file = Circuits/s298_prevpr.blif
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set act_file = Circuits/s298_prevpr.act
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#set blif_file = Circuits/simple_gates_prevpr.blif
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#set act_file = Circuits/simple_gates_prevpr.act
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set vpr_route_chan_width = 100
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# Step A: Make sure a clean start
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# Recompile if needed
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#make clean
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#make -j32
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# Remove previous designs
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rm -rf $spice_output_dirpath/$spice_output_dirname
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# Run VPR
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#valgrind
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./vpr $arch_xml_file $blif_file --full_stats --nodisp --activity_file $act_file --fpga_spice --fpga_spice_dir $spice_output_dirpath/$spice_output_dirname --fpga_x2p_rename_illegal_port --fpga_spice_print_top_testbench --fpga_spice_print_lut_testbench --fpga_spice_print_hardlogic_testbench --fpga_spice_print_io_testbench --fpga_spice_print_pb_mux_testbench --fpga_spice_print_cb_mux_testbench --fpga_spice_print_sb_mux_testbench --fpga_spice_print_cb_testbench --fpga_spice_print_sb_testbench --fpga_spice_print_grid_testbench
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