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OpenFPGA/openfpga_flow/regression_test_scripts/micro_benchmark_reg_test.sh

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[Test] Add micro benchmark to a dedicated regression test
2021-06-21 19:35:41 -05:00
#!/bin/bash
set -e
source openfpga.sh
PYTHON_EXEC=python3.8
###############################################
# OpenFPGA Shell with VPR8
##############################################
echo -e "Micro benchmark regression tests";
[Test] Splitting counter benchmarks into 2 categories; One has Verilog-to-Verification tests, while the other has only Verilog-to-Bitstream tests
2022-02-14 14:20:56 -06:00
run-task benchmark_sweep/counter8 --debug --show_thread_logs
[Test] Add new test case to regression tests
2022-02-14 17:58:53 -06:00
run-task benchmark_sweep/counter8_full_testbench --debug --show_thread_logs
[Test] Splitting counter benchmarks into 2 categories; One has Verilog-to-Verification tests, while the other has only Verilog-to-Bitstream tests
2022-02-14 14:20:56 -06:00
run-task benchmark_sweep/counter128 --debug --show_thread_logs
ready to merge
2021-07-01 16:28:59 -05:00
run-task benchmark_sweep/mac_units --debug --show_thread_logs
[Test] Deploy MCNC big20 to the micro benchmark regression test
2021-06-22 17:36:04 -05:00
# Verify MCNC big20 benchmark suite with ModelSim
# Please make sure you have ModelSim installed in the environment
# Otherwise, it will fail
ready to merge
2021-07-01 16:28:59 -05:00
run-task benchmark_sweep/mcnc_big20 --debug --show_thread_logs
[Test] Deploy MCNC big20 to the micro benchmark regression test
2021-06-22 17:36:04 -05:00
#python3 openfpga_flow/scripts/run_modelsim.py mcnc_big20 --run_sim
added signal gen regression test to shell script
2021-06-30 17:18:09 -05:00
run-task benchmark_sweep/signal_gen --debug --show_thread_logs