18 lines
276 B
Coq
18 lines
276 B
Coq
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module PC(PC_out,PC_in,load,inc,clk,rst);
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output [7:0]PC_out;
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input [7:0]PC_in;
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input load,inc,clk,rst;
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reg [7:0]PC_out;
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always@(posedge clk)
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begin
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if(rst==1)PC_out<=8'b0;
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else if(load==1)PC_out<=PC_in;
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else if(inc==1)PC_out<=PC_out+8'b00000001;
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end
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endmodule
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