OpenFPGA/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_wire.h

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2019-09-12 21:49:02 -05:00
/***********************************************
* Header file for verilog_wire.cpp
**********************************************/
#ifndef VERILOG_WIRE_H
#define VERILOG_WIRE_H
/* Include other header files which are dependency on the function declared below */
#include <fstream>
#include <vector>
#include "physical_types.h"
#include "vpr_types.h"
#include "circuit_library.h"
#include "module_manager.h"
void print_verilog_submodule_wires(ModuleManager& module_manager,
const CircuitLibrary& circuit_lib,
std::vector<t_segment_inf> routing_segments,
const std::string& verilog_dir,
const std::string& submodule_dir);
#endif