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#ifndef VERILOG_API_H
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#define VERILOG_API_H
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#include <string>
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#include <vector>
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#include "vpr_types.h"
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#include "mux_library.h"
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#include "rr_blocks.h"
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#include "module_manager.h"
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#include "bitstream_manager.h"
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void vpr_fpga_verilog(ModuleManager& module_manager,
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const BitstreamManager& bitstream_manager,
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const std::vector<ConfigBitId>& fabric_bitstream,
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const MuxLibrary& mux_lib,
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const std::vector<t_logical_block>& L_logical_blocks,
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const vtr::Point<size_t>& device_size,
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const std::vector<std::vector<t_grid_tile>>& L_grids,
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const std::vector<t_block>& L_blocks,
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const DeviceRRGSB& L_device_rr_gsb,
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const t_vpr_setup& vpr_setup,
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const t_arch& Arch,
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const std::string& circuit_name,
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t_sram_orgz_info* sram_verilog_orgz_info);
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2019-10-18 22:59:22 -05:00
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#endif
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