2019-10-07 17:03:15 -05:00
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/********************************************************************
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* This file includes functions to print Verilog modules for a Grid
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* (CLBs, I/Os, heterogeneous blocks etc.)
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*******************************************************************/
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/* System header files */
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#include <vector>
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#include <fstream>
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/* Header files from external libs */
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#include "util.h"
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#include "vtr_assert.h"
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2019-10-08 19:00:04 -05:00
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#include "circuit_library_utils.h"
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2019-10-07 17:03:15 -05:00
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/* Header files for VPR */
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#include "vpr_types.h"
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#include "globals.h"
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/* Header files for FPGA X2P tool suite */
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#include "fpga_x2p_naming.h"
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2019-10-07 18:39:00 -05:00
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#include "fpga_x2p_types.h"
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2019-10-07 17:03:15 -05:00
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#include "fpga_x2p_utils.h"
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#include "fpga_x2p_pbtypes_utils.h"
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2019-10-08 15:03:17 -05:00
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#include "module_manager_utils.h"
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#include "fpga_x2p_globals.h"
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2019-10-07 17:03:15 -05:00
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/* Header files for Verilog generator */
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#include "verilog_global.h"
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#include "verilog_utils.h"
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#include "verilog_writer_utils.h"
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#include "verilog_grid.h"
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2019-10-07 22:09:54 -05:00
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/********************************************************************
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2019-10-08 13:10:26 -05:00
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* Print Verilog modules of a primitive node in the pb_graph_node graph
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* This generic function can support all the different types of primitive nodes
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* i.e., Look-Up Tables (LUTs), Flip-flops (FFs) and hard logic blocks such as adders.
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*
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* The Verilog module will consist of two parts:
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* 1. Logic module of the primitive node
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* This module performs the logic function of the block
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* 2. Memory module of the primitive node
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* This module stores the configuration bits for the logic module
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* if the logic module is a programmable resource, such as LUT
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2019-10-07 22:09:54 -05:00
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*
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* Verilog module structure:
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*
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2019-10-08 13:10:26 -05:00
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* Primitive block
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* +---------------------------------------+
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* | |
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* | +---------+ +---------+ |
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* in |----->| |--->| |<------|configuration lines
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2019-10-08 13:10:26 -05:00
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* | | Logic |... | Memory | |
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* out|<-----| |--->| | |
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* | +---------+ +---------+ |
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* | |
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* +---------------------------------------+
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*
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*******************************************************************/
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static
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void print_verilog_primitive_block(std::fstream& fp,
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ModuleManager& module_manager,
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const CircuitLibrary& circuit_lib,
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t_sram_orgz_info* cur_sram_orgz_info,
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t_pb_graph_node* primitive_pb_graph_node,
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const e_side& io_side,
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const bool& use_explicit_mapping) {
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2019-10-07 22:09:54 -05:00
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/* Ensure a valid file handler */
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check_file_handler(fp);
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/* Ensure a valid pb_graph_node */
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2019-10-08 13:10:26 -05:00
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if (NULL == primitive_pb_graph_node) {
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2019-10-07 22:09:54 -05:00
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vpr_printf(TIO_MESSAGE_ERROR,
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"(File:%s,[LINE%d]) Invalid primitive_pb_graph_node!\n",
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__FILE__, __LINE__);
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exit(1);
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}
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/* Find the circuit model id linked to the pb_graph_node */
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CircuitModelId& primitive_model = primitive_pb_graph_node->pb_type->circuit_model;
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2019-10-07 22:09:54 -05:00
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/* Generate the module name for this primitive pb_graph_node*/
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std::string primitive_module_name_prefix(grid_verilog_file_name_prefix);
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/* Add side string to the name if it is valid, this is mainly for I/O block */
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if (NUM_SIDES != io_side) {
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Side side_manager(io_side);
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primitive_module_name_prefix += std::string(side_manager.to_string());
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primitive_module_name_prefix += std::string("_");
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}
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std::string primitive_module_name = generate_physical_block_module_name(primitive_module_name_prefix, primitive_pb_graph_node->pb_type);
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/* Create a module of the primitive LUT and register it to module manager */
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ModuleId primitive_module = module_manager.add_module(primitive_module_name);
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/* Ensure that the module has been created and thus unique! */
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VTR_ASSERT(ModuleId::INVALID() != primitive_module);
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/* Find the global ports required by the primitive node, and add them to the module */
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std::vector<CircuitPortId> primitive_model_global_ports = circuit_lib.model_global_ports(primitive_model, true);
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for (auto port : primitive_model_global_ports) {
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/* The global I/O of the FPGA has a special name */
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BasicPort module_port(circuit_lib.port_lib_name(port), circuit_lib.port_size(port));
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module_manager.add_port(primitive_module, module_port, ModuleManager::MODULE_GLOBAL_PORT);
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}
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2019-10-08 13:10:26 -05:00
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/* Find the inout ports required by the primitive node, and add them to the module
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* This is mainly due to the I/O blocks, which have inout ports for the top-level fabric
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2019-10-07 22:09:54 -05:00
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*/
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if (SPICE_MODEL_IOPAD == circuit_lib.model_type(primitive_model)) {
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std::vector<CircuitPortId> primitive_model_inout_ports = circuit_lib.model_ports_by_type(primitive_model, SPICE_MODEL_PORT_INOUT);
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for (auto port : primitive_model_inout_ports) {
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BasicPort module_port(generate_fpga_global_io_port_name(std::string(gio_inout_prefix), circuit_lib, primitive_model), circuit_lib.port_size(port));
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module_manager.add_port(primitive_module, module_port, ModuleManager::MODULE_INOUT_PORT);
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}
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}
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/* Note: to cooperate with the pb_type hierarchy and connections, we add the port of primitive pb_type here.
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* Since we have linked pb_type ports to circuit models when setting up FPGA-X2P,
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* no ports of the circuit model will be missing here
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*/
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add_pb_type_ports_to_module_manager(module_manager, primitive_module, primitive_pb_graph_node->pb_type);
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2019-10-07 22:09:54 -05:00
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2019-10-08 13:10:26 -05:00
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/* Add configuration ports */
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2019-10-08 19:00:04 -05:00
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/* Shared SRAM ports*/
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size_t num_shared_config_bits = find_circuit_num_shared_config_bits(circuit_lib, primitive_model, cur_sram_orgz_info->type);
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if (0 < num_shared_config_bits) {
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/* Check: this SRAM organization type must be memory-bank ! */
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VTR_ASSERT( SPICE_SRAM_MEMORY_BANK == cur_sram_orgz_info->type );
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/* Generate a list of ports */
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add_reserved_sram_ports_to_module_manager(module_manager, primitive_module,
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num_shared_config_bits);
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}
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/* TODO: this should be added to the cur_sram_orgz_info !!! */
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t_spice_model* mem_model = NULL;
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get_sram_orgz_info_mem_model(cur_sram_orgz_info, & mem_model);
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CircuitModelId sram_model = circuit_lib.model(mem_model->name);
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VTR_ASSERT(CircuitModelId::INVALID() != sram_model);
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/* Regular (independent) SRAM ports */
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size_t num_config_bits = find_circuit_num_config_bits(circuit_lib, primitive_model);
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if (0 < num_config_bits) {
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add_sram_ports_to_module_manager(module_manager, primitive_module,
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circuit_lib, sram_model, cur_sram_orgz_info->type,
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num_config_bits);
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/* Add ports only visible during formal verification to the module */
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add_formal_verification_sram_ports_to_module_manager(module_manager, primitive_module, circuit_lib, sram_model,
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std::string(verilog_formal_verification_preproc_flag),
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num_config_bits);
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}
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2019-10-07 22:09:54 -05:00
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2019-10-08 13:10:26 -05:00
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/* Print the module definition for the top-level Verilog module of physical block */
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print_verilog_module_declaration(fp, module_manager, primitive_module);
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2019-10-07 22:09:54 -05:00
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/* Finish printing ports */
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/* TODO: Create local wires as configuration bus */
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/* TODO: Create a bus wire for the inputs of the LUT */
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/* TODO: Instanciate LUT MUX module */
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/* TODO: Instanciate associated memory module for the LUT */
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/* Print an end to the Verilog module */
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2019-10-08 13:10:26 -05:00
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print_verilog_module_end(fp, module_manager.module_name(primitive_module));
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2019-10-07 22:09:54 -05:00
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/* Add an empty line as a splitter */
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fp << std::endl;
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}
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2019-10-07 18:39:00 -05:00
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/********************************************************************
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* Print Verilog modules of physical blocks inside a grid (CLB, I/O. etc.)
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* This function will traverse the graph of complex logic block (t_pb_graph_node)
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* in a recursive way, using a Depth First Search (DFS) algorithm.
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* As such, primitive physical blocks (LUTs, FFs, etc.), leaf node of the pb_graph
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* will be printed out first, while the top-level will be printed out in the last
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*
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* Note: this function will print a unique Verilog module for each type of
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* t_pb_graph_node, i.e., t_pb_type, in the graph, in order to enable highly
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* hierarchical Verilog organization as well as simplify the Verilog file sizes.
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*
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* Note: DFS is the right way. Do NOT use BFS.
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* DFS can guarantee that all the sub-modules can be registered properly
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* to its parent in module manager
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*******************************************************************/
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static
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void print_verilog_physical_blocks_rec(std::fstream& fp,
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ModuleManager& module_manager,
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const CircuitLibrary& circuit_lib,
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const MuxLibrary& mux_lib,
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t_sram_orgz_info* cur_sram_orgz_info,
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t_pb_graph_node* physical_pb_graph_node,
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2019-10-07 22:09:54 -05:00
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const e_side& io_side,
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const bool& use_explicit_mapping) {
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/* Check the file handler*/
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check_file_handler(fp);
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/* Check cur_pb_graph_node*/
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if (NULL == physical_pb_graph_node) {
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vpr_printf(TIO_MESSAGE_ERROR,
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"(File:%s,[LINE%d]) Invalid cur_pb_graph_node.\n",
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__FILE__, __LINE__);
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exit(1);
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}
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/* Get the pb_type definition related to the node */
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t_pb_type* physical_pb_type = physical_pb_graph_node->pb_type;
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/* Find the mode that physical implementation of a pb_type */
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int physical_mode_index = find_pb_type_physical_mode_index((*physical_pb_type));
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/* For non-leaf node in the pb_type graph:
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* Recursively Depth-First Generate all the child pb_type at the level
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*/
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if (FALSE == is_primitive_pb_type(physical_pb_type)) {
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for (int ipb = 0; ipb < physical_pb_type->modes[physical_mode_index].num_pb_type_children; ++ipb) {
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/* Go recursive to visit the children */
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print_verilog_physical_blocks_rec(fp, module_manager, circuit_lib, mux_lib,
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cur_sram_orgz_info,
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&(physical_pb_graph_node->child_pb_graph_nodes[physical_mode_index][ipb][0]),
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io_side,
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use_explicit_mapping);
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}
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}
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/* For leaf node, a primitive Verilog module will be generated */
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if (TRUE == is_primitive_pb_type(physical_pb_type)) {
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2019-10-08 13:10:26 -05:00
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print_verilog_primitive_block(fp, module_manager, circuit_lib,
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2019-10-07 22:09:54 -05:00
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cur_sram_orgz_info,
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physical_pb_graph_node,
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io_side,
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use_explicit_mapping);
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2019-10-07 18:39:00 -05:00
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/* Finish for primitive node, return */
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return;
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}
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2019-10-07 22:09:54 -05:00
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/* Generate the name of the Verilog module for this pb_type */
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std::string pb_module_name_prefix(grid_verilog_file_name_prefix);
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/* Add side string to the name if it is valid */
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if (NUM_SIDES != io_side) {
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Side side_manager(io_side);
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pb_module_name_prefix += std::string(side_manager.to_string());
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pb_module_name_prefix += std::string("_");
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}
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std::string pb_module_name = generate_physical_block_module_name(pb_module_name_prefix, physical_pb_type);
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2019-10-07 18:39:00 -05:00
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2019-10-07 22:09:54 -05:00
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/* Register the Verilog module in module manager */
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ModuleId pb_module = module_manager.add_module(pb_module_name);
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VTR_ASSERT(ModuleId::INVALID() != pb_module);
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2019-10-07 18:39:00 -05:00
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/* TODO: Add ports to the Verilog module */
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/* TODO: Count I/O (INOUT) ports from the sub-modules under this Verilog module */
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/* TODO: Count shared SRAM ports from the sub-modules under this Verilog module */
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/* TODO: Count SRAM ports from the sub-modules under this Verilog module */
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/* TODO: Count formal verification ports from the sub-modules under this Verilog module */
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2019-10-07 22:09:54 -05:00
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/* Print Verilog module declaration */
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print_verilog_module_declaration(fp, module_manager, pb_module);
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2019-10-07 18:39:00 -05:00
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/* Comment lines */
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print_verilog_comment(fp, std::string("----- BEGIN Physical programmable logic block Verilog module: " + std::string(physical_pb_type->name) + " -----"));
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/* TODO: Print local wires (bus wires for memory configuration) */
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/*
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dump_verilog_sram_config_bus_internal_wires(fp, cur_sram_orgz_info,
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stamped_sram_cnt,
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stamped_sram_cnt + num_conf_bits - 1);
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*/
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/* TODO: Instanciate all the child Verilog modules */
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for (int ipb = 0; ipb < physical_pb_type->modes[physical_mode_index].num_pb_type_children; ipb++) {
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/* Each child may exist multiple times in the hierarchy*/
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for (int jpb = 0; jpb < physical_pb_type->modes[physical_mode_index].pb_type_children[ipb].num_pb; jpb++) {
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/* we should make sure this placement index == child_pb_type[jpb] */
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VTR_ASSERT(jpb == physical_pb_graph_node->child_pb_graph_nodes[physical_mode_index][ipb][jpb].placement_index);
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}
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}
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/* TODO: Print programmable/non-programmable interconnections inside the Verilog module */
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/*
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dump_verilog_pb_graph_interc(cur_sram_orgz_info, fp, subckt_name,
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cur_pb_graph_node, mode_index,
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is_explicit_mapping);
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*/
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|
|
|
|
|
|
|
/* Print an end to the Verilog module */
|
2019-10-07 22:09:54 -05:00
|
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|
print_verilog_module_end(fp, module_manager.module_name(pb_module));
|
2019-10-07 18:39:00 -05:00
|
|
|
|
2019-10-07 22:09:54 -05:00
|
|
|
print_verilog_comment(fp, std::string("----- END Physical programmable logic block Verilog module: " + std::string(physical_pb_type->name) + " -----"));
|
2019-10-07 18:39:00 -05:00
|
|
|
|
2019-10-07 22:09:54 -05:00
|
|
|
/* Add an empty line as a splitter */
|
|
|
|
fp << std::endl;
|
|
|
|
}
|
2019-10-07 18:39:00 -05:00
|
|
|
|
2019-10-07 17:03:15 -05:00
|
|
|
/*****************************************************************************
|
|
|
|
* This function will create a Verilog file and print out a Verilog netlist
|
|
|
|
* for a type of physical block
|
|
|
|
*
|
|
|
|
* For IO blocks:
|
|
|
|
* The param 'border_side' is required, which is specify which side of fabric
|
|
|
|
* the I/O block locates at.
|
|
|
|
*****************************************************************************/
|
|
|
|
static
|
|
|
|
void print_verilog_grid(ModuleManager& module_manager,
|
|
|
|
const MuxLibrary& mux_lib,
|
|
|
|
const CircuitLibrary& circuit_lib,
|
|
|
|
t_sram_orgz_info* cur_sram_orgz_info,
|
|
|
|
const std::string& verilog_dir,
|
|
|
|
const std::string& subckt_dir,
|
|
|
|
t_type_ptr phy_block_type,
|
|
|
|
const e_side& border_side,
|
|
|
|
const bool& use_explicit_mapping) {
|
|
|
|
/* Check code: if this is an IO block, the border side MUST be valid */
|
|
|
|
if (IO_TYPE == phy_block_type) {
|
|
|
|
VTR_ASSERT(NUM_SIDES != border_side);
|
|
|
|
}
|
|
|
|
|
|
|
|
/* Give a name to the Verilog netlist */
|
|
|
|
/* Create the file name for Verilog */
|
|
|
|
std::string verilog_fname(subckt_dir
|
2019-10-07 22:09:54 -05:00
|
|
|
+ generate_grid_block_netlist_name(std::string(phy_block_type->name),
|
|
|
|
IO_TYPE == phy_block_type,
|
|
|
|
border_side,
|
|
|
|
std::string(verilog_netlist_file_postfix))
|
2019-10-07 17:03:15 -05:00
|
|
|
);
|
|
|
|
/* TODO: remove the bak file when the file is ready */
|
|
|
|
verilog_fname += ".bak";
|
|
|
|
|
|
|
|
/* Echo status */
|
|
|
|
if (IO_TYPE == phy_block_type) {
|
|
|
|
Side side_manager(border_side);
|
|
|
|
vpr_printf(TIO_MESSAGE_INFO,
|
|
|
|
"Writing FPGA Verilog Netlist (%s) for logic block %s at %s side ...\n",
|
|
|
|
verilog_fname.c_str(), phy_block_type->name,
|
|
|
|
side_manager.c_str());
|
|
|
|
} else {
|
|
|
|
vpr_printf(TIO_MESSAGE_INFO,
|
|
|
|
"Writing FPGA Verilog Netlist (%s) for logic block %s...\n",
|
|
|
|
verilog_fname.c_str(), phy_block_type->name);
|
|
|
|
}
|
|
|
|
|
|
|
|
/* Create the file stream */
|
|
|
|
std::fstream fp;
|
|
|
|
fp.open(verilog_fname, std::fstream::out | std::fstream::trunc);
|
|
|
|
|
|
|
|
check_file_handler(fp);
|
|
|
|
|
|
|
|
print_verilog_file_header(fp, std::string("Verilog modules for physical block: " + std::string(phy_block_type->name) + "]"));
|
|
|
|
|
|
|
|
/* Print preprocessing flags */
|
|
|
|
print_verilog_include_defines_preproc_file(fp, verilog_dir);
|
|
|
|
|
|
|
|
/* TODO: Print Verilog modules for all the pb_types/pb_graph_nodes */
|
2019-10-07 22:09:54 -05:00
|
|
|
/* TODO: use a Depth-First Search Algorithm to print the sub-modules
|
|
|
|
* Note: DFS is the right way. Do NOT use BFS.
|
|
|
|
* DFS can guarantee that all the sub-modules can be registered properly
|
|
|
|
* to its parent in module manager
|
|
|
|
*/
|
|
|
|
print_verilog_comment(fp, std::string("---- BEGIN Sub-module of physical block:" + std::string(phy_block_type->name) + " ----"));
|
|
|
|
|
|
|
|
/* Print Verilog modules starting from the top-level pb_type/pb_graph_node, and traverse the graph in a recursive way */
|
|
|
|
print_verilog_physical_blocks_rec(fp, module_manager, circuit_lib, mux_lib,
|
|
|
|
cur_sram_orgz_info,
|
|
|
|
phy_block_type->pb_graph_head,
|
|
|
|
border_side,
|
|
|
|
use_explicit_mapping);
|
|
|
|
|
|
|
|
print_verilog_comment(fp, std::string("---- END Sub-module of physical block:" + std::string(phy_block_type->name) + " ----"));
|
2019-10-07 17:03:15 -05:00
|
|
|
|
|
|
|
/* TODO: Create a Verilog Module for the top-level physical block, and add to module manager */
|
2019-10-07 22:09:54 -05:00
|
|
|
std::string module_name = generate_grid_block_module_name(std::string(grid_verilog_file_name_prefix), phy_block_type->name, IO_TYPE == phy_block_type, border_side);
|
2019-10-07 17:03:15 -05:00
|
|
|
ModuleId module_id = module_manager.add_module(module_name);
|
2019-10-07 22:09:54 -05:00
|
|
|
VTR_ASSERT(ModuleId::INVALID() != module_id);
|
2019-10-07 17:03:15 -05:00
|
|
|
|
|
|
|
/* TODO: Add ports to the module */
|
|
|
|
|
|
|
|
|
|
|
|
/* TODO: Print the module definition for the top-level Verilog module of physical block */
|
|
|
|
print_verilog_module_declaration(fp, module_manager, module_id);
|
|
|
|
/* Finish printing ports */
|
|
|
|
|
|
|
|
/* Print an empty line a splitter */
|
|
|
|
fp << std::endl;
|
|
|
|
|
|
|
|
/* TODO: instanciate all the sub modules */
|
|
|
|
for (int iz = 0; iz < phy_block_type->capacity; ++iz) {
|
|
|
|
}
|
|
|
|
|
|
|
|
/* Put an end to the top-level Verilog module of physical block */
|
|
|
|
print_verilog_module_end(fp, module_manager.module_name(module_id));
|
|
|
|
|
|
|
|
/* Add an empty line as a splitter */
|
|
|
|
fp << std::endl;
|
|
|
|
|
|
|
|
/* Close file handler */
|
|
|
|
fp.close();
|
|
|
|
|
|
|
|
/* Add fname to the linked list */
|
2019-10-07 18:39:00 -05:00
|
|
|
/* TODO: add it when it is ready
|
2019-10-07 17:03:15 -05:00
|
|
|
grid_verilog_subckt_file_path_head = add_one_subckt_file_name_to_llist(grid_verilog_subckt_file_path_head, verilog_fname.c_str());
|
|
|
|
*/
|
|
|
|
}
|
|
|
|
|
|
|
|
/*****************************************************************************
|
|
|
|
* Create logic block modules in a compact way:
|
|
|
|
* 1. Only one module for each I/O on each border side (IO_TYPE)
|
|
|
|
* 2. Only one module for each CLB (FILL_TYPE)
|
|
|
|
* 3. Only one module for each heterogeneous block
|
|
|
|
****************************************************************************/
|
|
|
|
void print_verilog_grids(ModuleManager& module_manager,
|
|
|
|
const CircuitLibrary& circuit_lib,
|
|
|
|
const MuxLibrary& mux_lib,
|
|
|
|
t_sram_orgz_info* cur_sram_orgz_info,
|
|
|
|
const std::string& verilog_dir,
|
|
|
|
const std::string& subckt_dir,
|
|
|
|
const bool& is_explicit_mapping) {
|
|
|
|
/* Enumerate the types, dump one Verilog module for each */
|
|
|
|
for (int itype = 0; itype < num_types; itype++) {
|
|
|
|
if (EMPTY_TYPE == &type_descriptors[itype]) {
|
|
|
|
/* Bypass empty type or NULL */
|
|
|
|
continue;
|
|
|
|
} else if (IO_TYPE == &type_descriptors[itype]) {
|
|
|
|
/* Special for I/O block, generate one module for each border side */
|
|
|
|
for (int iside = 0; iside < NUM_SIDES; iside++) {
|
|
|
|
Side side_manager(iside);
|
|
|
|
print_verilog_grid(module_manager, mux_lib, circuit_lib,
|
|
|
|
cur_sram_orgz_info,
|
|
|
|
verilog_dir, subckt_dir,
|
|
|
|
&type_descriptors[itype],
|
|
|
|
side_manager.get_side(),
|
|
|
|
is_explicit_mapping);
|
|
|
|
}
|
|
|
|
continue;
|
|
|
|
} else if (FILL_TYPE == &type_descriptors[itype]) {
|
|
|
|
/* For CLB */
|
|
|
|
print_verilog_grid(module_manager, mux_lib, circuit_lib,
|
|
|
|
cur_sram_orgz_info,
|
|
|
|
verilog_dir, subckt_dir,
|
|
|
|
&type_descriptors[itype],
|
|
|
|
NUM_SIDES,
|
|
|
|
is_explicit_mapping);
|
|
|
|
continue;
|
|
|
|
} else {
|
|
|
|
/* For heterogenenous blocks */
|
|
|
|
print_verilog_grid(module_manager, mux_lib, circuit_lib,
|
|
|
|
cur_sram_orgz_info,
|
|
|
|
verilog_dir, subckt_dir,
|
|
|
|
&type_descriptors[itype],
|
|
|
|
NUM_SIDES,
|
|
|
|
is_explicit_mapping);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
/* Output a header file for all the logic blocks */
|
|
|
|
vpr_printf(TIO_MESSAGE_INFO, "Generating header file for grid Verilog modules...\n");
|
|
|
|
std::string grid_verilog_fname(logic_block_verilog_file_name);
|
|
|
|
/* TODO: remove .bak when it is ready */
|
|
|
|
grid_verilog_fname += ".bak";
|
|
|
|
dump_verilog_subckt_header_file(grid_verilog_subckt_file_path_head,
|
|
|
|
subckt_dir.c_str(),
|
|
|
|
grid_verilog_fname.c_str());
|
|
|
|
}
|
|
|
|
|