526 lines
18 KiB
Coq
526 lines
18 KiB
Coq
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//-------------------------------------------
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// FPGA Synthesizable Verilog Netlist
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// Description: Routing Channel - X direction [1][0] in FPGA
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// Author: Xifan TANG
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// Organization: EPFL/IC/LSI
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// Date: Thu Nov 15 14:26:09 2018
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//-------------------------------------------
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//----- Time scale -----
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`timescale 1ns / 1ps
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//----- Verilog Module of Channel X [1][0] -----
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module chanx_1__0_ (
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//----- BEGIN Global ports -----
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input [0:0] zin,
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input [0:0] clk,
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input [0:0] Reset,
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input [0:0] Set
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//----- END Global ports -----
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,
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input in0, //--- track 0 input
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output out1, //--- track 1 output
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input in2, //--- track 2 input
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output out3, //--- track 3 output
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input in4, //--- track 4 input
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output out5, //--- track 5 output
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input in6, //--- track 6 input
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output out7, //--- track 7 output
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input in8, //--- track 8 input
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output out9, //--- track 9 output
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input in10, //--- track 10 input
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output out11, //--- track 11 output
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input in12, //--- track 12 input
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output out13, //--- track 13 output
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input in14, //--- track 14 input
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output out15, //--- track 15 output
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input in16, //--- track 16 input
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output out17, //--- track 17 output
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input in18, //--- track 18 input
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output out19, //--- track 19 output
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input in20, //--- track 20 input
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output out21, //--- track 21 output
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input in22, //--- track 22 input
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output out23, //--- track 23 output
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input in24, //--- track 24 input
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output out25, //--- track 25 output
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input in26, //--- track 26 input
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output out27, //--- track 27 output
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input in28, //--- track 28 input
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output out29, //--- track 29 output
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input in30, //--- track 30 input
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output out31, //--- track 31 output
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input in32, //--- track 32 input
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output out33, //--- track 33 output
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input in34, //--- track 34 input
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output out35, //--- track 35 output
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input in36, //--- track 36 input
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output out37, //--- track 37 output
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input in38, //--- track 38 input
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output out39, //--- track 39 output
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input in40, //--- track 40 input
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output out41, //--- track 41 output
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input in42, //--- track 42 input
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output out43, //--- track 43 output
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input in44, //--- track 44 input
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output out45, //--- track 45 output
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input in46, //--- track 46 input
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output out47, //--- track 47 output
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input in48, //--- track 48 input
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output out49, //--- track 49 output
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input in50, //--- track 50 input
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output out51, //--- track 51 output
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input in52, //--- track 52 input
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output out53, //--- track 53 output
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input in54, //--- track 54 input
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output out55, //--- track 55 output
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input in56, //--- track 56 input
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output out57, //--- track 57 output
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input in58, //--- track 58 input
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output out59, //--- track 59 output
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input in60, //--- track 60 input
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output out61, //--- track 61 output
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input in62, //--- track 62 input
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output out63, //--- track 63 output
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input in64, //--- track 64 input
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output out65, //--- track 65 output
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input in66, //--- track 66 input
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output out67, //--- track 67 output
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input in68, //--- track 68 input
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output out69, //--- track 69 output
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input in70, //--- track 70 input
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output out71, //--- track 71 output
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input in72, //--- track 72 input
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output out73, //--- track 73 output
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input in74, //--- track 74 input
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output out75, //--- track 75 output
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input in76, //--- track 76 input
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output out77, //--- track 77 output
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input in78, //--- track 78 input
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output out79, //--- track 79 output
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input in80, //--- track 80 input
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output out81, //--- track 81 output
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input in82, //--- track 82 input
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output out83, //--- track 83 output
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input in84, //--- track 84 input
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output out85, //--- track 85 output
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input in86, //--- track 86 input
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output out87, //--- track 87 output
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input in88, //--- track 88 input
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output out89, //--- track 89 output
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input in90, //--- track 90 input
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output out91, //--- track 91 output
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input in92, //--- track 92 input
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output out93, //--- track 93 output
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input in94, //--- track 94 input
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output out95, //--- track 95 output
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input in96, //--- track 96 input
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output out97, //--- track 97 output
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input in98, //--- track 98 input
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output out99, //--- track 99 output
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output out0, //--- track 0 output
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input in1, //--- track 1 input
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output out2, //--- track 2 output
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input in3, //--- track 3 input
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output out4, //--- track 4 output
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input in5, //--- track 5 input
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output out6, //--- track 6 output
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input in7, //--- track 7 input
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output out8, //--- track 8 output
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input in9, //--- track 9 input
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output out10, //--- track 10 output
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input in11, //--- track 11 input
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output out12, //--- track 12 output
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input in13, //--- track 13 input
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output out14, //--- track 14 output
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input in15, //--- track 15 input
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output out16, //--- track 16 output
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input in17, //--- track 17 input
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output out18, //--- track 18 output
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input in19, //--- track 19 input
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output out20, //--- track 20 output
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input in21, //--- track 21 input
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output out22, //--- track 22 output
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input in23, //--- track 23 input
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output out24, //--- track 24 output
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input in25, //--- track 25 input
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output out26, //--- track 26 output
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input in27, //--- track 27 input
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output out28, //--- track 28 output
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input in29, //--- track 29 input
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output out30, //--- track 30 output
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input in31, //--- track 31 input
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output out32, //--- track 32 output
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input in33, //--- track 33 input
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output out34, //--- track 34 output
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input in35, //--- track 35 input
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output out36, //--- track 36 output
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input in37, //--- track 37 input
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output out38, //--- track 38 output
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input in39, //--- track 39 input
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output out40, //--- track 40 output
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input in41, //--- track 41 input
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output out42, //--- track 42 output
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input in43, //--- track 43 input
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output out44, //--- track 44 output
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input in45, //--- track 45 input
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output out46, //--- track 46 output
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input in47, //--- track 47 input
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output out48, //--- track 48 output
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input in49, //--- track 49 input
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output out50, //--- track 50 output
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input in51, //--- track 51 input
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output out52, //--- track 52 output
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input in53, //--- track 53 input
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output out54, //--- track 54 output
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input in55, //--- track 55 input
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output out56, //--- track 56 output
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input in57, //--- track 57 input
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output out58, //--- track 58 output
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input in59, //--- track 59 input
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output out60, //--- track 60 output
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input in61, //--- track 61 input
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output out62, //--- track 62 output
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input in63, //--- track 63 input
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output out64, //--- track 64 output
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input in65, //--- track 65 input
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output out66, //--- track 66 output
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input in67, //--- track 67 input
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output out68, //--- track 68 output
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input in69, //--- track 69 input
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output out70, //--- track 70 output
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input in71, //--- track 71 input
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output out72, //--- track 72 output
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input in73, //--- track 73 input
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output out74, //--- track 74 output
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input in75, //--- track 75 input
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output out76, //--- track 76 output
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input in77, //--- track 77 input
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output out78, //--- track 78 output
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input in79, //--- track 79 input
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output out80, //--- track 80 output
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input in81, //--- track 81 input
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output out82, //--- track 82 output
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input in83, //--- track 83 input
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output out84, //--- track 84 output
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input in85, //--- track 85 input
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output out86, //--- track 86 output
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input in87, //--- track 87 input
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output out88, //--- track 88 output
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input in89, //--- track 89 input
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output out90, //--- track 90 output
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input in91, //--- track 91 input
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output out92, //--- track 92 output
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input in93, //--- track 93 input
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output out94, //--- track 94 output
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input in95, //--- track 95 input
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output out96, //--- track 96 output
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input in97, //--- track 97 input
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output out98, //--- track 98 output
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input in99, //--- track 99 input
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output mid_out0, // Middle output 0 to logic blocks
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output mid_out1, // Middle output 1 to logic blocks
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output mid_out2, // Middle output 2 to logic blocks
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output mid_out3, // Middle output 3 to logic blocks
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output mid_out4, // Middle output 4 to logic blocks
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output mid_out5, // Middle output 5 to logic blocks
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output mid_out6, // Middle output 6 to logic blocks
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output mid_out7, // Middle output 7 to logic blocks
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output mid_out8, // Middle output 8 to logic blocks
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output mid_out9, // Middle output 9 to logic blocks
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output mid_out10, // Middle output 10 to logic blocks
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output mid_out11, // Middle output 11 to logic blocks
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output mid_out12, // Middle output 12 to logic blocks
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output mid_out13, // Middle output 13 to logic blocks
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output mid_out14, // Middle output 14 to logic blocks
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output mid_out15, // Middle output 15 to logic blocks
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output mid_out16, // Middle output 16 to logic blocks
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output mid_out17, // Middle output 17 to logic blocks
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output mid_out18, // Middle output 18 to logic blocks
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output mid_out19, // Middle output 19 to logic blocks
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output mid_out20, // Middle output 20 to logic blocks
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output mid_out21, // Middle output 21 to logic blocks
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output mid_out22, // Middle output 22 to logic blocks
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output mid_out23, // Middle output 23 to logic blocks
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output mid_out24, // Middle output 24 to logic blocks
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output mid_out25, // Middle output 25 to logic blocks
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output mid_out26, // Middle output 26 to logic blocks
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output mid_out27, // Middle output 27 to logic blocks
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output mid_out28, // Middle output 28 to logic blocks
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output mid_out29, // Middle output 29 to logic blocks
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output mid_out30, // Middle output 30 to logic blocks
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output mid_out31, // Middle output 31 to logic blocks
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output mid_out32, // Middle output 32 to logic blocks
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output mid_out33, // Middle output 33 to logic blocks
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output mid_out34, // Middle output 34 to logic blocks
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output mid_out35, // Middle output 35 to logic blocks
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output mid_out36, // Middle output 36 to logic blocks
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output mid_out37, // Middle output 37 to logic blocks
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output mid_out38, // Middle output 38 to logic blocks
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output mid_out39, // Middle output 39 to logic blocks
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output mid_out40, // Middle output 40 to logic blocks
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output mid_out41, // Middle output 41 to logic blocks
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output mid_out42, // Middle output 42 to logic blocks
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output mid_out43, // Middle output 43 to logic blocks
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output mid_out44, // Middle output 44 to logic blocks
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output mid_out45, // Middle output 45 to logic blocks
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output mid_out46, // Middle output 46 to logic blocks
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output mid_out47, // Middle output 47 to logic blocks
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output mid_out48, // Middle output 48 to logic blocks
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output mid_out49, // Middle output 49 to logic blocks
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output mid_out50, // Middle output 50 to logic blocks
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output mid_out51, // Middle output 51 to logic blocks
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output mid_out52, // Middle output 52 to logic blocks
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output mid_out53, // Middle output 53 to logic blocks
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output mid_out54, // Middle output 54 to logic blocks
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output mid_out55, // Middle output 55 to logic blocks
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output mid_out56, // Middle output 56 to logic blocks
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output mid_out57, // Middle output 57 to logic blocks
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output mid_out58, // Middle output 58 to logic blocks
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output mid_out59, // Middle output 59 to logic blocks
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output mid_out60, // Middle output 60 to logic blocks
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output mid_out61, // Middle output 61 to logic blocks
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output mid_out62, // Middle output 62 to logic blocks
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output mid_out63, // Middle output 63 to logic blocks
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output mid_out64, // Middle output 64 to logic blocks
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output mid_out65, // Middle output 65 to logic blocks
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output mid_out66, // Middle output 66 to logic blocks
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output mid_out67, // Middle output 67 to logic blocks
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output mid_out68, // Middle output 68 to logic blocks
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output mid_out69, // Middle output 69 to logic blocks
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output mid_out70, // Middle output 70 to logic blocks
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output mid_out71, // Middle output 71 to logic blocks
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output mid_out72, // Middle output 72 to logic blocks
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output mid_out73, // Middle output 73 to logic blocks
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output mid_out74, // Middle output 74 to logic blocks
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output mid_out75, // Middle output 75 to logic blocks
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output mid_out76, // Middle output 76 to logic blocks
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output mid_out77, // Middle output 77 to logic blocks
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output mid_out78, // Middle output 78 to logic blocks
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output mid_out79, // Middle output 79 to logic blocks
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output mid_out80, // Middle output 80 to logic blocks
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output mid_out81, // Middle output 81 to logic blocks
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output mid_out82, // Middle output 82 to logic blocks
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output mid_out83, // Middle output 83 to logic blocks
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output mid_out84, // Middle output 84 to logic blocks
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output mid_out85, // Middle output 85 to logic blocks
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output mid_out86, // Middle output 86 to logic blocks
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output mid_out87, // Middle output 87 to logic blocks
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output mid_out88, // Middle output 88 to logic blocks
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output mid_out89, // Middle output 89 to logic blocks
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output mid_out90, // Middle output 90 to logic blocks
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output mid_out91, // Middle output 91 to logic blocks
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output mid_out92, // Middle output 92 to logic blocks
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output mid_out93, // Middle output 93 to logic blocks
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output mid_out94, // Middle output 94 to logic blocks
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output mid_out95, // Middle output 95 to logic blocks
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output mid_out96, // Middle output 96 to logic blocks
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output mid_out97, // Middle output 97 to logic blocks
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output mid_out98, // Middle output 98 to logic blocks
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output mid_out99 // Middle output 99 to logic blocks
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);
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assign out0 = in0;
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assign mid_out0 = in0;
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assign out1 = in1;
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assign mid_out1 = in1;
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assign out2 = in2;
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assign mid_out2 = in2;
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assign out3 = in3;
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assign mid_out3 = in3;
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assign out4 = in4;
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assign mid_out4 = in4;
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assign out5 = in5;
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assign mid_out5 = in5;
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assign out6 = in6;
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assign mid_out6 = in6;
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assign out7 = in7;
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assign mid_out7 = in7;
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assign out8 = in8;
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assign mid_out8 = in8;
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assign out9 = in9;
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|
|
assign mid_out9 = in9;
|
||
|
|
assign out10 = in10;
|
||
|
|
assign mid_out10 = in10;
|
||
|
|
assign out11 = in11;
|
||
|
|
assign mid_out11 = in11;
|
||
|
|
assign out12 = in12;
|
||
|
|
assign mid_out12 = in12;
|
||
|
|
assign out13 = in13;
|
||
|
|
assign mid_out13 = in13;
|
||
|
|
assign out14 = in14;
|
||
|
|
assign mid_out14 = in14;
|
||
|
|
assign out15 = in15;
|
||
|
|
assign mid_out15 = in15;
|
||
|
|
assign out16 = in16;
|
||
|
|
assign mid_out16 = in16;
|
||
|
|
assign out17 = in17;
|
||
|
|
assign mid_out17 = in17;
|
||
|
|
assign out18 = in18;
|
||
|
|
assign mid_out18 = in18;
|
||
|
|
assign out19 = in19;
|
||
|
|
assign mid_out19 = in19;
|
||
|
|
assign out20 = in20;
|
||
|
|
assign mid_out20 = in20;
|
||
|
|
assign out21 = in21;
|
||
|
|
assign mid_out21 = in21;
|
||
|
|
assign out22 = in22;
|
||
|
|
assign mid_out22 = in22;
|
||
|
|
assign out23 = in23;
|
||
|
|
assign mid_out23 = in23;
|
||
|
|
assign out24 = in24;
|
||
|
|
assign mid_out24 = in24;
|
||
|
|
assign out25 = in25;
|
||
|
|
assign mid_out25 = in25;
|
||
|
|
assign out26 = in26;
|
||
|
|
assign mid_out26 = in26;
|
||
|
|
assign out27 = in27;
|
||
|
|
assign mid_out27 = in27;
|
||
|
|
assign out28 = in28;
|
||
|
|
assign mid_out28 = in28;
|
||
|
|
assign out29 = in29;
|
||
|
|
assign mid_out29 = in29;
|
||
|
|
assign out30 = in30;
|
||
|
|
assign mid_out30 = in30;
|
||
|
|
assign out31 = in31;
|
||
|
|
assign mid_out31 = in31;
|
||
|
|
assign out32 = in32;
|
||
|
|
assign mid_out32 = in32;
|
||
|
|
assign out33 = in33;
|
||
|
|
assign mid_out33 = in33;
|
||
|
|
assign out34 = in34;
|
||
|
|
assign mid_out34 = in34;
|
||
|
|
assign out35 = in35;
|
||
|
|
assign mid_out35 = in35;
|
||
|
|
assign out36 = in36;
|
||
|
|
assign mid_out36 = in36;
|
||
|
|
assign out37 = in37;
|
||
|
|
assign mid_out37 = in37;
|
||
|
|
assign out38 = in38;
|
||
|
|
assign mid_out38 = in38;
|
||
|
|
assign out39 = in39;
|
||
|
|
assign mid_out39 = in39;
|
||
|
|
assign out40 = in40;
|
||
|
|
assign mid_out40 = in40;
|
||
|
|
assign out41 = in41;
|
||
|
|
assign mid_out41 = in41;
|
||
|
|
assign out42 = in42;
|
||
|
|
assign mid_out42 = in42;
|
||
|
|
assign out43 = in43;
|
||
|
|
assign mid_out43 = in43;
|
||
|
|
assign out44 = in44;
|
||
|
|
assign mid_out44 = in44;
|
||
|
|
assign out45 = in45;
|
||
|
|
assign mid_out45 = in45;
|
||
|
|
assign out46 = in46;
|
||
|
|
assign mid_out46 = in46;
|
||
|
|
assign out47 = in47;
|
||
|
|
assign mid_out47 = in47;
|
||
|
|
assign out48 = in48;
|
||
|
|
assign mid_out48 = in48;
|
||
|
|
assign out49 = in49;
|
||
|
|
assign mid_out49 = in49;
|
||
|
|
assign out50 = in50;
|
||
|
|
assign mid_out50 = in50;
|
||
|
|
assign out51 = in51;
|
||
|
|
assign mid_out51 = in51;
|
||
|
|
assign out52 = in52;
|
||
|
|
assign mid_out52 = in52;
|
||
|
|
assign out53 = in53;
|
||
|
|
assign mid_out53 = in53;
|
||
|
|
assign out54 = in54;
|
||
|
|
assign mid_out54 = in54;
|
||
|
|
assign out55 = in55;
|
||
|
|
assign mid_out55 = in55;
|
||
|
|
assign out56 = in56;
|
||
|
|
assign mid_out56 = in56;
|
||
|
|
assign out57 = in57;
|
||
|
|
assign mid_out57 = in57;
|
||
|
|
assign out58 = in58;
|
||
|
|
assign mid_out58 = in58;
|
||
|
|
assign out59 = in59;
|
||
|
|
assign mid_out59 = in59;
|
||
|
|
assign out60 = in60;
|
||
|
|
assign mid_out60 = in60;
|
||
|
|
assign out61 = in61;
|
||
|
|
assign mid_out61 = in61;
|
||
|
|
assign out62 = in62;
|
||
|
|
assign mid_out62 = in62;
|
||
|
|
assign out63 = in63;
|
||
|
|
assign mid_out63 = in63;
|
||
|
|
assign out64 = in64;
|
||
|
|
assign mid_out64 = in64;
|
||
|
|
assign out65 = in65;
|
||
|
|
assign mid_out65 = in65;
|
||
|
|
assign out66 = in66;
|
||
|
|
assign mid_out66 = in66;
|
||
|
|
assign out67 = in67;
|
||
|
|
assign mid_out67 = in67;
|
||
|
|
assign out68 = in68;
|
||
|
|
assign mid_out68 = in68;
|
||
|
|
assign out69 = in69;
|
||
|
|
assign mid_out69 = in69;
|
||
|
|
assign out70 = in70;
|
||
|
|
assign mid_out70 = in70;
|
||
|
|
assign out71 = in71;
|
||
|
|
assign mid_out71 = in71;
|
||
|
|
assign out72 = in72;
|
||
|
|
assign mid_out72 = in72;
|
||
|
|
assign out73 = in73;
|
||
|
|
assign mid_out73 = in73;
|
||
|
|
assign out74 = in74;
|
||
|
|
assign mid_out74 = in74;
|
||
|
|
assign out75 = in75;
|
||
|
|
assign mid_out75 = in75;
|
||
|
|
assign out76 = in76;
|
||
|
|
assign mid_out76 = in76;
|
||
|
|
assign out77 = in77;
|
||
|
|
assign mid_out77 = in77;
|
||
|
|
assign out78 = in78;
|
||
|
|
assign mid_out78 = in78;
|
||
|
|
assign out79 = in79;
|
||
|
|
assign mid_out79 = in79;
|
||
|
|
assign out80 = in80;
|
||
|
|
assign mid_out80 = in80;
|
||
|
|
assign out81 = in81;
|
||
|
|
assign mid_out81 = in81;
|
||
|
|
assign out82 = in82;
|
||
|
|
assign mid_out82 = in82;
|
||
|
|
assign out83 = in83;
|
||
|
|
assign mid_out83 = in83;
|
||
|
|
assign out84 = in84;
|
||
|
|
assign mid_out84 = in84;
|
||
|
|
assign out85 = in85;
|
||
|
|
assign mid_out85 = in85;
|
||
|
|
assign out86 = in86;
|
||
|
|
assign mid_out86 = in86;
|
||
|
|
assign out87 = in87;
|
||
|
|
assign mid_out87 = in87;
|
||
|
|
assign out88 = in88;
|
||
|
|
assign mid_out88 = in88;
|
||
|
|
assign out89 = in89;
|
||
|
|
assign mid_out89 = in89;
|
||
|
|
assign out90 = in90;
|
||
|
|
assign mid_out90 = in90;
|
||
|
|
assign out91 = in91;
|
||
|
|
assign mid_out91 = in91;
|
||
|
|
assign out92 = in92;
|
||
|
|
assign mid_out92 = in92;
|
||
|
|
assign out93 = in93;
|
||
|
|
assign mid_out93 = in93;
|
||
|
|
assign out94 = in94;
|
||
|
|
assign mid_out94 = in94;
|
||
|
|
assign out95 = in95;
|
||
|
|
assign mid_out95 = in95;
|
||
|
|
assign out96 = in96;
|
||
|
|
assign mid_out96 = in96;
|
||
|
|
assign out97 = in97;
|
||
|
|
assign mid_out97 = in97;
|
||
|
|
assign out98 = in98;
|
||
|
|
assign mid_out98 = in98;
|
||
|
|
assign out99 = in99;
|
||
|
|
assign mid_out99 = in99;
|
||
|
|
endmodule
|
||
|
|
//----- END Verilog Module of Channel X [1][0] -----
|
||
|
|
|