32 lines
1.8 KiB
Plaintext
32 lines
1.8 KiB
Plaintext
|
# Standard Configuration Example
|
||
|
|
[dir_path]
|
||
|
|
script_base = ${PATH:OPENFPGA_PATH}/fpga_flow/scripts/
|
||
|
|
benchmark_dir = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/Verilog/MCNC/
|
||
|
|
yosys_path = /research/ece/lnis/USERS/alacchi/Current_release/branch_multimode/OpenFPGA/yosys/yosys
|
||
|
|
odin2_path = ${PATH:OPENFPGA_PATH}/fpga_flow/not_used_atm/odin2.exe
|
||
|
|
cirkit_path = ${PATH:OPENFPGA_PATH}/fpga_flow/not_used_atm/cirkit
|
||
|
|
abc_path = ${PATH:OPENFPGA_PATH}/yosys/yosys-abc
|
||
|
|
abc_mccl_path = ${PATH:OPENFPGA_PATH}/abc_with_bb_support/abc
|
||
|
|
abc_with_bb_support_path = ${PATH:OPENFPGA_PATH}/abc_with_bb_support/abc
|
||
|
|
mpack1_path = ${PATH:OPENFPGA_PATH}/fpga_flow/not_used_atm/mpack1
|
||
|
|
m2net_path = ${PATH:OPENFPGA_PATH}/fpga_flow/not_used_atm/m2net
|
||
|
|
mpack2_path = ${PATH:OPENFPGA_PATH}/fpga_flow/not_used_atm/mpack2
|
||
|
|
vpr_path = ${PATH:OPENFPGA_PATH}/vpr7_x2p/vpr/vpr
|
||
|
|
rpt_dir = /var/tmp/Openfpga/results
|
||
|
|
ace_path = ${PATH:OPENFPGA_PATH}/ace2/ace
|
||
|
|
|
||
|
|
[flow_conf]
|
||
|
|
#Flow Types standard|mpack2|mpack1|vtr_standard|vtr|yosys_vpr
|
||
|
|
flow_type = yosys_vpr
|
||
|
|
vpr_arch = ${PATH:OPENFPGA_PATH}/fpga_flow/arch/winbond90/k6_N10_rram_memory_bank_SC_winbond90.xml
|
||
|
|
mpack1_abc_stdlib = Not_Required
|
||
|
|
m2net_conf = Not_Required
|
||
|
|
mpack2_arch = Not_Required
|
||
|
|
power_tech_xml = ${PATH:OPENFPGA_PATH}/fpga_flow/tech/winbond90nm/winbond90nm_power_properties.xml
|
||
|
|
|
||
|
|
[csv_tags]
|
||
|
|
mpack1_tags = Global mapping efficiency: | efficiency: | occupancy wo buf: | efficiency wo buf:
|
||
|
|
mpack2_tags = BLE Number: | BLE Fill Rate:
|
||
|
|
vpr_tags = Netlist clb blocks: | Final critical path: | Total logic delay: | total net delay: | Total routing area: | Total used logic block area: | Total wirelength: | Packing took | Placement took | Routing took | Average net density: | Median net density: | Recommend no. of clock cycles:
|
||
|
|
vpr_power_tags = PB Types | Routing | Switch Box | Connection Box | Primitives | Interc Structures | lut6 | ff
|