2020-12-08 18:16:50 -06:00
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---
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name: Pull request
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about: Push a change to this project
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---
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2020-12-08 18:29:30 -06:00
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### Motivate of the pull request
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2020-12-08 18:16:50 -06:00
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- [ ] To address an existing issue. If so, please provide a link to the issue.
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- [ ] Breaking new feature. If so, please decribe details in the description part.
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2020-12-08 18:29:30 -06:00
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### Describe the technical details
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2020-12-08 18:16:50 -06:00
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- What is currently done? (Provide issue link if applicable)
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- What does this pull request change?
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2020-12-08 18:29:30 -06:00
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### Which part of the code base require a change
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2020-12-08 18:27:48 -06:00
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**In general, modification on existing submodules are not acceptable. You should push changes to upstream.**
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- [ ] VPR
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- [ ] OpenFPGA libraries
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- [ ] FPGA-Verilog
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- [ ] FPGA-Bitstream
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- [ ] FPGA-SDC
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- [ ] FPGA-SPICE
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- [ ] Flow scripts
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- [ ] Architecture library
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- [ ] Cell library
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2020-12-08 18:29:30 -06:00
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### Checklist of the pull request
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2020-12-08 18:27:48 -06:00
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- [ ] Require code changes.
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2020-12-08 18:16:50 -06:00
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- [ ] Require new tests to be added
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- [ ] Require an update on documentation
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2020-12-08 18:29:30 -06:00
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### Impact of the pull request
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2020-12-08 18:16:50 -06:00
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- [ ] Require a change on Quality of Results (QoR)
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2020-12-08 18:27:48 -06:00
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- [ ] Break back-compatibility. If so, please list who may be influenced.
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