riscv
/
OpenFPGA
mirror of https://github.com/lnis-uofu/OpenFPGA.git
1
0
Fork 0
Code Issues Projects Releases Wiki Activity
OpenFPGA/docs/source/fpga_verilog/file_organization.rst

3 lines
56 B
ReStructuredText
Raw Normal View History

Update a draft
2018-09-13 23:58:54 -05:00
Verilog Output File Format
Adding documentation
2018-09-13 16:38:41 -05:00
============================