107 lines
4.7 KiB
Coq
107 lines
4.7 KiB
Coq
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/////////////////////////////////////////////////////////////////////
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//// ////
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//// USB CRC5 and CRC16 Modules ////
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//// ////
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//// ////
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//// Author: Rudolf Usselmann ////
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//// rudi@asics.ws ////
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//// ////
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//// ////
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//// Downloaded from: http://www.opencores.org/cores/usb/ ////
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//// ////
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/////////////////////////////////////////////////////////////////////
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//// ////
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//// Copyright (C) 2000-2003 Rudolf Usselmann ////
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//// www.asics.ws ////
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//// rudi@asics.ws ////
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//// ////
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//// This source file may be used and distributed without ////
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//// restriction provided that this copyright statement is not ////
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//// removed from the file and that any derivative work contains ////
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//// the original copyright notice and the associated disclaimer.////
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//// ////
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//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ////
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//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ////
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//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ////
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//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ////
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//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ////
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//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ////
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//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ////
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//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ////
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//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ////
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//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ////
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//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ////
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//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ////
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//// POSSIBILITY OF SUCH DAMAGE. ////
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//// ////
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/////////////////////////////////////////////////////////////////////
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// CVS Log
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//
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// $Id: usbf_crc5.v,v 1.2 2003/10/17 02:36:57 rudi Exp $
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//
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// $Date: 2003/10/17 02:36:57 $
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// $Revision: 1.2 $
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// $Author: rudi $
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// $Locker: $
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// $State: Exp $
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//
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// Change History:
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// $Log: usbf_crc5.v,v $
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// Revision 1.2 2003/10/17 02:36:57 rudi
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// - Disabling bit stuffing and NRZI encoding during speed negotiation
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// - Now the core can send zero size packets
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// - Fixed register addresses for some of the higher endpoints
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// (conversion between decimal/hex was wrong)
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// - The core now does properly evaluate the function address to
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// determine if the packet was intended for it.
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// - Various other minor bugs and typos
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//
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// Revision 1.1 2001/08/03 05:30:09 rudi
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//
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//
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// 1) Reorganized directory structure
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//
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// Revision 1.0 2001/03/07 09:17:12 rudi
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//
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//
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// Changed all revisions to revision 1.0. This is because OpenCores CVS
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// interface could not handle the original '0.1' revision ....
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//
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// Revision 0.1.0.1 2001/02/28 08:10:42 rudi
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// Initial Release
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//
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//
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`include "usbf_defines.v"
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///////////////////////////////////////////////////////////////////
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//
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// CRC5
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//
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///////////////////////////////////////////////////////////////////
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module usbf_crc5(crc_in, din, crc_out);
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input [4:0] crc_in;
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input [10:0] din;
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output [4:0] crc_out;
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assign crc_out[0] = din[10] ^ din[9] ^ din[6] ^ din[5] ^ din[3] ^
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din[0] ^ crc_in[0] ^ crc_in[3] ^ crc_in[4];
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assign crc_out[1] = din[10] ^ din[7] ^ din[6] ^ din[4] ^ din[1] ^
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crc_in[0] ^ crc_in[1] ^ crc_in[4];
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assign crc_out[2] = din[10] ^ din[9] ^ din[8] ^ din[7] ^ din[6] ^
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din[3] ^ din[2] ^ din[0] ^ crc_in[0] ^ crc_in[1] ^
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crc_in[2] ^ crc_in[3] ^ crc_in[4];
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assign crc_out[3] = din[10] ^ din[9] ^ din[8] ^ din[7] ^ din[4] ^ din[3] ^
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din[1] ^ crc_in[1] ^ crc_in[2] ^ crc_in[3] ^ crc_in[4];
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assign crc_out[4] = din[10] ^ din[9] ^ din[8] ^ din[5] ^ din[4] ^ din[2] ^
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crc_in[2] ^ crc_in[3] ^ crc_in[4];
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endmodule
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