OpenFPGA/yosys/examples/smtbmc/demo6.v

15 lines
215 B
Coq
Raw Normal View History

// Demo for assertpmux
module demo6 (input A, B, C, D, E, output reg Y);
always @* begin
Y = 0;
if (A != B) begin
(* parallel_case *)
case (C)
A: Y = D;
B: Y = E;
endcase
end
end
endmodule