100 lines
2.3 KiB
Coq
100 lines
2.3 KiB
Coq
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// //
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// ERI summit demo-benchmark //
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// pipelined_8b_adder.v //
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// by Aurelien //
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// //
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/////////////////////////////////////
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//-----------------------------------------------------
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// Design Name : pipelined_8bit_adder
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// File Name : pipelined_8bit_adder.v
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// Function : Pipelined 8-bit adders, whose sum and carry outputs
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// are cached in a memory
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// Coder : Aurelien Alacchi
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//-----------------------------------------------------
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`timescale 1 ns/ 1 ps
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// To match the port definition in BLIF format, so that we can do verification
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// Each input/output bus is expanded here.
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// In future, we should be able to support buses in verification!
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module pipelined_8bit_adder(
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input clk,
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input ren,
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input wen,
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input raddr_0_,
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input raddr_1_,
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input raddr_2_,
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input raddr_3_,
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input raddr_4_,
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input raddr_5_,
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input waddr_0_,
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input waddr_1_,
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input waddr_2_,
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input waddr_3_,
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input waddr_4_,
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input waddr_5_,
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input a_0_,
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input a_1_,
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input a_2_,
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input a_3_,
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input a_4_,
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input a_5_,
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input a_6_,
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input b_0_,
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input b_1_,
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input b_2_,
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input b_3_,
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input b_4_,
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input b_5_,
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input b_6_,
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output q_0_,
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output q_1_,
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output q_2_,
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output q_3_,
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output q_4_,
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output q_5_,
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output q_6_,
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output q_7_);
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wire [5:0] raddr = { raddr_5_, raddr_4_, raddr_3_, raddr_2_, raddr_1_, raddr_0_ };
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wire [5:0] waddr = { waddr_5_, waddr_4_, waddr_3_, waddr_2_, waddr_1_, waddr_0_ };
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wire [6:0] a = { a_6_, a_5_, a_4_, a_3_, a_2_, a_1_, a_0_ };
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wire [6:0] b = { b_6_, b_5_, b_4_, b_3_, b_2_, b_1_, b_0_ };
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wire [7:0] q = { q_7_, q_6_, q_5_, q_4_, q_3_, q_2_, q_1_, q_0_ };
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reg[7:0] ram[63:0];
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reg[6:0] a_st0;
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reg[6:0] a_st1;
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reg[6:0] b_st0;
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reg[6:0] b_st1;
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reg[8:0] waddr_st0;
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reg[8:0] waddr_st1;
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reg wen_st0;
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reg wen_st1;
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reg[7:0] q_int;
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wire[7:0] AplusB;
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assign AplusB = a_st1 + b_st1;
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assign q = q_int;
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always@(posedge clk) begin
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waddr_st0 <= waddr;
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waddr_st1 <= waddr_st0;
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a_st0 <= a;
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a_st1 <= a_st0;
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b_st0 <= b;
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b_st1 <= b_st0;
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wen_st0 <= wen;
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wen_st1 <= wen_st0;
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if(wen_st1) begin
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ram[waddr_st1] <= AplusB;
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end
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if(ren) begin
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q_int <= ram[raddr];
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end
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end
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endmodule
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