227 lines
6.9 KiB
C++
227 lines
6.9 KiB
C++
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/*
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* yosys -- Yosys Open SYnthesis Suite
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*
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* Copyright (C) 2012 Clifford Wolf <clifford@clifford.at>
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*
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* Permission to use, copy, modify, and/or distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*
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*/
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#include "kernel/yosys.h"
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#include "kernel/sigtools.h"
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USING_YOSYS_NAMESPACE
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PRIVATE_NAMESPACE_BEGIN
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struct Clk2fflogicPass : public Pass {
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Clk2fflogicPass() : Pass("clk2fflogic", "convert clocked FFs to generic $ff cells") { }
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virtual void help()
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{
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// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
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log("\n");
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log(" clk2fflogic [options] [selection]\n");
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log("\n");
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log("This command replaces clocked flip-flops with generic $ff cells that use the\n");
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log("implicit global clock. This is useful for formal verification of designs with\n");
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log("multiple clocks.\n");
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log("\n");
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}
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virtual void execute(std::vector<std::string> args, RTLIL::Design *design)
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{
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// bool flag_noinit = false;
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log_header(design, "Executing CLK2FFLOGIC pass (convert clocked FFs to generic $ff cells).\n");
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size_t argidx;
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for (argidx = 1; argidx < args.size(); argidx++)
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{
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// if (args[argidx] == "-noinit") {
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// flag_noinit = true;
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// continue;
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// }
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break;
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}
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extra_args(args, argidx, design);
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for (auto module : design->selected_modules())
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{
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SigMap sigmap(module);
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dict<SigBit, State> initbits;
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pool<SigBit> del_initbits;
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for (auto wire : module->wires())
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if (wire->attributes.count("\\init") > 0)
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{
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Const initval = wire->attributes.at("\\init");
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SigSpec initsig = sigmap(wire);
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for (int i = 0; i < GetSize(initval) && i < GetSize(initsig); i++)
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if (initval[i] == State::S0 || initval[i] == State::S1)
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initbits[initsig[i]] = initval[i];
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}
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for (auto cell : vector<Cell*>(module->selected_cells()))
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{
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if (cell->type.in("$dlatch"))
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{
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bool enpol = cell->parameters["\\EN_POLARITY"].as_bool();
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SigSpec sig_en = cell->getPort("\\EN");
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SigSpec sig_d = cell->getPort("\\D");
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SigSpec sig_q = cell->getPort("\\Q");
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log("Replacing %s.%s (%s): EN=%s, D=%s, Q=%s\n",
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log_id(module), log_id(cell), log_id(cell->type),
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log_signal(sig_en), log_signal(sig_d), log_signal(sig_q));
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Wire *past_q = module->addWire(NEW_ID, GetSize(sig_q));
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module->addFf(NEW_ID, sig_q, past_q);
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if (enpol)
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module->addMux(NEW_ID, past_q, sig_d, sig_en, sig_q);
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else
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module->addMux(NEW_ID, sig_d, past_q, sig_en, sig_q);
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Const initval;
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bool assign_initval = false;
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for (int i = 0; i < GetSize(sig_d); i++) {
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SigBit qbit = sigmap(sig_q[i]);
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if (initbits.count(qbit)) {
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initval.bits.push_back(initbits.at(qbit));
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del_initbits.insert(qbit);
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} else
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initval.bits.push_back(State::Sx);
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if (initval.bits.back() != State::Sx)
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assign_initval = true;
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}
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if (assign_initval)
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past_q->attributes["\\init"] = initval;
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module->remove(cell);
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continue;
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}
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if (cell->type.in("$dff", "$adff", "$dffsr"))
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{
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bool clkpol = cell->parameters["\\CLK_POLARITY"].as_bool();
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SigSpec clk = cell->getPort("\\CLK");
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Wire *past_clk = module->addWire(NEW_ID);
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past_clk->attributes["\\init"] = clkpol ? State::S1 : State::S0;
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module->addFf(NEW_ID, clk, past_clk);
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SigSpec sig_d = cell->getPort("\\D");
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SigSpec sig_q = cell->getPort("\\Q");
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log("Replacing %s.%s (%s): CLK=%s, D=%s, Q=%s\n",
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log_id(module), log_id(cell), log_id(cell->type),
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log_signal(clk), log_signal(sig_d), log_signal(sig_q));
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SigSpec clock_edge_pattern;
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if (clkpol) {
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clock_edge_pattern.append_bit(State::S0);
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clock_edge_pattern.append_bit(State::S1);
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} else {
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clock_edge_pattern.append_bit(State::S1);
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clock_edge_pattern.append_bit(State::S0);
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}
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SigSpec clock_edge = module->Eqx(NEW_ID, {clk, SigSpec(past_clk)}, clock_edge_pattern);
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Wire *past_d = module->addWire(NEW_ID, GetSize(sig_d));
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Wire *past_q = module->addWire(NEW_ID, GetSize(sig_q));
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module->addFf(NEW_ID, sig_d, past_d);
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module->addFf(NEW_ID, sig_q, past_q);
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if (cell->type == "$adff")
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{
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SigSpec arst = cell->getPort("\\ARST");
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SigSpec qval = module->Mux(NEW_ID, past_q, past_d, clock_edge);
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Const rstval = cell->parameters["\\ARST_VALUE"];
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if (cell->parameters["\\ARST_POLARITY"].as_bool())
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module->addMux(NEW_ID, qval, rstval, arst, sig_q);
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else
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module->addMux(NEW_ID, rstval, qval, arst, sig_q);
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}
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else
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if (cell->type == "$dffsr")
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{
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SigSpec qval = module->Mux(NEW_ID, past_q, past_d, clock_edge);
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SigSpec setval = cell->getPort("\\SET");
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SigSpec clrval = cell->getPort("\\CLR");
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if (!cell->parameters["\\SET_POLARITY"].as_bool())
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setval = module->Not(NEW_ID, setval);
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if (cell->parameters["\\CLR_POLARITY"].as_bool())
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clrval = module->Not(NEW_ID, clrval);
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qval = module->Or(NEW_ID, qval, setval);
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module->addAnd(NEW_ID, qval, clrval, sig_q);
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}
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else
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{
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module->addMux(NEW_ID, past_q, past_d, clock_edge, sig_q);
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}
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Const initval;
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bool assign_initval = false;
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for (int i = 0; i < GetSize(sig_d); i++) {
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SigBit qbit = sigmap(sig_q[i]);
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if (initbits.count(qbit)) {
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initval.bits.push_back(initbits.at(qbit));
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del_initbits.insert(qbit);
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} else
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initval.bits.push_back(State::Sx);
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if (initval.bits.back() != State::Sx)
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assign_initval = true;
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}
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if (assign_initval) {
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past_d->attributes["\\init"] = initval;
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past_q->attributes["\\init"] = initval;
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}
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module->remove(cell);
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continue;
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}
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}
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for (auto wire : module->wires())
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if (wire->attributes.count("\\init") > 0)
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{
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bool delete_initattr = true;
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Const initval = wire->attributes.at("\\init");
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SigSpec initsig = sigmap(wire);
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for (int i = 0; i < GetSize(initval) && i < GetSize(initsig); i++)
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if (del_initbits.count(initsig[i]) > 0)
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initval[i] = State::Sx;
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else if (initval[i] != State::Sx)
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delete_initattr = false;
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if (delete_initattr)
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wire->attributes.erase("\\init");
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else
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wire->attributes.at("\\init") = initval;
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}
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}
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}
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} Clk2fflogicPass;
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PRIVATE_NAMESPACE_END
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