2018-10-03 18:10:29 -05:00
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<architecture>
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<!--
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ODIN II specific config begins
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Describes the types of user-specified netlist blocks (in blif, this corresponds to
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".model [type_of_block]") that this architecture supports.
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Note: Basic LUTs, I/Os, and flip-flops are not included here as there are
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already special structures in blif (.names, .input, .output, and .latch)
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that describe them.
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-->
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<models>
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<model name="io">
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<input_ports>
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<port name="outpad"/>
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</input_ports>
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<output_ports>
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<port name="inpad"/>
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</output_ports>
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</model>
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</models>
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<!-- ODIN II specific config ends -->
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<!-- Physical descriptions begin -->
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<layout auto="1.0"/>
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2018-11-14 15:01:39 -06:00
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<!-- <layout width="3" height="3"/> -->
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2018-10-03 18:10:29 -05:00
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<spice_settings>
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<parameters>
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<options sim_temp="25" post="off" captab="off" fast="on"/>
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<!-- Used only when doing monte_carlo simulations
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<monte_carlo mc_sim="off" num_mc_points="2" cmos_variation="off" rram_variation="off">
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<cmos abs_variation="0.1" num_sigma="3"/>
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<rram abs_variation="0.1" num_sigma="3"/>
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</monte_carlo>
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-->
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<measure sim_num_clock_cycle="auto" accuracy="1e-13" accuracy_type="abs">
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<slew>
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<rise upper_thres_pct="0.95" lower_thres_pct="0.05"/>
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<fall upper_thres_pct="0.05" lower_thres_pct="0.95"/>
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</slew>
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<delay>
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<rise input_thres_pct="0.5" output_thres_pct="0.5"/>
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<fall input_thres_pct="0.5" output_thres_pct="0.5"/>
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</delay>
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</measure>
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<stimulate>
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<clock op_freq="auto" sim_slack="0.2" prog_freq="2.5e6">
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<rise slew_time="20e-12" slew_type="abs"/>
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<fall slew_time="20e-12" slew_type="abs"/>
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</clock>
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<input>
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<rise slew_time="25e-12" slew_type="abs"/>
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<fall slew_time="25e-12" slew_type="abs"/>
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</input>
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</stimulate>
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</parameters>
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<tech_lib lib_type="industry" transistor_type="TOP_TT" lib_path="/research/ece/lnis/USERS/tang/tangxifan-eda-tools/branches/subvt_fpga/process/tsmc40nm/toplevel.l" nominal_vdd="0.9" io_vdd="2.5"/>
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<transistors pn_ratio="2" model_ref="M">
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<nmos model_name="nch" chan_length="40e-9" min_width="140e-9"/>
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<pmos model_name="pch" chan_length="40e-9" min_width="140e-9"/>
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<io_nmos model_name="nch_25" chan_length="270e-9" min_width="320e-9"/>
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<io_pmos model_name="pch_25" chan_length="270e-9" min_width="320e-9"/>
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</transistors>
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<module_circuit_models>
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<circuit_model type="inv_buf" name="INVTX1" prefix="INVTX1" is_default="1">
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<design_technology type="cmos" topology="inverter" size="1" tapered="off"/>
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<port type="input" prefix="in" size="1"/>
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<port type="output" prefix="out" size="1"/>
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</circuit_model>
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<circuit_model type="inv_buf" name="buf4" prefix="buf4" is_default="0">
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<design_technology type="cmos" topology="buffer" size="1" tapered="on" tap_drive_level="2" f_per_stage="4"/>
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<port type="input" prefix="in" size="1"/>
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<port type="output" prefix="out" size="1"/>
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</circuit_model>
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<circuit_model type="inv_buf" name="tap_buf4" prefix="tap_buf4" is_default="0">
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<design_technology type="cmos" topology="buffer" size="1" tapered="on" tap_drive_level="3" f_per_stage="4"/>
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<port type="input" prefix="in" size="1"/>
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<port type="output" prefix="out" size="1"/>
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</circuit_model>
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<circuit_model type="pass_gate" name="TGATE" prefix="TGATE" is_default="1">
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<design_technology type="cmos" topology="transmission_gate" nmos_size="1" pmos_size="2"/>
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<input_buffer exist="off"/>
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<output_buffer exist="off"/>
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<port type="input" prefix="in" size="1"/>
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<port type="input" prefix="sel" size="1"/>
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<port type="input" prefix="selb" size="1"/>
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<port type="output" prefix="out" size="1"/>
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2018-11-14 15:01:39 -06:00
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</circuit_model>
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<circuit_model type="chan_wire" name="chan_segment" prefix="track_seg" is_default="1">
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2018-10-03 18:10:29 -05:00
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<design_technology type="cmos"/>
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<input_buffer exist="off"/>
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<output_buffer exist="off"/>
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<port type="input" prefix="in" size="1"/>
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<port type="output" prefix="out" size="1"/>
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<wire_param model_type="pie" res_val="101" cap_val="22.5e-15" level="1"/> <!-- model_type could be T, res_val and cap_val DON'T CARE -->
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</circuit_model>
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<circuit_model type="wire" name="direct_interc" prefix="direct_interc" is_default="1">
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2018-10-03 18:10:29 -05:00
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<design_technology type="cmos"/>
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<input_buffer exist="off"/>
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<output_buffer exist="off"/>
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<port type="input" prefix="in" size="1"/>
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<port type="output" prefix="out" size="1"/>
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<wire_param model_type="pie" res_val="0" cap_val="0" level="1"/> <!-- model_type could be T, res_val cap_val should be defined -->
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2018-11-14 15:01:39 -06:00
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</circuit_model>
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<circuit_model type="mux" name="mux_1level_tapbuf" prefix="mux_1level_tapbuf" dump_structural_verilog="true">
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<design_technology type="cmos" structure="one-level"/>
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<input_buffer exist="on" circuit_model_name="INVTX1"/>
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<output_buffer exist="on" circuit_model_name="tap_buf4"/>
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<!--mux2to1 subckt_name="mux2to1"/-->
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<pass_gate_logic circuit_model_name="TGATE"/>
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<port type="input" prefix="in" size="1"/>
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<port type="output" prefix="out" size="1"/>
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<port type="sram" prefix="sram" size="1"/>
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</circuit_model>
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<circuit_model type="mux" name="mux_2level" prefix="mux_2level" is_default="1" dump_structural_verilog="true">
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2018-10-03 18:10:29 -05:00
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<design_technology type="cmos" structure="multi-level" num_level="2"/>
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2018-11-14 15:01:39 -06:00
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<input_buffer exist="on" circuit_model_name="INVTX1"/>
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<output_buffer exist="on" circuit_model_name="INVTX1"/>
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2018-10-03 18:10:29 -05:00
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<!--mux2to1 subckt_name="mux2to1"/-->
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2018-11-14 15:01:39 -06:00
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<pass_gate_logic circuit_model_name="TGATE"/>
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2018-10-03 18:10:29 -05:00
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<port type="input" prefix="in" size="1"/>
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<port type="output" prefix="out" size="1"/>
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<port type="sram" prefix="sram" size="1"/>
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2018-11-14 15:01:39 -06:00
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</circuit_model>
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<circuit_model type="mux" name="mux_2level_tapbuf" prefix="mux_2level_tapbuf" dump_structural_verilog="true">
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<design_technology type="cmos" structure="multi-level" num_level="2"/>
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<input_buffer exist="on" circuit_model_name="INVTX1"/>
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<output_buffer exist="on" circuit_model_name="tap_buf4"/>
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<!--mux2to1 subckt_name="mux2to1"/-->
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<pass_gate_logic circuit_model_name="TGATE"/>
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<port type="input" prefix="in" size="1"/>
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<port type="output" prefix="out" size="1"/>
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<port type="sram" prefix="sram" size="1"/>
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</circuit_model>
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2018-10-03 18:10:29 -05:00
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2018-11-14 15:01:39 -06:00
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<circuit_model type="ff" name="static_dff" prefix="dff" spice_netlist="/research/ece/lnis/USERS/tang/tangxifan-eda-tools/branches/vpr7_rram/vpr/SpiceNetlists/ff.sp" verilog_netlist="/research/ece/lnis/USERS/tang/tangxifan-eda-tools/branches/vpr7_rram/vpr/VerilogNetlists/ff.v">
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2018-10-03 18:10:29 -05:00
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<design_technology type="cmos"/>
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2018-11-14 15:01:39 -06:00
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<input_buffer exist="on" circuit_model_name="INVTX1"/>
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<output_buffer exist="on" circuit_model_name="INVTX1"/>
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<pass_gate_logic circuit_model_name="TGATE"/>
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2018-10-03 18:10:29 -05:00
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<port type="input" prefix="D" size="1"/>
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<port type="input" prefix="Set" size="1" is_global="true" default_val="0" is_set="true"/>
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<port type="input" prefix="Reset" size="1" is_global="true" default_val="0" is_reset="true"/>
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<port type="output" prefix="Q" size="1"/>
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<port type="clock" prefix="clk" size="1" is_global="true" default_val="0" />
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2018-11-14 15:01:39 -06:00
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</circuit_model>
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<circuit_model type="lut" name="lut4" prefix="lut4" dump_structural_verilog="true">
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2018-10-03 18:10:29 -05:00
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<design_technology type="cmos"/>
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2018-11-14 15:01:39 -06:00
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<input_buffer exist="on" circuit_model_name="INVTX1"/>
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<output_buffer exist="on" circuit_model_name="INVTX1"/>
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<lut_input_buffer exist="on" circuit_model_name="buf4"/>
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<pass_gate_logic circuit_model_name="TGATE"/>
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2018-10-03 18:10:29 -05:00
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<port type="input" prefix="in" size="4"/>
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<port type="output" prefix="out" size="1"/>
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<port type="sram" prefix="sram" size="16"/>
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2018-11-14 15:01:39 -06:00
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</circuit_model>
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<circuit_model type="sram" name="sram6T" prefix="sram" spice_netlist="/research/ece/lnis/USERS/tang/tangxifan-eda-tools/branches/vpr7_rram/vpr/SpiceNetlists/sram.sp" verilog_netlist="/research/ece/lnis/USERS/tang/tangxifan-eda-tools/branches/vpr7_rram/vpr/VerilogNetlists/sram.v" >
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2018-10-03 18:10:29 -05:00
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<design_technology type="cmos"/>
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2018-11-14 15:01:39 -06:00
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<input_buffer exist="on" circuit_model_name="INVTX1"/>
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<output_buffer exist="on" circuit_model_name="INVTX1"/>
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<pass_gate_logic circuit_model_name="TGATE"/>
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2018-10-03 18:10:29 -05:00
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<port type="input" prefix="in" size="1"/>
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<port type="output" prefix="out" size="2"/>
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2018-11-14 15:01:39 -06:00
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</circuit_model>
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<circuit_model type="sram" name="sram6T_blwl" prefix="sram_blwl" spice_netlist="/research/ece/lnis/USERS/tang/tangxifan-eda-tools/branches/vpr7_rram/vpr/SpiceNetlists/sram.sp" verilog_netlist="/research/ece/lnis/USERS/tang/tangxifan-eda-tools/branches/vpr7_rram/vpr/VerilogNetlists/sram.v">
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2018-10-03 18:10:29 -05:00
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<design_technology type="cmos"/>
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2018-11-14 15:01:39 -06:00
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<input_buffer exist="on" circuit_model_name="INVTX1"/>
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<output_buffer exist="on" circuit_model_name="INVTX1"/>
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<pass_gate_logic circuit_model_name="TGATE"/>
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2018-10-03 18:10:29 -05:00
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<port type="input" prefix="in" size="1"/>
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<port type="output" prefix="out" size="2"/>
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2018-11-14 15:01:39 -06:00
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<port type="bl" prefix="bl" size="1" default_val="0" inv_circuit_model_name="INVTX1"/>
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<port type="blb" prefix="blb" size="1" default_val="1" inv_circuit_model_name="INVTX1"/>
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<port type="wl" prefix="wl" size="1" default_val="0" inv_circuit_model_name="INVTX1"/>
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</circuit_model>
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<circuit_model type="iopad" name="iopad" prefix="iopad" spice_netlist="/research/ece/lnis/USERS/tang/tangxifan-eda-tools/branches/vpr7_rram/vpr/SpiceNetlists/io.sp" verilog_netlist="/research/ece/lnis/USERS/tang/tangxifan-eda-tools/branches/vpr7_rram/vpr/VerilogNetlists/io.v">
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<design_technology type="cmos"/>
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<input_buffer exist="on" circuit_model_name="INVTX1"/>
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<output_buffer exist="on" circuit_model_name="INVTX1"/>
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<pass_gate_logic circuit_model_name="TGATE"/>
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<port type="inout" prefix="pad" size="1"/>
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<port type="sram" prefix="en" size="1" mode_select="true" circuit_model_name="sram6T_blwl" default_val="1"/>
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2018-10-03 18:10:29 -05:00
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<port type="input" prefix="outpad" size="1"/>
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<port type="input" prefix="zin" size="1" is_global="true" default_val="0" />
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<port type="output" prefix="inpad" size="1"/>
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2018-11-14 15:01:39 -06:00
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</circuit_model>
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</module_circuit_models>
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2018-10-03 18:10:29 -05:00
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</spice_settings>
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<device>
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<sizing R_minW_nmos="8926" R_minW_pmos="16067" ipin_mux_trans_size="9"/>
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<timing C_ipin_cblock="596e-18" T_ipin_cblock="77.93e-12"/>
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<area grid_logic_tile_area="0"/>
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<sram area="6">
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<verilog organization="memory_bank" circuit_model_name="sram6T_blwl"/>
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<spice organization="standalone" circuit_model_name="sram6T" />
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2018-10-03 18:10:29 -05:00
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</sram>
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<chan_width_distr>
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<io width="1.000000"/>
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<x distr="uniform" peak="1.000000"/>
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<y distr="uniform" peak="1.000000"/>
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</chan_width_distr>
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<switch_block type="wilton" fs="3"/>
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</device>
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<cblocks>
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2018-11-14 15:01:39 -06:00
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<switch type="mux" name="cb_mux" R="0" Cin="596e-18" Cout="0" Tdel="77.93e-12" mux_trans_size="3" buf_size="63" circuit_model_name="mux_2level_tapbuf" structure="multi-level" num_level="2">
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</switch>
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</cblocks>
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<switchlist>
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<switch type="mux" name="sb_mux_L4" R="128" Cin="596e-18" Cout="0e-15" Tdel="47.2e-12" mux_trans_size="3" buf_size="63" circuit_model_name="mux_1level_tapbuf" structure="multi-level" num_level="1">
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</switch>
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</switchlist>
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<segmentlist>
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<segment freq="0.4" length="4" type="unidir" Rmetal="101" Cmetal="22.5e-15" circuit_model_name="chan_segment">
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<mux name="sb_mux_L4"/>
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<sb type="pattern">1 1 1 1 1</sb>
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<cb type="pattern">1 1 1 1</cb>
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</segment>
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2018-11-14 15:01:39 -06:00
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<segment freq="0.3" length="2" type="unidir" Rmetal="101" Cmetal="22.5e-15" circuit_model_name="chan_segment">
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2018-10-03 18:10:29 -05:00
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<mux name="sb_mux_L4"/>
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<sb type="pattern">1 1 1</sb>
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<cb type="pattern">1 1 </cb>
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</segment>
|
2018-11-14 15:01:39 -06:00
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<segment freq="0.3" length="1" type="unidir" Rmetal="101" Cmetal="22.5e-15" circuit_model_name="chan_segment">
|
2018-10-03 18:10:29 -05:00
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<mux name="sb_mux_L4"/>
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<sb type="pattern">1 1</sb>
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<cb type="pattern">1</cb>
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</segment>
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</segmentlist>
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<complexblocklist>
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<pb_type name="io" capacity="8" area="0" idle_mode_name="inpad" physical_mode_name="io_phy">
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<input name="outpad" num_pins="1"/>
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<output name="inpad" num_pins="1"/>
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<!-- physical design description -->
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<mode name="io_phy" disabled_in_packing="false">
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2018-11-14 15:01:39 -06:00
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<pb_type name="iopad" blif_model=".subckt io" num_pb="1" circuit_model_name="iopad">
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2018-10-03 18:10:29 -05:00
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<input name="outpad" num_pins="1"/>
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<output name="inpad" num_pins="1"/>
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</pb_type>
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<interconnect>
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<direct name="inpad" input="iopad.inpad" output="io.inpad">
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<delay_constant max="0e-11" in_port="iopad.inpad" out_port="io.inpad"/>
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</direct>
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<direct name="outpad" input="io.outpad" output="iopad.outpad">
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|
<delay_constant max="0e-11" in_port="io.outpad" out_port="iopad.outpad"/>
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</direct>
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</interconnect>
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</mode>
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<mode name="inpad">
|
2018-11-14 15:01:39 -06:00
|
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|
<pb_type name="inpad" blif_model=".input" num_pb="1" circuit_model_name="iopad" mode_bits="1">
|
2018-10-03 18:10:29 -05:00
|
|
|
<output name="inpad" num_pins="1"/>
|
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|
|
|
</pb_type>
|
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|
|
<interconnect>
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|
|
<direct name="inpad" input="inpad.inpad" output="io.inpad">
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|
|
|
<delay_constant max="0e-11" in_port="inpad.inpad" out_port="io.inpad"/>
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|
</direct>
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|
</interconnect>
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|
</mode>
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|
|
<mode name="outpad">
|
2018-11-14 15:01:39 -06:00
|
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|
<pb_type name="outpad" blif_model=".output" num_pb="1" circuit_model_name="iopad" mode_bits="0">
|
2018-10-03 18:10:29 -05:00
|
|
|
<input name="outpad" num_pins="1"/>
|
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|
|
|
</pb_type>
|
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|
|
<interconnect>
|
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|
|
<direct name="outpad" input="io.outpad" output="outpad.outpad">
|
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|
|
|
<delay_constant max="0e-11" in_port="io.outpad" out_port="outpad.outpad"/>
|
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|
|
</direct>
|
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|
</interconnect>
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|
</mode>
|
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|
|
|
<!-- Every input pin is driven by 15% of the tracks in a channel, every output pin is driven by 10% of the tracks in a channel -->
|
|
|
|
|
<fc default_in_type="frac" default_in_val="0.15" default_out_type="frac" default_out_val="0.10"/>
|
|
|
|
|
|
|
|
|
|
<!-- IOs go on the periphery of the FPGA, for consistency,
|
|
|
|
|
make it physically equivalent on all sides so that only one definition of I/Os is needed.
|
|
|
|
|
If I do not make a physically equivalent definition, then I need to define 4 different I/Os, one for each side of the FPGA
|
|
|
|
|
-->
|
|
|
|
|
<pinlocations pattern="custom">
|
|
|
|
|
<loc side="left">io.outpad io.inpad</loc>
|
|
|
|
|
<loc side="top">io.outpad io.inpad</loc>
|
|
|
|
|
<loc side="right">io.outpad io.inpad</loc>
|
|
|
|
|
<loc side="bottom">io.outpad io.inpad</loc>
|
|
|
|
|
</pinlocations>
|
|
|
|
|
|
|
|
|
|
<!-- Place I/Os on the sides of the FPGA -->
|
|
|
|
|
<gridlocations>
|
|
|
|
|
<loc type="perimeter" priority="10"/>
|
|
|
|
|
</gridlocations>
|
|
|
|
|
|
|
|
|
|
<power method="ignore"/>
|
|
|
|
|
</pb_type>
|
|
|
|
|
<!-- Define I/O pads ends -->
|
|
|
|
|
|
|
|
|
|
<!-- In this example, to keep the design as simple as possible, we
|
|
|
|
|
create a CLB with only a BLE and no feedback-->
|
|
|
|
|
<pb_type name="clb" area="53894" opin_to_cb="false">
|
|
|
|
|
<pin_equivalence_auto_detect input_ports ="off" output_ports="off"/>
|
|
|
|
|
<input name="I" num_pins="4" equivalent="true"/>
|
|
|
|
|
<output name="O" num_pins="1" equivalent="false"/>
|
|
|
|
|
<clock name="clk" num_pins="1"/>
|
|
|
|
|
|
|
|
|
|
<!-- fle basically refers to a slice. In this example, we just want one of them but we
|
|
|
|
|
leave it in so that we know this architecture can and should be used -->
|
|
|
|
|
<pb_type name="fle" num_pb="1" idle_mode_name="n1_lut4" physical_mode_name="n1_lut4">
|
|
|
|
|
<input name="in" num_pins="4"/>
|
|
|
|
|
<output name="out" num_pins="1"/>
|
|
|
|
|
<clock name="clk" num_pins="1"/>
|
|
|
|
|
<!-- 4-LUT mode definition begin -->
|
|
|
|
|
<mode name="n1_lut4">
|
|
|
|
|
<!-- Define 4-LUT mode -->
|
|
|
|
|
<pb_type name="ble4" num_pb="1">
|
|
|
|
|
<input name="in" num_pins="4"/>
|
|
|
|
|
<output name="out" num_pins="1"/>
|
|
|
|
|
<clock name="clk" num_pins="1"/>
|
|
|
|
|
|
|
|
|
|
<!-- Define LUT -->
|
2018-11-14 15:01:39 -06:00
|
|
|
<pb_type name="lut4" blif_model=".names" num_pb="1" class="lut" circuit_model_name="lut4">
|
2018-10-03 18:10:29 -05:00
|
|
|
<input name="in" num_pins="4" port_class="lut_in"/>
|
|
|
|
|
<output name="out" num_pins="1" port_class="lut_out"/>
|
|
|
|
|
<!-- LUT timing using delay matrix, one delay per input -->
|
|
|
|
|
<delay_matrix type="max" in_port="lut4.in" out_port="lut4.out">
|
|
|
|
|
127e-12
|
|
|
|
|
127e-12
|
|
|
|
|
127e-12
|
|
|
|
|
127e-12
|
|
|
|
|
</delay_matrix>
|
|
|
|
|
</pb_type>
|
|
|
|
|
|
|
|
|
|
<!-- Define flip-flop -->
|
2018-11-14 15:01:39 -06:00
|
|
|
<pb_type name="ff" blif_model=".latch" num_pb="1" class="flipflop" circuit_model_name="static_dff">
|
2018-10-03 18:10:29 -05:00
|
|
|
<input name="D" num_pins="1" port_class="D"/>
|
|
|
|
|
<output name="Q" num_pins="1" port_class="Q"/>
|
|
|
|
|
<clock name="clk" num_pins="1" port_class="clock"/>
|
|
|
|
|
<T_setup value="29e-12" port="ff.D" clock="clk"/>
|
|
|
|
|
<T_clock_to_Q max="16e-12" port="ff.Q" clock="clk"/>
|
|
|
|
|
</pb_type>
|
|
|
|
|
|
|
|
|
|
<interconnect>
|
|
|
|
|
<direct name="direct1" input="ble4.in" output="lut4[0:0].in"/>
|
|
|
|
|
<direct name="direct2" input="lut4.out" output="ff.D">
|
|
|
|
|
<!-- Advanced user option that tells CAD tool to find LUT+FF pairs in netlist
|
|
|
|
|
<pack_pattern name="ble6" in_port="lut6.out" out_port="ff.D"/> -->
|
|
|
|
|
</direct>
|
|
|
|
|
<direct name="direct3" input="ble4.clk" output="ff.clk"/>
|
2018-11-14 15:01:39 -06:00
|
|
|
<mux name="mux1" input="ff.Q lut4.out" output="ble4.out" circuit_model_name="mux_1level_tapbuf">
|
2018-10-03 18:10:29 -05:00
|
|
|
<delay_constant max="42.06e-12" in_port="lut4.out" out_port="ble4.out" />
|
|
|
|
|
<delay_constant max="42.06e-12" in_port="ff.Q" out_port="ble4.out" />
|
|
|
|
|
</mux>
|
|
|
|
|
</interconnect>
|
|
|
|
|
</pb_type>
|
|
|
|
|
<interconnect>
|
|
|
|
|
<direct name="direct1" input="fle.in" output="ble4.in"/>
|
|
|
|
|
<direct name="direct2" input="ble4.out" output="fle.out[0:0]"/>
|
|
|
|
|
<direct name="direct3" input="fle.clk" output="ble4.clk"/>
|
|
|
|
|
</interconnect>
|
|
|
|
|
</mode>
|
|
|
|
|
<!-- 4-LUT mode definition end -->
|
|
|
|
|
</pb_type>
|
|
|
|
|
<interconnect>
|
2018-11-14 15:01:39 -06:00
|
|
|
<complete name="crossbar" input="clb.I fle[0:0].out" output="fle[0:0].in" circuit_model_name="mux_2level">
|
2018-10-03 18:10:29 -05:00
|
|
|
<delay_constant max="53.44e-12" in_port="clb.I" out_port="fle[0:0].in" />
|
|
|
|
|
<delay_constant max="53.44e-12" in_port="fle[0:0].out" out_port="fle[0:0].in" />
|
|
|
|
|
</complete>
|
|
|
|
|
<complete name="clks" input="clb.clk" output="fle[0:0].clk">
|
|
|
|
|
</complete>
|
|
|
|
|
|
|
|
|
|
<direct name="clbouts1" input="fle[0:0].out[0:0]" output="clb.O[0:0]"/>
|
|
|
|
|
<!--direct name="clbouts2" input="fle[9:0].out[1:1]" output="clb.O[19:10]"/-->
|
|
|
|
|
</interconnect>
|
|
|
|
|
|
|
|
|
|
<!-- Every input pin is driven by 15% of the tracks in a channel, every output pin is driven by 10% of the tracks in a channel -->
|
|
|
|
|
<fc default_in_type="frac" default_in_val="0.15" default_out_type="frac" default_out_val="0.10"/>
|
|
|
|
|
|
|
|
|
|
<pinlocations pattern="spread"/>
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
<!-- Place this general purpose logic block in any unspecified column -->
|
|
|
|
|
<gridlocations>
|
|
|
|
|
<loc type="fill" priority="1"/>
|
|
|
|
|
</gridlocations>
|
|
|
|
|
</pb_type>
|
|
|
|
|
<!-- Define general purpose logic block (CLB) ends -->
|
|
|
|
|
|
|
|
|
|
<!-- Define fracturable multiplier begin -->
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
</complexblocklist>
|
|
|
|
|
<power>
|
|
|
|
|
<local_interconnect C_wire="0"/>
|
|
|
|
|
<mux_transistor_size mux_transistor_size="5"/>
|
|
|
|
|
<FF_size FF_size="4"/>
|
|
|
|
|
<LUT_transistor_size LUT_transistor_size="5"/>
|
|
|
|
|
</power>
|
|
|
|
|
<clocks>
|
|
|
|
|
<clock buffer_size="auto" C_wire="0"/>
|
|
|
|
|
</clocks>
|
2018-11-14 15:01:39 -06:00
|
|
|
</architecture>
|
