2020-06-12 11:41:34 -05:00
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/***************************************************************************************
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* Output fabric key of Module Graph to file formats
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***************************************************************************************/
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/* Headers from vtrutil library */
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#include "vtr_log.h"
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#include "vtr_assert.h"
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#include "vtr_time.h"
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/* Headers from openfpgautil library */
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#include "openfpga_digest.h"
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/* Headers from archopenfpga library */
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#include "write_xml_fabric_key.h"
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#include "openfpga_naming.h"
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#include "fabric_key_writer.h"
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/* begin namespace openfpga */
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namespace openfpga {
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/***************************************************************************************
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* Write the fabric key of top module to an XML file
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* We will use the writer API in libfabrickey
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*
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* Return 0 if successful
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* Return 1 if there are more serious bugs in the architecture
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* Return 2 if fail when creating files
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***************************************************************************************/
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int write_fabric_key_to_xml_file(const ModuleManager& module_manager,
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const std::string& fname,
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2020-07-06 17:42:33 -05:00
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const e_config_protocol_type& config_protocol_type,
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2020-06-12 11:41:34 -05:00
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const bool& verbose) {
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std::string timer_message = std::string("Write fabric key to XML file '") + fname + std::string("'");
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std::string dir_path = format_dir_path(find_path_dir_name(fname));
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/* Create directories */
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create_directory(dir_path);
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/* Start time count */
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vtr::ScopedStartFinishTimer timer(timer_message);
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/* Use default name if user does not provide one */
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VTR_ASSERT(true != fname.empty());
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/* Find top-level module */
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std::string top_module_name = generate_fpga_top_module_name();
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ModuleId top_module = module_manager.find_module(top_module_name);
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if (true != module_manager.valid_module_id(top_module)) {
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VTR_LOGV_ERROR(verbose,
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"Unable to find the top-level module '%s'!\n",
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top_module_name.c_str());
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return 1;
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}
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/* Build a fabric key database by visiting all the configurable children */
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FabricKey fabric_key;
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2020-06-12 11:50:23 -05:00
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size_t num_keys = module_manager.configurable_children(top_module).size();
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2020-07-06 17:42:33 -05:00
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/* Exclude configuration-related modules in the keys */
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if (CONFIG_MEM_MEMORY_BANK == config_protocol_type) {
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num_keys -= 2;
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} else if (CONFIG_MEM_FRAME_BASED == config_protocol_type) {
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num_keys -= 1;
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}
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2020-06-12 11:41:34 -05:00
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fabric_key.reserve_keys(num_keys);
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for (size_t ichild = 0; ichild < num_keys; ++ichild) {
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2020-06-12 11:50:23 -05:00
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ModuleId child_module = module_manager.configurable_children(top_module)[ichild];
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size_t child_instance = module_manager.configurable_child_instances(top_module)[ichild];
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2020-06-12 11:41:34 -05:00
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FabricKeyId key = fabric_key.create_key();
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fabric_key.set_key_name(key, module_manager.module_name(child_module));
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fabric_key.set_key_value(key, child_instance);
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2020-06-27 15:59:53 -05:00
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if (false == module_manager.instance_name(top_module, child_module, child_instance).empty()) {
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fabric_key.set_key_alias(key, module_manager.instance_name(top_module, child_module, child_instance));
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}
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2020-06-12 11:41:34 -05:00
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}
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VTR_LOGV(verbose,
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"Created %lu keys for the top module %s.\n",
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num_keys, top_module_name.c_str());
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/* Call the XML writer for fabric key */
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int err_code = write_xml_fabric_key(fname.c_str(), fabric_key);
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return err_code;
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}
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} /* end namespace openfpga */
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