356 lines
12 KiB
C++
356 lines
12 KiB
C++
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/*
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* yosys -- Yosys Open SYnthesis Suite
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*
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* Copyright (C) 2012 Clifford Wolf <clifford@clifford.at>
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*
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* Permission to use, copy, modify, and/or distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*
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*/
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#include "kernel/log.h"
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#include "kernel/register.h"
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#include "kernel/sigtools.h"
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#include "kernel/consteval.h"
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#include "kernel/celltypes.h"
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#include "fsmdata.h"
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#include <string.h>
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USING_YOSYS_NAMESPACE
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PRIVATE_NAMESPACE_BEGIN
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static bool pattern_is_subset(const RTLIL::Const &super_pattern, const RTLIL::Const &sub_pattern)
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{
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log_assert(GetSize(super_pattern.bits) == GetSize(sub_pattern.bits));
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for (int i = 0; i < GetSize(super_pattern.bits); i++)
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if (sub_pattern.bits[i] == RTLIL::State::S0 || sub_pattern.bits[i] == RTLIL::State::S1) {
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if (super_pattern.bits[i] == RTLIL::State::S0 || super_pattern.bits[i] == RTLIL::State::S1) {
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if (super_pattern.bits[i] != sub_pattern.bits[i])
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return false;
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} else
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return false;
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}
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return true;
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}
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static void implement_pattern_cache(RTLIL::Module *module, std::map<RTLIL::Const, std::set<int>> &pattern_cache, std::set<int> &fullstate_cache, int num_states, RTLIL::Wire *state_onehot, RTLIL::SigSpec &ctrl_in, RTLIL::SigSpec output)
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{
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RTLIL::SigSpec cases_vector;
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for (int in_state : fullstate_cache)
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cases_vector.append(RTLIL::SigSpec(state_onehot, in_state));
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for (auto &it : pattern_cache)
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{
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RTLIL::Const pattern = it.first;
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RTLIL::SigSpec eq_sig_a, eq_sig_b, or_sig;
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for (size_t j = 0; j < pattern.bits.size(); j++)
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if (pattern.bits[j] == RTLIL::State::S0 || pattern.bits[j] == RTLIL::State::S1) {
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eq_sig_a.append(ctrl_in.extract(j, 1));
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eq_sig_b.append(RTLIL::SigSpec(pattern.bits[j]));
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}
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for (int in_state : it.second)
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if (fullstate_cache.count(in_state) == 0)
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or_sig.append(RTLIL::SigSpec(state_onehot, in_state));
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if (or_sig.size() == 0)
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continue;
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RTLIL::SigSpec and_sig;
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if (eq_sig_a.size() > 0)
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{
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RTLIL::Wire *eq_wire = module->addWire(NEW_ID);
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and_sig.append(RTLIL::SigSpec(eq_wire));
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RTLIL::Cell *eq_cell = module->addCell(NEW_ID, "$eq");
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eq_cell->setPort("\\A", eq_sig_a);
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eq_cell->setPort("\\B", eq_sig_b);
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eq_cell->setPort("\\Y", RTLIL::SigSpec(eq_wire));
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eq_cell->parameters["\\A_SIGNED"] = RTLIL::Const(false);
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eq_cell->parameters["\\B_SIGNED"] = RTLIL::Const(false);
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eq_cell->parameters["\\A_WIDTH"] = RTLIL::Const(eq_sig_a.size());
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eq_cell->parameters["\\B_WIDTH"] = RTLIL::Const(eq_sig_b.size());
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eq_cell->parameters["\\Y_WIDTH"] = RTLIL::Const(1);
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}
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std::set<int> complete_in_state_cache = it.second;
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for (auto &it2 : pattern_cache)
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if (pattern_is_subset(pattern, it2.first))
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complete_in_state_cache.insert(it2.second.begin(), it2.second.end());
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if (GetSize(complete_in_state_cache) < num_states)
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{
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if (or_sig.size() == 1)
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{
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and_sig.append(or_sig);
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}
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else
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{
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RTLIL::Wire *or_wire = module->addWire(NEW_ID);
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and_sig.append(RTLIL::SigSpec(or_wire));
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RTLIL::Cell *or_cell = module->addCell(NEW_ID, "$reduce_or");
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or_cell->setPort("\\A", or_sig);
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or_cell->setPort("\\Y", RTLIL::SigSpec(or_wire));
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or_cell->parameters["\\A_SIGNED"] = RTLIL::Const(false);
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or_cell->parameters["\\A_WIDTH"] = RTLIL::Const(or_sig.size());
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or_cell->parameters["\\Y_WIDTH"] = RTLIL::Const(1);
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}
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}
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switch (and_sig.size())
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{
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case 2:
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{
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RTLIL::Wire *and_wire = module->addWire(NEW_ID);
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cases_vector.append(RTLIL::SigSpec(and_wire));
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RTLIL::Cell *and_cell = module->addCell(NEW_ID, "$and");
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and_cell->setPort("\\A", and_sig.extract(0, 1));
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and_cell->setPort("\\B", and_sig.extract(1, 1));
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and_cell->setPort("\\Y", RTLIL::SigSpec(and_wire));
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and_cell->parameters["\\A_SIGNED"] = RTLIL::Const(false);
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and_cell->parameters["\\B_SIGNED"] = RTLIL::Const(false);
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and_cell->parameters["\\A_WIDTH"] = RTLIL::Const(1);
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and_cell->parameters["\\B_WIDTH"] = RTLIL::Const(1);
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and_cell->parameters["\\Y_WIDTH"] = RTLIL::Const(1);
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break;
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}
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case 1:
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cases_vector.append(and_sig);
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break;
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case 0:
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cases_vector.append(RTLIL::SigSpec(1, 1));
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break;
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default:
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log_abort();
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}
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}
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if (cases_vector.size() > 1) {
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RTLIL::Cell *or_cell = module->addCell(NEW_ID, "$reduce_or");
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or_cell->setPort("\\A", cases_vector);
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or_cell->setPort("\\Y", output);
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or_cell->parameters["\\A_SIGNED"] = RTLIL::Const(false);
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or_cell->parameters["\\A_WIDTH"] = RTLIL::Const(cases_vector.size());
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or_cell->parameters["\\Y_WIDTH"] = RTLIL::Const(1);
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} else if (cases_vector.size() == 1) {
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module->connect(RTLIL::SigSig(output, cases_vector));
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} else {
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module->connect(RTLIL::SigSig(output, RTLIL::SigSpec(0, 1)));
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}
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}
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static void map_fsm(RTLIL::Cell *fsm_cell, RTLIL::Module *module)
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{
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log("Mapping FSM `%s' from module `%s'.\n", fsm_cell->name.c_str(), module->name.c_str());
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FsmData fsm_data;
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fsm_data.copy_from_cell(fsm_cell);
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RTLIL::SigSpec ctrl_in = fsm_cell->getPort("\\CTRL_IN");
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RTLIL::SigSpec ctrl_out = fsm_cell->getPort("\\CTRL_OUT");
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// create state register
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RTLIL::Wire *state_wire = module->addWire(module->uniquify(fsm_cell->parameters["\\NAME"].decode_string()), fsm_data.state_bits);
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RTLIL::Wire *next_state_wire = module->addWire(NEW_ID, fsm_data.state_bits);
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RTLIL::Cell *state_dff = module->addCell(NEW_ID, "");
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if (fsm_cell->getPort("\\ARST").is_fully_const()) {
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state_dff->type = "$dff";
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} else {
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state_dff->type = "$adff";
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state_dff->parameters["\\ARST_POLARITY"] = fsm_cell->parameters["\\ARST_POLARITY"];
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state_dff->parameters["\\ARST_VALUE"] = fsm_data.state_table[fsm_data.reset_state];
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for (auto &bit : state_dff->parameters["\\ARST_VALUE"].bits)
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if (bit != RTLIL::State::S1)
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bit = RTLIL::State::S0;
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state_dff->setPort("\\ARST", fsm_cell->getPort("\\ARST"));
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}
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state_dff->parameters["\\WIDTH"] = RTLIL::Const(fsm_data.state_bits);
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state_dff->parameters["\\CLK_POLARITY"] = fsm_cell->parameters["\\CLK_POLARITY"];
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state_dff->setPort("\\CLK", fsm_cell->getPort("\\CLK"));
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state_dff->setPort("\\D", RTLIL::SigSpec(next_state_wire));
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state_dff->setPort("\\Q", RTLIL::SigSpec(state_wire));
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// decode state register
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bool encoding_is_onehot = true;
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RTLIL::Wire *state_onehot = module->addWire(NEW_ID, fsm_data.state_table.size());
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for (size_t i = 0; i < fsm_data.state_table.size(); i++)
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{
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RTLIL::Const state = fsm_data.state_table[i];
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RTLIL::SigSpec sig_a, sig_b;
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for (size_t j = 0; j < state.bits.size(); j++)
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if (state.bits[j] == RTLIL::State::S0 || state.bits[j] == RTLIL::State::S1) {
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sig_a.append(RTLIL::SigSpec(state_wire, j));
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sig_b.append(RTLIL::SigSpec(state.bits[j]));
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}
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if (sig_b == RTLIL::SigSpec(RTLIL::State::S1))
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{
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module->connect(RTLIL::SigSig(RTLIL::SigSpec(state_onehot, i), sig_a));
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}
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else
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{
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encoding_is_onehot = false;
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RTLIL::Cell *eq_cell = module->addCell(NEW_ID, "$eq");
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eq_cell->setPort("\\A", sig_a);
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eq_cell->setPort("\\B", sig_b);
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eq_cell->setPort("\\Y", RTLIL::SigSpec(state_onehot, i));
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eq_cell->parameters["\\A_SIGNED"] = RTLIL::Const(false);
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eq_cell->parameters["\\B_SIGNED"] = RTLIL::Const(false);
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eq_cell->parameters["\\A_WIDTH"] = RTLIL::Const(sig_a.size());
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eq_cell->parameters["\\B_WIDTH"] = RTLIL::Const(sig_b.size());
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eq_cell->parameters["\\Y_WIDTH"] = RTLIL::Const(1);
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}
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}
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if (encoding_is_onehot)
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state_wire->set_bool_attribute("\\onehot");
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// generate next_state signal
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if (GetSize(fsm_data.state_table) == 1)
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{
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module->connect(next_state_wire, fsm_data.state_table.front());
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}
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else
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{
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RTLIL::Wire *next_state_onehot = module->addWire(NEW_ID, fsm_data.state_table.size());
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for (size_t i = 0; i < fsm_data.state_table.size(); i++)
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{
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std::map<RTLIL::Const, std::set<int>> pattern_cache;
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std::set<int> fullstate_cache;
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for (size_t j = 0; j < fsm_data.state_table.size(); j++)
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fullstate_cache.insert(j);
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for (auto &tr : fsm_data.transition_table) {
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if (tr.state_out == int(i))
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pattern_cache[tr.ctrl_in].insert(tr.state_in);
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else
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fullstate_cache.erase(tr.state_in);
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}
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implement_pattern_cache(module, pattern_cache, fullstate_cache, fsm_data.state_table.size(), state_onehot, ctrl_in, RTLIL::SigSpec(next_state_onehot, i));
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}
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if (encoding_is_onehot)
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{
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RTLIL::SigSpec next_state_sig(RTLIL::State::Sm, next_state_wire->width);
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for (size_t i = 0; i < fsm_data.state_table.size(); i++) {
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RTLIL::Const state = fsm_data.state_table[i];
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int bit_idx = -1;
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for (size_t j = 0; j < state.bits.size(); j++)
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if (state.bits[j] == RTLIL::State::S1)
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bit_idx = j;
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if (bit_idx >= 0)
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next_state_sig.replace(bit_idx, RTLIL::SigSpec(next_state_onehot, i));
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}
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log_assert(!next_state_sig.has_marked_bits());
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module->connect(RTLIL::SigSig(next_state_wire, next_state_sig));
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}
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else
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{
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RTLIL::SigSpec sig_a(RTLIL::State::Sx, next_state_wire->width);
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RTLIL::SigSpec sig_b, sig_s;
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int reset_state = fsm_data.reset_state;
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if (reset_state < 0)
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reset_state = 0;
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for (size_t i = 0; i < fsm_data.state_table.size(); i++) {
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RTLIL::Const state = fsm_data.state_table[i];
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if (int(i) == fsm_data.reset_state) {
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sig_a = RTLIL::SigSpec(state);
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} else {
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sig_b.append(RTLIL::SigSpec(state));
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sig_s.append(RTLIL::SigSpec(next_state_onehot, i));
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}
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}
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RTLIL::Cell *mux_cell = module->addCell(NEW_ID, "$pmux");
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mux_cell->setPort("\\A", sig_a);
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mux_cell->setPort("\\B", sig_b);
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mux_cell->setPort("\\S", sig_s);
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mux_cell->setPort("\\Y", RTLIL::SigSpec(next_state_wire));
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mux_cell->parameters["\\WIDTH"] = RTLIL::Const(sig_a.size());
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mux_cell->parameters["\\S_WIDTH"] = RTLIL::Const(sig_s.size());
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}
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}
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// Generate ctrl_out signal
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for (int i = 0; i < fsm_data.num_outputs; i++)
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{
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std::map<RTLIL::Const, std::set<int>> pattern_cache;
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std::set<int> fullstate_cache;
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for (size_t j = 0; j < fsm_data.state_table.size(); j++)
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fullstate_cache.insert(j);
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for (auto &tr : fsm_data.transition_table) {
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if (tr.ctrl_out.bits[i] == RTLIL::State::S1)
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pattern_cache[tr.ctrl_in].insert(tr.state_in);
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else
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fullstate_cache.erase(tr.state_in);
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}
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implement_pattern_cache(module, pattern_cache, fullstate_cache, fsm_data.state_table.size(), state_onehot, ctrl_in, ctrl_out.extract(i, 1));
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||
|
|
}
|
||
|
|
|
||
|
|
// Remove FSM cell
|
||
|
|
|
||
|
|
module->remove(fsm_cell);
|
||
|
|
}
|
||
|
|
|
||
|
|
struct FsmMapPass : public Pass {
|
||
|
|
FsmMapPass() : Pass("fsm_map", "mapping FSMs to basic logic") { }
|
||
|
|
virtual void help()
|
||
|
|
{
|
||
|
|
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
|
||
|
|
log("\n");
|
||
|
|
log(" fsm_map [selection]\n");
|
||
|
|
log("\n");
|
||
|
|
log("This pass translates FSM cells to flip-flops and logic.\n");
|
||
|
|
log("\n");
|
||
|
|
}
|
||
|
|
virtual void execute(std::vector<std::string> args, RTLIL::Design *design)
|
||
|
|
{
|
||
|
|
log_header(design, "Executing FSM_MAP pass (mapping FSMs to basic logic).\n");
|
||
|
|
extra_args(args, 1, design);
|
||
|
|
|
||
|
|
for (auto &mod_it : design->modules_) {
|
||
|
|
if (!design->selected(mod_it.second))
|
||
|
|
continue;
|
||
|
|
std::vector<RTLIL::Cell*> fsm_cells;
|
||
|
|
for (auto &cell_it : mod_it.second->cells_)
|
||
|
|
if (cell_it.second->type == "$fsm" && design->selected(mod_it.second, cell_it.second))
|
||
|
|
fsm_cells.push_back(cell_it.second);
|
||
|
|
for (auto cell : fsm_cells)
|
||
|
|
map_fsm(cell, mod_it.second);
|
||
|
|
}
|
||
|
|
}
|
||
|
|
} FsmMapPass;
|
||
|
|
|
||
|
|
PRIVATE_NAMESPACE_END
|