OpenFPGA/docs/source/arch_lang/direct_interconnect.rst

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.. _direct_interconnect:
Inter-Tile Direct Interconnection extensions
--------------------------------------------
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This section introduces extensions on the architecture description file about existing interconnection description.
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Directlist
~~~~~~~~~~
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The original direct connections in the directlist section are documented here_. Its description is given below:
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.. _here: http://docs.verilogtorouting.org/en/latest/arch/reference/?highlight=directlist#direct-inter-block-connections
.. code-block:: xml
<directlist>
<direct name="string" from_pin="string" to_pin="string" x_offset="int" y_offset="int" z_offset="int" switch_name="string"/>
</directlist>
.. note:: These options are required
Our extension include three more options:
.. code-block:: xml
<directlist>
<direct name="string" from_pin="string" to_pin="string" x_offset="int" y_offset="int" z_offset="int" switch_name="string" interconnection_type="string" x_dir="string" y_dir="string"/>
</directlist>
.. note:: these options are optional. However, if `interconnection_type` is set `x_dir` and `y_dir` are required.
.. option:: interconnection_type="<string>"
the type of interconnection should be a string.
Available types are ``NONE`` | ``column`` | ``row``, specifies if it applies on a column or a row ot if it doesn't apply.
.. option:: x_dir="<string>"
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Available directionalities are ``positive`` | ``negative``, specifies if the next cell to connect has a bigger or lower ``x`` value.
Considering a coordinate system where (0,0) is the origin at the bottom left and ``x`` and ``y`` are positives:
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- x_dir="positive":
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- interconnection_type="column": a column will be connected to a column on the ``right``, if it exists.
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- interconnection_type="row": the most on the ``right`` cell from a row connection will connect the most on the ``left`` cell of next row, if it exists.
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- x_dir="negative":
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- interconnection_type="column": a column will be connected to a column on the ``left``, if it exists.
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- interconnection_type="row": the most on the ``left`` cell from a row connection will connect the most on the ``right`` cell of next row, if it exists.
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.. option:: y_dir="<string>"
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Available directionalities are ``positive`` | ``negative``, specifies if the next cell to connect has a bigger or lower x value.
Considering a coordinate system where (0,0) is the origin at the bottom left and `x` and `y` are positives:
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- y_dir="positive":
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- interconnection_type="column": the ``bottom`` cell of a column will be connected to the next column ``top`` cell, if it exists.
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- interconnection_type="row": a row will be connected on an ``above`` row, if it exists.
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- y_dir="negative":
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- interconnection_type="column": the ``top`` cell of a column will be connected to the next column ``bottom`` cell, if it exists.
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- interconnection_type="row": a row will be connected on a row ``below``, if it exists.
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Example
~~~~~~~
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For this example, we will study a scan-chain implementation. The description could be:
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.. code-block:: xml
<directlist>
<direct name="scff_chain" from_pin="clb.sc_out" to_pin="clb.sc_in" x_offset="0" y_offset="-1" z_offset="0" interconnection_type="column" x_dir="positive" y_dir="positive"/>
</directlist>
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:numref:`fig_p2p_exple` is the graphical representation of the above scan-chain description on a 4x4 FPGA.
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.. _fig_p2p_exple:
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.. figure:: ./figures/point2point_example.png
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An example of scan-chain implementation
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In this figure, the red arrows represent the initial direct connection. The green arrows represent the point to point connection to connect all the columns of CLB.
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Truth table
~~~~~~~~~~~
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A point to point connection can be applied in different ways than showed in the example section. To help the designer implement his point to point connection, a truth table with our new parameters id provided below.
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:numref:`fig_p2p_trtable` provides all possible variable combination and the connection it will generate.
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.. _fig_p2p_trtable:
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.. figure:: ./figures/point2point_truthtable.png
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Point to point truth table