2022-05-09 03:08:31 -05:00
|
|
|
name: Cell Library Tests
|
|
|
|
|
|
|
|
# Run CI on push, PR, and weekly.
|
|
|
|
|
|
|
|
on:
|
|
|
|
push:
|
|
|
|
pull_request:
|
|
|
|
schedule:
|
|
|
|
- cron: "0 0 * * 0 " # weekly
|
|
|
|
|
|
|
|
# Multiple job to tests
|
|
|
|
jobs:
|
|
|
|
# Test the RTL compilation compatibility
|
|
|
|
verilog:
|
|
|
|
name: RTL compilation and tests
|
2022-11-03 23:19:50 -05:00
|
|
|
runs-on: ubuntu-20.04
|
2022-05-09 03:08:31 -05:00
|
|
|
steps:
|
|
|
|
- name: Cancel previous
|
|
|
|
uses: styfle/cancel-workflow-action@0.9.1
|
|
|
|
with:
|
|
|
|
access_token: ${{ github.token }}
|
|
|
|
|
|
|
|
- name: Checkout OpenFPGA repo
|
|
|
|
uses: actions/checkout@v2
|
|
|
|
with:
|
|
|
|
submodules: true
|
|
|
|
|
2022-05-09 04:03:33 -05:00
|
|
|
- name: Install Dependencies
|
|
|
|
run: |
|
2022-11-04 16:18:30 -05:00
|
|
|
sudo bash .github/workflows/install_dependencies_run.sh
|
2022-05-09 04:03:33 -05:00
|
|
|
|
2022-05-09 03:08:31 -05:00
|
|
|
- name: Dump tool versions
|
|
|
|
run: |
|
|
|
|
iverilog -V
|
|
|
|
vvp -V
|
|
|
|
|
|
|
|
- name: Verilog compilation
|
|
|
|
run: |
|
|
|
|
cd openfpga_flow/openfpga_cell_library
|
|
|
|
make compile_verilog
|