OpenFPGA/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_submodules.h

10 lines
406 B
C
Raw Normal View History

#ifndef VERILOG_SUBMODULES_H
#define VERILOG_SUBMODULES_H
2019-04-26 13:23:47 -05:00
void dump_verilog_submodules(t_sram_orgz_info* cur_sram_orgz_info,
char* verilog_dir,
char* submodule_dir,
t_arch Arch,
t_det_routing_arch* routing_arch,
t_syn_verilog_opts fpga_verilog_opts);
#endif