OpenFPGA/fpga_flow/benchmarks/FPGA_SPICE_bench/usb_phy.blif

# Benchmark "usb_phy" written by ABC on Mon Aug 29 15:33:14 2005
.model usb_phy
.inputs clk rst phy_tx_mode rxd rxdp rxdn TxValid_i DataOut_i[0] \
 DataOut_i[1] DataOut_i[2] DataOut_i[3] DataOut_i[4] DataOut_i[5] \
 DataOut_i[6] DataOut_i[7]
.outputs usb_rst txdp txdn txoe TxReady_o RxValid_o RxActive_o RxError_o \
 DataIn_o[0] DataIn_o[1] DataIn_o[2] DataIn_o[3] DataIn_o[4] DataIn_o[5] \
 DataIn_o[6] DataIn_o[7] LineState_o[0] LineState_o[1]

.latch i_rx_phy_shift_en_reg_in i_rx_phy_shift_en_reg  2
.latch \i_rx_phy_fs_state_reg[0]_in \i_rx_phy_fs_state_reg[0]  2
.latch i_rx_phy_rx_active_reg_in i_rx_phy_rx_active_reg  2
.latch i_rx_phy_sync_err_reg_in i_rx_phy_sync_err_reg  2
.latch \i_rx_phy_fs_state_reg[1]_in \i_rx_phy_fs_state_reg[1]  2
.latch \i_rx_phy_fs_state_reg[2]_in \i_rx_phy_fs_state_reg[2]  2
.latch i_rx_phy_byte_err_reg_in i_rx_phy_byte_err_reg  2
.latch \i_tx_phy_hold_reg_reg[7]_in \i_tx_phy_hold_reg_reg[7]  2
.latch i_rx_phy_bit_stuff_err_reg_in i_rx_phy_bit_stuff_err_reg  2
.latch \i_tx_phy_hold_reg_reg[0]_in \i_tx_phy_hold_reg_reg[0]  2
.latch \i_tx_phy_hold_reg_reg[1]_in \i_tx_phy_hold_reg_reg[1]  2
.latch \i_tx_phy_hold_reg_reg[2]_in \i_tx_phy_hold_reg_reg[2]  2
.latch \i_tx_phy_hold_reg_reg[3]_in \i_tx_phy_hold_reg_reg[3]  2
.latch \i_tx_phy_hold_reg_reg[4]_in \i_tx_phy_hold_reg_reg[4]  2
.latch \i_tx_phy_hold_reg_reg[5]_in \i_tx_phy_hold_reg_reg[5]  2
.latch \i_tx_phy_hold_reg_reg[6]_in \i_tx_phy_hold_reg_reg[6]  2
.latch i_rx_phy_se0_s_reg_in i_rx_phy_se0_s_reg  2
.latch \i_tx_phy_state_reg[0]_in \i_tx_phy_state_reg[0]  2
.latch \i_rx_phy_dpll_state_reg[0]_in \i_rx_phy_dpll_state_reg[0]  2
.latch \i_tx_phy_state_reg[2]_in \i_tx_phy_state_reg[2]  2
.latch i_rx_phy_rx_valid1_reg_in i_rx_phy_rx_valid1_reg  2
.latch \i_rx_phy_dpll_state_reg[1]_in \i_rx_phy_dpll_state_reg[1]  2
.latch i_rx_phy_rx_valid_r_reg_in i_rx_phy_rx_valid_r_reg  2
.latch i_rx_phy_se0_r_reg_in i_rx_phy_se0_r_reg  2
.latch \rst_cnt_reg[3]_in \rst_cnt_reg[3]  2
.latch \rst_cnt_reg[4]_in \rst_cnt_reg[4]  2
.latch \rst_cnt_reg[2]_in \rst_cnt_reg[2]  2
.latch \i_tx_phy_state_reg[1]_in \i_tx_phy_state_reg[1]  2
.latch \i_rx_phy_one_cnt_reg[2]_in \i_rx_phy_one_cnt_reg[2]  2
.latch \i_rx_phy_one_cnt_reg[1]_in \i_rx_phy_one_cnt_reg[1]  2
.latch i_tx_phy_sd_raw_o_reg_in i_tx_phy_sd_raw_o_reg  2
.latch \i_rx_phy_bit_cnt_reg[2]_in \i_rx_phy_bit_cnt_reg[2]  2
.latch \i_tx_phy_bit_cnt_reg[2]_in \i_tx_phy_bit_cnt_reg[2]  2
.latch i_tx_phy_append_eop_reg_in i_tx_phy_append_eop_reg  2
.latch \i_rx_phy_one_cnt_reg[0]_in \i_rx_phy_one_cnt_reg[0]  2
.latch \i_rx_phy_bit_cnt_reg[0]_in \i_rx_phy_bit_cnt_reg[0]  2
.latch \i_rx_phy_bit_cnt_reg[1]_in \i_rx_phy_bit_cnt_reg[1]  2
.latch i_tx_phy_ld_data_reg_in i_tx_phy_ld_data_reg  2
.latch \i_tx_phy_one_cnt_reg[1]_in \i_tx_phy_one_cnt_reg[1]  2
.latch \i_tx_phy_one_cnt_reg[2]_in \i_tx_phy_one_cnt_reg[2]  2
.latch i_tx_phy_TxReady_o_reg_in i_tx_phy_TxReady_o_reg  2
.latch \i_tx_phy_bit_cnt_reg[0]_in \i_tx_phy_bit_cnt_reg[0]  2
.latch \i_tx_phy_bit_cnt_reg[1]_in \i_tx_phy_bit_cnt_reg[1]  2
.latch \i_tx_phy_one_cnt_reg[0]_in \i_tx_phy_one_cnt_reg[0]  2
.latch i_rx_phy_rx_valid_reg_in i_rx_phy_rx_valid_reg  2
.latch \i_rx_phy_hold_reg_reg[6]_in \i_rx_phy_hold_reg_reg[6]  2
.latch \i_rx_phy_hold_reg_reg[4]_in \i_rx_phy_hold_reg_reg[4]  2
.latch \i_rx_phy_hold_reg_reg[0]_in \i_rx_phy_hold_reg_reg[0]  2
.latch \i_rx_phy_hold_reg_reg[1]_in \i_rx_phy_hold_reg_reg[1]  2
.latch \i_rx_phy_hold_reg_reg[2]_in \i_rx_phy_hold_reg_reg[2]  2
.latch \i_rx_phy_hold_reg_reg[3]_in \i_rx_phy_hold_reg_reg[3]  2
.latch \i_rx_phy_hold_reg_reg[5]_in \i_rx_phy_hold_reg_reg[5]  2
.latch \i_rx_phy_hold_reg_reg[7]_in \i_rx_phy_hold_reg_reg[7]  2
.latch i_tx_phy_tx_ip_reg_in i_tx_phy_tx_ip_reg  2
.latch \rst_cnt_reg[1]_in \rst_cnt_reg[1]  2
.latch i_tx_phy_txdp_reg_in i_tx_phy_txdp_reg  2
.latch i_rx_phy_sd_nrzi_reg_in i_rx_phy_sd_nrzi_reg  2
.latch i_tx_phy_sd_bs_o_reg_in i_tx_phy_sd_bs_o_reg  2
.latch \rst_cnt_reg[0]_in \rst_cnt_reg[0]  2
.latch i_tx_phy_txdn_reg_in i_tx_phy_txdn_reg  2
.latch i_tx_phy_append_eop_sync3_reg_in i_tx_phy_append_eop_sync3_reg  2
.latch i_tx_phy_txoe_reg_in i_tx_phy_txoe_reg  2
.latch i_rx_phy_rxdn_s_reg_in i_rx_phy_rxdn_s_reg  2
.latch i_rx_phy_rxdp_s_reg_in i_rx_phy_rxdp_s_reg  2
.latch i_tx_phy_sft_done_reg_in i_tx_phy_sft_done_reg  2
.latch i_tx_phy_tx_ip_sync_reg_in i_tx_phy_tx_ip_sync_reg  2
.latch i_tx_phy_txoe_r1_reg_in i_tx_phy_txoe_r1_reg  2
.latch i_tx_phy_append_eop_sync1_reg_in i_tx_phy_append_eop_sync1_reg  2
.latch i_tx_phy_append_eop_sync2_reg_in i_tx_phy_append_eop_sync2_reg  2
.latch i_tx_phy_txoe_r2_reg_in i_tx_phy_txoe_r2_reg  2
.latch usb_rst_reg_in usb_rst_reg  2
.latch i_tx_phy_sd_nrzi_o_reg_in i_tx_phy_sd_nrzi_o_reg  2
.latch i_tx_phy_append_eop_sync4_reg_in i_tx_phy_append_eop_sync4_reg  2
.latch i_rx_phy_fs_ce_reg_in i_rx_phy_fs_ce_reg  2
.latch i_rx_phy_rxd_s_reg_in i_rx_phy_rxd_s_reg  2
.latch i_rx_phy_sd_r_reg_in i_rx_phy_sd_r_reg  2
.latch i_rx_phy_fs_ce_r2_reg_in i_rx_phy_fs_ce_r2_reg  2
.latch i_tx_phy_data_done_reg_in i_tx_phy_data_done_reg  2
.latch i_rx_phy_rxdn_s_r_reg_in i_rx_phy_rxdn_s_r_reg  2
.latch i_rx_phy_rxdp_s_r_reg_in i_rx_phy_rxdp_s_r_reg  2
.latch i_rx_phy_fs_ce_r1_reg_in i_rx_phy_fs_ce_r1_reg  2
.latch i_rx_phy_rxd_r_reg_in i_rx_phy_rxd_r_reg  2
.latch i_rx_phy_rxdn_s1_reg_in i_rx_phy_rxdn_s1_reg  2
.latch i_rx_phy_rxd_s1_reg_in i_rx_phy_rxd_s1_reg  2
.latch i_rx_phy_rxdp_s1_reg_in i_rx_phy_rxdp_s1_reg  2
.latch \i_tx_phy_hold_reg_d_reg[1]_in \i_tx_phy_hold_reg_d_reg[1]  2
.latch \i_tx_phy_hold_reg_d_reg[5]_in \i_tx_phy_hold_reg_d_reg[5]  2
.latch i_rx_phy_rxd_s0_reg_in i_rx_phy_rxd_s0_reg  2
.latch \i_tx_phy_hold_reg_d_reg[3]_in \i_tx_phy_hold_reg_d_reg[3]  2
.latch i_rx_phy_rxdn_s0_reg_in i_rx_phy_rxdn_s0_reg  2
.latch \i_tx_phy_hold_reg_d_reg[6]_in \i_tx_phy_hold_reg_d_reg[6]  2
.latch i_tx_phy_sft_done_r_reg_in i_tx_phy_sft_done_r_reg  2
.latch \i_tx_phy_hold_reg_d_reg[0]_in \i_tx_phy_hold_reg_d_reg[0]  2
.latch i_rx_phy_rxdp_s0_reg_in i_rx_phy_rxdp_s0_reg  2
.latch \i_tx_phy_hold_reg_d_reg[2]_in \i_tx_phy_hold_reg_d_reg[2]  2
.latch i_rx_phy_rx_en_reg_in i_rx_phy_rx_en_reg  2
.latch \i_tx_phy_hold_reg_d_reg[7]_in \i_tx_phy_hold_reg_d_reg[7]  2
.latch \i_tx_phy_hold_reg_d_reg[4]_in \i_tx_phy_hold_reg_d_reg[4]  2

.names [131]
 0
.names [132]
 1
.names [142] [137] [145] RxError_o
111 0
.names i_rx_phy_shift_en_reg [134]
1 1
.names \i_rx_phy_fs_state_reg[0] [135]
1 1
.names i_rx_phy_rx_active_reg RxActive_o
1 1
.names i_rx_phy_sync_err_reg [137]
0 1
.names [547] \i_rx_phy_fs_state_reg[0]_in
0 1
.names \i_rx_phy_fs_state_reg[1] [139]
1 1
.names \i_rx_phy_fs_state_reg[2] [140]
1 1
.names [154] [551] [403] \i_rx_phy_fs_state_reg[1]_in
11- 0
--1 0
.names i_rx_phy_byte_err_reg [142]
0 1
.names [157] [198] [143]
11 0
.names \i_tx_phy_hold_reg_reg[7] \i_tx_phy_hold_reg_d_reg[7]_in
1 1
.names i_rx_phy_bit_stuff_err_reg [145]
0 1
.names \i_tx_phy_hold_reg_reg[0] \i_tx_phy_hold_reg_d_reg[0]_in
1 1
.names \i_tx_phy_hold_reg_reg[1] \i_tx_phy_hold_reg_d_reg[1]_in
1 1
.names \i_tx_phy_hold_reg_reg[2] \i_tx_phy_hold_reg_d_reg[2]_in
1 1
.names \i_tx_phy_hold_reg_reg[3] \i_tx_phy_hold_reg_d_reg[3]_in
1 1
.names \i_tx_phy_hold_reg_reg[4] \i_tx_phy_hold_reg_d_reg[4]_in
1 1
.names \i_tx_phy_hold_reg_reg[5] \i_tx_phy_hold_reg_d_reg[5]_in
1 1
.names \i_tx_phy_hold_reg_reg[6] \i_tx_phy_hold_reg_d_reg[6]_in
1 1
.names [661] [175] [191] \i_tx_phy_hold_reg_reg[7]_in
111 0
.names [170] [589] [154]
11 0
.names [168] i_rx_phy_bit_stuff_err_reg_in
0 1
.names [171] [195] i_rx_phy_byte_err_reg_in
00 1
.names [393] [415] [174] [157]
111 0
.names i_rx_phy_se0_s_reg [158]
1 1
.names [615] [606] [159]
11 0
.names [179] [661] \i_tx_phy_hold_reg_reg[0]_in
11 1
.names [180] [661] \i_tx_phy_hold_reg_reg[1]_in
11 1
.names [181] [661] \i_tx_phy_hold_reg_reg[2]_in
11 1
.names [182] [661] \i_tx_phy_hold_reg_reg[3]_in
11 1
.names [183] [661] \i_tx_phy_hold_reg_reg[4]_in
11 1
.names [184] [661] \i_tx_phy_hold_reg_reg[5]_in
11 1
.names [185] [661] \i_tx_phy_hold_reg_reg[6]_in
11 1
.names [629] [190] [167]
11 0
.names [374] [431] [236] \i_rx_phy_hold_reg_reg[7]_in [168]
1111 0
.names \i_tx_phy_state_reg[0] [169]
1 1
.names [582] [170]
0 1
.names [217] [212] [193] [171]
00- 1
--0 1
.names [519] [602] [194] i_rx_phy_se0_s_reg_in
00- 1
--0 1
.names \i_rx_phy_dpll_state_reg[0] [173]
1 1
.names [612] [197] [174]
00 1
.names [207] DataOut_i[7] [175]
11 0
.names [583] [176]
0 1
.names [583] [177]
0 1
.names [556] [619] [414] \i_tx_phy_state_reg[0]_in
11- 0
--1 0
.names DataOut_i[0] \i_tx_phy_hold_reg_d_reg[0]_in [222] [179]
01- 1
1-1 1
.names DataOut_i[1] \i_tx_phy_hold_reg_d_reg[1]_in [222] [180]
01- 1
1-1 1
.names DataOut_i[2] \i_tx_phy_hold_reg_d_reg[2]_in [222] [181]
01- 1
1-1 1
.names DataOut_i[3] \i_tx_phy_hold_reg_d_reg[3]_in [222] [182]
01- 1
1-1 1
.names DataOut_i[4] \i_tx_phy_hold_reg_d_reg[4]_in [222] [183]
01- 1
1-1 1
.names DataOut_i[5] \i_tx_phy_hold_reg_d_reg[5]_in [222] [184]
01- 1
1-1 1
.names DataOut_i[6] \i_tx_phy_hold_reg_d_reg[6]_in [222] [185]
01- 1
1-1 1
.names \i_tx_phy_state_reg[2] [186]
1 1
.names i_rx_phy_rx_valid1_reg [187]
1 1
.names \i_rx_phy_dpll_state_reg[1] [188]
1 1
.names i_rx_phy_rx_valid_r_reg [189]
1 1
.names [618] [666] [190]
11 0
.names \i_tx_phy_hold_reg_d_reg[7]_in [222] [191]
11 0
.names [225] [261] rst \i_rx_phy_dpll_state_reg[0]_in
111 0
.names i_rx_phy_se0_r_reg [193]
0 1
.names i_rx_phy_se0_r_reg_in [674] [194]
11 0
.names i_rx_phy_se0_r_reg_in RxActive_o [195]
11 0
.names [189] i_rx_phy_se0_r_reg_in [196]
11 0
.names [634] [197]
0 1
.names [221] [443] [636] [198]
111 0
.names \rst_cnt_reg[3] [199]
1 1
.names \rst_cnt_reg[4] [200]
1 1
.names \rst_cnt_reg[2] [201]
1 1
.names \i_tx_phy_state_reg[1] [202]
1 1
.names \i_rx_phy_one_cnt_reg[2] [203]
1 1
.names \i_rx_phy_one_cnt_reg[1] [204]
1 1
.names [612] [471] [205]
11 0
.names [261] [479] [414] \i_rx_phy_dpll_state_reg[1]_in
11- 0
--1 0
.names [222] [207]
0 1
.names [427] RxValid_o i_rx_phy_rx_valid_r_reg_in
00 0
.names [255] [348] [404] \i_tx_phy_state_reg[2]_in
11- 0
--1 0
.names [585] [238] i_rx_phy_rx_valid1_reg_in
11 0
.names i_tx_phy_sd_raw_o_reg [211]
1 1
.names \i_rx_phy_bit_cnt_reg[2] [212]
1 1
.names \i_tx_phy_bit_cnt_reg[2] [213]
1 1
.names i_tx_phy_append_eop_reg [214]
1 1
.names \i_rx_phy_one_cnt_reg[0] [215]
1 1
.names \i_rx_phy_bit_cnt_reg[0] [216]
1 1
.names \i_rx_phy_bit_cnt_reg[1] [217]
1 1
.names [265] [385] \rst_cnt_reg[2]_in
00 1
.names [430] [276] [651] \i_rx_phy_one_cnt_reg[1]_in
11- 0
--1 0
.names [236] i_rx_phy_se0_r_reg_in
0 1
.names [272] [552] [221]
00 1
.names i_tx_phy_ld_data_reg [222]
0 1
.names \i_tx_phy_one_cnt_reg[1] [223]
1 1
.names [243] \rst_cnt_reg[4]_in
0 1
.names [465] [299] [260] [225]
11- 0
--1 0
.names [652] rst \i_tx_phy_state_reg[1]_in
11 1
.names [264] [385] \rst_cnt_reg[3]_in
00 1
.names \i_tx_phy_one_cnt_reg[2] [228]
1 1
.names i_tx_phy_TxReady_o_reg TxReady_o
1 1
.names \i_tx_phy_bit_cnt_reg[0] [230]
1 1
.names \i_tx_phy_bit_cnt_reg[1] [231]
1 1
.names \i_tx_phy_one_cnt_reg[0] [232]
1 1
.names [275] [475] \i_tx_phy_bit_cnt_reg[2]_in
00 1
.names [291] [302] [651] \i_rx_phy_bit_cnt_reg[2]_in
11- 0
--1 0
.names [554] [537] [235]
00 1
.names [272] [553] [236]
11 0
.names [280] [310] [496] i_tx_phy_sd_raw_o_reg_in
11- 0
--1 0
.names [586] [212] rst [473] [238]
1111 0
.names [477] [658] [414] i_tx_phy_append_eop_reg_in
11- 0
--1 0
.names [292] [315] [651] \i_rx_phy_bit_cnt_reg[0]_in
11- 0
--1 0
.names [426] [300] [651] \i_rx_phy_one_cnt_reg[0]_in
11- 0
--1 0
.names [293] [312] [651] \i_rx_phy_bit_cnt_reg[1]_in
11- 0
--1 0
.names [273] [356] [243]
11 0
.names i_rx_phy_rx_valid_reg RxValid_o
1 1
.names \i_rx_phy_hold_reg_reg[6] \i_rx_phy_hold_reg_reg[5]_in
1 1
.names \i_rx_phy_hold_reg_reg[4] \i_rx_phy_hold_reg_reg[3]_in
1 1
.names \i_rx_phy_hold_reg_reg[0] DataIn_o[0]
1 1
.names \i_rx_phy_hold_reg_reg[1] \i_rx_phy_hold_reg_reg[0]_in
1 1
.names \i_rx_phy_hold_reg_reg[2] \i_rx_phy_hold_reg_reg[1]_in
1 1
.names \i_rx_phy_hold_reg_reg[3] \i_rx_phy_hold_reg_reg[2]_in
1 1
.names \i_rx_phy_hold_reg_reg[5] \i_rx_phy_hold_reg_reg[4]_in
1 1
.names \i_rx_phy_hold_reg_reg[7] \i_rx_phy_hold_reg_reg[6]_in
1 1
.names i_tx_phy_tx_ip_reg [253]
1 1
.names [428] [307] [475] \i_tx_phy_one_cnt_reg[1]_in
11- 0
--1 0
.names [318] [641] [321] [255]
11- 0
--1 0
.names [314] [336] [475] \i_tx_phy_bit_cnt_reg[0]_in
11- 0
--1 0
.names [305] [340] [475] \i_tx_phy_bit_cnt_reg[1]_in
11- 0
--1 0
.names \rst_cnt_reg[1] [258]
1 1
.names [334] [290] i_tx_phy_TxReady_o_reg_in
11 0
.names [299] [479] [260]
00 1
.names [299] [188] [530] [261]
111 0
.names [423] [306] [475] \i_tx_phy_one_cnt_reg[2]_in
11- 0
--1 0
.names [346] [541] [301] i_tx_phy_ld_data_reg_in
00- 1
--0 1
.names [425] [199] [279] [264]
11- 0
--1 0
.names [425] [201] [281] [265]
11- 0
--1 0
.names i_tx_phy_txdp_reg txdp
1 1
.names i_rx_phy_sd_nrzi_reg \i_rx_phy_hold_reg_reg[7]_in
1 1
.names i_tx_phy_sd_bs_o_reg [268]
1 1
.names \rst_cnt_reg[0] [269]
1 1
.names i_tx_phy_txdn_reg txdn
1 1
.names i_tx_phy_append_eop_sync3_reg [271]
1 1
.names [282] [272]
0 1
.names [328] [425] [371] [273]
00- 1
--0 1
.names [424] [338] [475] \i_tx_phy_one_cnt_reg[0]_in
11- 0
--1 0
.names [342] [213] [308] [275]
11- 0
--1 0
.names [446] [649] [276]
11 0
.names [586] [187] i_rx_phy_rx_valid_reg_in
11 1
.names i_tx_phy_txoe_reg i_rx_phy_rx_en_reg_in
1 1
.names [344] [367] [425] [279]
11- 0
--1 0
.names [382] [337] [280]
00 1
.names [332] [425] [281]
00 1
.names i_rx_phy_rxdn_s_reg [282]
1 1
.names i_rx_phy_rxdp_s_reg [283]
1 1
.names [373] [357] [385] \rst_cnt_reg[1]_in
11- 0
--1 0
.names [331] rst i_tx_phy_txdp_reg_in
11 0
.names [359] RxActive_o [414] i_rx_phy_sd_nrzi_reg_in
11- 0
--1 0
.names [429] [360] [403] i_tx_phy_txdn_reg_in
11- 0
--1 0
.names [326] [385] \rst_cnt_reg[0]_in
00 1
.names [351] [339] i_tx_phy_sd_bs_o_reg_in
11 0
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1111 0
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11 0
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11 0
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11 0
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1 1
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1 1
.names i_tx_phy_txoe_r1_reg [296]
1 1
.names i_tx_phy_append_eop_sync1_reg [297]
1 1
.names i_tx_phy_append_eop_sync2_reg [298]
1 1
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111 0
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111 0
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11 0
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1 1
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1 1
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11 0
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11 0
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11 0
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11 0
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11 0
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11 0
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11 0
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11 1
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1 1
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1 1
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1 1
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1 1
.end