107 lines
3.0 KiB
C++
107 lines
3.0 KiB
C++
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/*
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* yosys -- Yosys Open SYnthesis Suite
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*
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* Copyright (C) 2012 Clifford Wolf <clifford@clifford.at>
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*
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* Permission to use, copy, modify, and/or distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*
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*/
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#include "kernel/yosys.h"
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#include "kernel/sigtools.h"
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#include <stdlib.h>
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#include <stdio.h>
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USING_YOSYS_NAMESPACE
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PRIVATE_NAMESPACE_BEGIN
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static SigBit get_bit_or_zero(const SigSpec &sig)
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{
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if (GetSize(sig) == 0)
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return State::S0;
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return sig[0];
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}
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static void run_ice40_unlut(Module *module)
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{
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SigMap sigmap(module);
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for (auto cell : module->selected_cells())
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{
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if (cell->type == "\\SB_LUT4")
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{
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SigSpec inbits;
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inbits.append(get_bit_or_zero(cell->getPort("\\I0")));
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inbits.append(get_bit_or_zero(cell->getPort("\\I1")));
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inbits.append(get_bit_or_zero(cell->getPort("\\I2")));
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inbits.append(get_bit_or_zero(cell->getPort("\\I3")));
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sigmap.apply(inbits);
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log("Mapping SB_LUT4 cell %s.%s to $lut.\n", log_id(module), log_id(cell));
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cell->type ="$lut";
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cell->setParam("\\WIDTH", 4);
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cell->setParam("\\LUT", cell->getParam("\\LUT_INIT"));
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cell->unsetParam("\\LUT_INIT");
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cell->setPort("\\A", SigSpec({
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get_bit_or_zero(cell->getPort("\\I3")),
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get_bit_or_zero(cell->getPort("\\I2")),
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get_bit_or_zero(cell->getPort("\\I1")),
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get_bit_or_zero(cell->getPort("\\I0"))
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}));
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cell->setPort("\\Y", cell->getPort("\\O")[0]);
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cell->unsetPort("\\I0");
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cell->unsetPort("\\I1");
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cell->unsetPort("\\I2");
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cell->unsetPort("\\I3");
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cell->unsetPort("\\O");
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cell->check();
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}
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}
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}
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struct Ice40UnlutPass : public Pass {
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Ice40UnlutPass() : Pass("ice40_unlut", "iCE40: perform simple optimizations") { }
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void help() YS_OVERRIDE
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{
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// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
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log("\n");
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log(" ice40_unlut [options] [selection]\n");
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log("\n");
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log("This command transforms all SB_LUT4 cells to generic $lut cells.\n");
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log("\n");
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}
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void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
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{
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log_header(design, "Executing ICE40_UNLUT pass (convert SB_LUT4 to $lut).\n");
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log_push();
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size_t argidx;
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for (argidx = 1; argidx < args.size(); argidx++) {
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// if (args[argidx] == "-???") {
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// continue;
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// }
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break;
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}
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extra_args(args, argidx, design);
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for (auto module : design->selected_modules())
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run_ice40_unlut(module);
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}
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} Ice40UnlutPass;
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PRIVATE_NAMESPACE_END
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