OpenFPGA/openfpga_flow/benchmarks/iwls2005/pci/rtl/timescale.v

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//////////////////////////////////////////////////////////////////////
//// ////
//// File name "timescale.v" ////
//// ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: timescale.v,v $
// Revision 1.2 2002/02/01 15:25:13 mihad
// Repaired a few bugs, updated specification, added test bench files and design document
//
// Revision 1.1 2001/10/05 08:11:22 mihad
// Updated all files with inclusion of timescale file for simulation purposes.
//
//
// timescale directive is included in all core's modules for simulation purposes
`timescale 1ns/1ps