102 lines
4.2 KiB
Plaintext
102 lines
4.2 KiB
Plaintext
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# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
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# Configuration file for running experiments
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# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
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# timeout_each_job : FPGA Task script splits fpga flow into multiple jobs
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# Each job execute fpga_flow script on combination of architecture & benchmark
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# timeout_each_job is timeout for each job
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# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
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[GENERAL]
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power_tech_file = ${PATH:OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.xml
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power_analysis = true
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spice_output=false
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verilog_output=true
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timeout_each_job = 200*60
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fpga_flow=yosys_vpr
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[ARCHITECTURES]
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#arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/arch/template/k6_N10_sram_chain_HC_template.xml
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#arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/arch/template/k4_N4_sram_chain_FC_behavioral_verilog_template.xml
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arch1=${PATH:OPENFPGA_PATH}/openfpga_flow/arch/template/k6_N10_sram_chain_HC_tileable_template.xml
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[BENCHMARKS]
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bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/epfl/adder/adder.v
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bench1=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/epfl/arbiter/arbiter.v
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bench2=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/epfl/bar/bar.v
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bench3=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/epfl/cavlc/cavlc.v
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bench4=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/epfl/ctrl/ctrl.v
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bench5=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/epfl/dec/dec.v
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bench6=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/epfl/div/div.v
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# This benchmark is failing -> debug ongoing
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#bench7=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/epfl/hyp/hyp.v
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bench8=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/epfl/i2c/i2c.v
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bench9=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/epfl/int2float/int2float.v
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bench10=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/epfl/log2/log2.v
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bench11=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/epfl/max/max.v
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# This benchmark is commented because of its runtime
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#bench12=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/epfl/mem_ctrl/mem_ctrl.v
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bench13=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/epfl/multiplier/multiplier.v
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bench14=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/epfl/priority/priority.v
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bench15=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/epfl/router/router.v
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bench16=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/epfl/sin/sin.v
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bench17=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/epfl/sqrt/sqrt.v
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bench18=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/epfl/square/square.v
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bench19=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/epfl/voter/voter.v
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[SYNTHESIS_PARAM]
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bench0_top = adder
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bench1_top = arbiter
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bench2_top = bar
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bench3_top = cavlc
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bench4_top = ctrl
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bench5_top = dec
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bench6_top = div
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#bench7_top = hyp
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bench8_top = i2c
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bench9_top = int2float
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bench10_top = log2
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bench11_top = max
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bench12_top = mem_ctrl
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bench13_top = multiplier
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bench14_top = priority
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bench15_top = router
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bench16_top = sin
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bench17_top = sqrt
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bench18_top = square
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bench19_top = voter
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#[SCRIPT_PARAM_FIX_ROUTE_CHAN_WIDTH]
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#fix_route_chan_width=300
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#vpr_fpga_verilog_include_icarus_simulator=
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#vpr_fpga_verilog_formal_verification_top_netlist=
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#vpr_fpga_verilog_include_timing=
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#vpr_fpga_verilog_include_signal_init=
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#vpr_fpga_verilog_print_autocheck_top_testbench=
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#vpr_fpga_bitstream_generator=
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#vpr_fpga_verilog_print_user_defined_template=
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#vpr_fpga_verilog_print_report_timing_tcl=
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#vpr_fpga_verilog_print_sdc_pnr=
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#vpr_fpga_verilog_print_sdc_analysis=
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##vpr_fpga_x2p_compact_routing_hierarchy=
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#end_flow_with_test=
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[SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH]
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min_route_chan_width=1.3
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#vpr_fpga_verilog_include_icarus_simulator=
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vpr_fpga_verilog_formal_verification_top_netlist=
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vpr_fpga_verilog_include_timing=
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vpr_fpga_verilog_include_signal_init=
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vpr_fpga_verilog_print_autocheck_top_testbench=
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vpr_fpga_bitstream_generator=
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vpr_fpga_verilog_print_user_defined_template=
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#vpr_fpga_verilog_print_report_timing_tcl=
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#vpr_fpga_verilog_print_sdc_pnr=
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#vpr_fpga_verilog_print_sdc_analysis=
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vpr_fpga_verilog_explicit_mapping=
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vpr_fpga_x2p_compact_routing_hierarchy=
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# If you wish to run Modelsim verification in batch, turn on the ini file outputting
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vpr_fpga_verilog_print_simulation_ini=
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# If you wish to run Modelsim verification in batch, turn off running iVerilog at the end of the flow
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#end_flow_with_test=
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