OpenFPGA/docs/source/manual/fpga_verilog/index.rst

FPGA-Verilog
------------

.. _fpga_verilog:
   FPGA-Verilog
 
.. toctree::
   :maxdepth: 2
  
   fabric_netlist
 
   testbench
start reworking the openfpga tool documentation 2020-03-10 18:29:35 -05:00			`FPGA-Verilog`
			`------------`
minor format fix on documentation 2020-03-11 11:22:30 -05:00
Adding documentation 2018-09-13 16:38:41 -05:00			`.. _fpga_verilog:`
update documentation in simulation setting syntax 2020-03-09 18:40:33 -05:00			`FPGA-Verilog`
Adding documentation 2018-09-13 16:38:41 -05:00
			`.. toctree::`
			`:maxdepth: 2`

Update Verilog fabric netlist documentation 2020-05-24 17:29:57 -05:00			`fabric_netlist`
Adding documentation 2018-09-13 16:38:41 -05:00
update documentation about Verilog testbenches 2020-05-24 19:01:34 -05:00			`testbench`