OpenFPGA/openfpga_flow/benchmarks/micro_benchmark/or2/or2.v

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/////////////////////////////////////////
// Functionality: 2-input OR
// Author: Xifan Tang
////////////////////////////////////////
`timescale 1ns / 1ps
module or2(
a,
b,
c);
input wire a;
input wire b;
output wire c;
assign c = a | b;
endmodule