139 lines
4.7 KiB
Coq
139 lines
4.7 KiB
Coq
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/////////////////////////////////////////////////////////////////////
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//// ////
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//// WISHBONE rev.B2 compliant VGA/LCD Core; Clock Generator ////
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//// ////
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//// ////
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//// Author: Richard Herveille ////
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//// richard@asics.ws ////
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//// www.asics.ws ////
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//// ////
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//// Downloaded from: http://www.opencores.org/projects/vga_lcd ////
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//// ////
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/////////////////////////////////////////////////////////////////////
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//// ////
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//// Copyright (C) 2003 Richard Herveille ////
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//// richard@asics.ws ////
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//// ////
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//// This source file may be used and distributed without ////
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//// restriction provided that this copyright statement is not ////
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//// removed from the file and that any derivative work contains ////
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//// the original copyright notice and the associated disclaimer.////
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//// ////
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//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ////
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//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ////
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//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ////
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//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ////
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//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ////
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//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ////
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//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ////
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//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ////
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//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ////
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//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ////
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//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ////
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//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ////
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//// POSSIBILITY OF SUCH DAMAGE. ////
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//// ////
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/////////////////////////////////////////////////////////////////////
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/////////////////////////////////////////////////////////////////////
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// //
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// !! SPECIAL LOGIC, USE PRECAUTION DURING SYNTHESIS AND LAYOUT !! //
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// //
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// This is a clock generation circuit. Although all output clocks //
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// are generated synchronous to the input clock, special care must //
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// be taken during synthesis and physical layout. //
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// //
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/////////////////////////////////////////////////////////////////////
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// CVS Log
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//
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// $Id: vga_clkgen.v,v 1.1 2003/05/07 14:43:01 rherveille Exp $
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//
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// $Date: 2003/05/07 14:43:01 $
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// $Revision: 1.1 $
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// $Author: rherveille $
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// $Locker: $
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// $State: Exp $
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//
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// Change History:
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// $Log: vga_clkgen.v,v $
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// Revision 1.1 2003/05/07 14:43:01 rherveille
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// Initial release.
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//
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//
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//synopsys translate_off
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`include "timescale.v"
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//synopsys translate_on
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`include "vga_defines.v"
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module vga_clkgen (
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pclk_i, rst_i, pclk_o, dvi_pclk_p_o, dvi_pclk_m_o, pclk_ena_o
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);
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// inputs & outputs
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input pclk_i; // pixel clock in
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input rst_i; // reset input
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output pclk_o; // pixel clock out
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output dvi_pclk_p_o; // dvi cpclk+ output
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output dvi_pclk_m_o; // dvi cpclk- output
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output pclk_ena_o; // pixel clock enable output
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//
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// variable declarations
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//
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reg dvi_pclk_p_o;
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reg dvi_pclk_m_o;
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//////////////////////////////////
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//
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// module body
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//
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// These should be registers in or near IO buffers
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always @(posedge pclk_i)
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if (rst_i) begin
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dvi_pclk_p_o <= #1 1'b0;
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dvi_pclk_m_o <= #1 1'b0;
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end else begin
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dvi_pclk_p_o <= #1 ~dvi_pclk_p_o;
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dvi_pclk_m_o <= #1 dvi_pclk_p_o;
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end
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`ifdef VGA_12BIT_DVI
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// DVI circuit
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// pixel clock is half of the input pixel clock
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reg pclk_o, pclk_ena_o;
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always @(posedge pclk_i)
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if (rst_i)
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pclk_o <= #1 1'b0;
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else
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pclk_o <= #1 ~pclk_o;
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always @(posedge pclk_i)
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if (rst_i)
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pclk_ena_o <= #1 1'b1;
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else
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pclk_ena_o <= #1 ~pclk_ena_o;
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`else
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// No DVI circuit
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// Simply reroute the pixel clock input
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assign pclk_o = pclk_i;
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assign pclk_ena_o = 1'b1;
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`endif
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endmodule
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