239 lines
9.2 KiB
Coq
239 lines
9.2 KiB
Coq
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//////////////////////////////////////////////////////////////////////
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//// ////
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//// spi_shift.v ////
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//// ////
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//// This file is part of the SPI IP core project ////
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//// http://www.opencores.org/projects/spi/ ////
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//// ////
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//// Author(s): ////
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//// - Simon Srot (simons@opencores.org) ////
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//// ////
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//// All additional information is avaliable in the Readme.txt ////
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//// file. ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//// ////
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//// Copyright (C) 2002 Authors ////
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//// ////
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//// This source file may be used and distributed without ////
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//// restriction provided that this copyright statement is not ////
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//// removed from the file and that any derivative work contains ////
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//// the original copyright notice and the associated disclaimer. ////
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//// ////
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//// This source file is free software; you can redistribute it ////
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//// and/or modify it under the terms of the GNU Lesser General ////
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//// Public License as published by the Free Software Foundation; ////
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//// either version 2.1 of the License, or (at your option) any ////
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//// later version. ////
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//// ////
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//// This source is distributed in the hope that it will be ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
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//// PURPOSE. See the GNU Lesser General Public License for more ////
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//// details. ////
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//// ////
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//// You should have received a copy of the GNU Lesser General ////
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//// Public License along with this source; if not, download it ////
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//// from http://www.opencores.org/lgpl.shtml ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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`include "spi_defines.v"
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`include "timescale.v"
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module spi_shift (clk, rst, latch, byte_sel, len, lsb, go,
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pos_edge, neg_edge, rx_negedge, tx_negedge,
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tip, last,
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p_in, p_out, s_clk, s_in, s_out);
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parameter Tp = 1;
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input clk; // system clock
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input rst; // reset
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input [3:0] latch; // latch signal for storing the data in shift register
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input [3:0] byte_sel; // byte select signals for storing the data in shift register
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input [`SPI_CHAR_LEN_BITS-1:0] len; // data len in bits (minus one)
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input lsb; // lbs first on the line
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input go; // start stansfer
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input pos_edge; // recognize posedge of sclk
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input neg_edge; // recognize negedge of sclk
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input rx_negedge; // s_in is sampled on negative edge
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input tx_negedge; // s_out is driven on negative edge
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output tip; // transfer in progress
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output last; // last bit
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input [31:0] p_in; // parallel in
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output [`SPI_MAX_CHAR-1:0] p_out; // parallel out
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input s_clk; // serial clock
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input s_in; // serial in
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output s_out; // serial out
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reg s_out;
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reg tip;
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reg [`SPI_CHAR_LEN_BITS:0] cnt; // data bit count
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reg [`SPI_MAX_CHAR-1:0] data; // shift register
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wire [`SPI_CHAR_LEN_BITS:0] tx_bit_pos; // next bit position
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wire [`SPI_CHAR_LEN_BITS:0] rx_bit_pos; // next bit position
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wire rx_clk; // rx clock enable
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wire tx_clk; // tx clock enable
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assign p_out = data;
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assign tx_bit_pos = lsb ? {!(|len), len} - cnt : cnt - {{`SPI_CHAR_LEN_BITS{1'b0}},1'b1};
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assign rx_bit_pos = lsb ? {!(|len), len} - (rx_negedge ? cnt + {{`SPI_CHAR_LEN_BITS{1'b0}},1'b1} : cnt) :
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(rx_negedge ? cnt : cnt - {{`SPI_CHAR_LEN_BITS{1'b0}},1'b1});
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assign last = !(|cnt);
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assign rx_clk = (rx_negedge ? neg_edge : pos_edge) && (!last || s_clk);
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assign tx_clk = (tx_negedge ? neg_edge : pos_edge) && !last;
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// Character bit counter
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always @(posedge clk or posedge rst)
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begin
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if(rst)
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cnt <= #Tp {`SPI_CHAR_LEN_BITS+1{1'b0}};
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else
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begin
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if(tip)
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cnt <= #Tp pos_edge ? (cnt - {{`SPI_CHAR_LEN_BITS{1'b0}}, 1'b1}) : cnt;
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else
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cnt <= #Tp !(|len) ? {1'b1, {`SPI_CHAR_LEN_BITS{1'b0}}} : {1'b0, len};
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end
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end
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// Transfer in progress
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always @(posedge clk or posedge rst)
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begin
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if(rst)
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tip <= #Tp 1'b0;
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else if(go && ~tip)
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tip <= #Tp 1'b1;
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else if(tip && last && pos_edge)
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tip <= #Tp 1'b0;
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end
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// Sending bits to the line
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always @(posedge clk or posedge rst)
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begin
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if (rst)
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s_out <= #Tp 1'b0;
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else
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s_out <= #Tp (tx_clk || !tip) ? data[tx_bit_pos[`SPI_CHAR_LEN_BITS-1:0]] : s_out;
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end
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// Receiving bits from the line
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always @(posedge clk or posedge rst)
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begin
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if (rst)
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data <= #Tp {`SPI_MAX_CHAR{1'b0}};
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`ifdef SPI_MAX_CHAR_128
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else if (latch[0] && !tip)
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begin
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if (byte_sel[3])
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data[31:24] <= #Tp p_in[31:24];
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if (byte_sel[2])
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data[23:16] <= #Tp p_in[23:16];
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if (byte_sel[1])
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data[15:8] <= #Tp p_in[15:8];
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if (byte_sel[0])
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data[7:0] <= #Tp p_in[7:0];
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end
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else if (latch[1] && !tip)
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begin
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if (byte_sel[3])
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data[63:56] <= #Tp p_in[31:24];
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if (byte_sel[2])
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data[55:48] <= #Tp p_in[23:16];
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if (byte_sel[1])
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data[47:40] <= #Tp p_in[15:8];
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if (byte_sel[0])
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data[39:32] <= #Tp p_in[7:0];
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end
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else if (latch[2] && !tip)
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begin
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if (byte_sel[3])
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data[95:88] <= #Tp p_in[31:24];
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if (byte_sel[2])
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data[87:80] <= #Tp p_in[23:16];
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if (byte_sel[1])
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data[79:72] <= #Tp p_in[15:8];
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if (byte_sel[0])
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data[71:64] <= #Tp p_in[7:0];
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end
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else if (latch[3] && !tip)
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begin
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if (byte_sel[3])
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data[127:120] <= #Tp p_in[31:24];
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if (byte_sel[2])
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data[119:112] <= #Tp p_in[23:16];
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if (byte_sel[1])
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data[111:104] <= #Tp p_in[15:8];
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if (byte_sel[0])
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data[103:96] <= #Tp p_in[7:0];
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end
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`else
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`ifdef SPI_MAX_CHAR_64
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else if (latch[0] && !tip)
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begin
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if (byte_sel[3])
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data[31:24] <= #Tp p_in[31:24];
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if (byte_sel[2])
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data[23:16] <= #Tp p_in[23:16];
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if (byte_sel[1])
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data[15:8] <= #Tp p_in[15:8];
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if (byte_sel[0])
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data[7:0] <= #Tp p_in[7:0];
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end
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else if (latch[1] && !tip)
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begin
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if (byte_sel[3])
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data[63:56] <= #Tp p_in[31:24];
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if (byte_sel[2])
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data[55:48] <= #Tp p_in[23:16];
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if (byte_sel[1])
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data[47:40] <= #Tp p_in[15:8];
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if (byte_sel[0])
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data[39:32] <= #Tp p_in[7:0];
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end
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`else
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else if (latch[0] && !tip)
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begin
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`ifdef SPI_MAX_CHAR_8
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if (byte_sel[0])
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data[`SPI_MAX_CHAR-1:0] <= #Tp p_in[`SPI_MAX_CHAR-1:0];
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`endif
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`ifdef SPI_MAX_CHAR_16
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if (byte_sel[0])
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data[7:0] <= #Tp p_in[7:0];
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if (byte_sel[1])
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data[`SPI_MAX_CHAR-1:8] <= #Tp p_in[`SPI_MAX_CHAR-1:8];
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`endif
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`ifdef SPI_MAX_CHAR_24
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if (byte_sel[0])
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data[7:0] <= #Tp p_in[7:0];
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if (byte_sel[1])
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data[15:8] <= #Tp p_in[15:8];
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if (byte_sel[2])
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data[`SPI_MAX_CHAR-1:16] <= #Tp p_in[`SPI_MAX_CHAR-1:16];
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`endif
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`ifdef SPI_MAX_CHAR_32
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if (byte_sel[0])
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data[7:0] <= #Tp p_in[7:0];
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if (byte_sel[1])
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data[15:8] <= #Tp p_in[15:8];
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if (byte_sel[2])
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data[23:16] <= #Tp p_in[23:16];
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if (byte_sel[3])
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data[`SPI_MAX_CHAR-1:24] <= #Tp p_in[`SPI_MAX_CHAR-1:24];
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`endif
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end
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`endif
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`endif
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else
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data[rx_bit_pos[`SPI_CHAR_LEN_BITS-1:0]] <= #Tp rx_clk ? s_in : data[rx_bit_pos[`SPI_CHAR_LEN_BITS-1:0]];
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end
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endmodule
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