15395 lines
2.0 MiB
Plaintext
15395 lines
2.0 MiB
Plaintext
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# Generated by Yosys 0.7+449 (git sha1 0659d9e, gcc 5.4.1-2ubuntu1~16.04 -fPIC -Os)
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.model sha1
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.inputs clk_i rst_i text_i[0] text_i[1] text_i[2] text_i[3] text_i[4] text_i[5] text_i[6] text_i[7] text_i[8] text_i[9] text_i[10] text_i[11] text_i[12] text_i[13] text_i[14] text_i[15] text_i[16] text_i[17] text_i[18] text_i[19] text_i[20] text_i[21] text_i[22] text_i[23] text_i[24] text_i[25] text_i[26] text_i[27] text_i[28] text_i[29] text_i[30] text_i[31] cmd_i[0] cmd_i[1] cmd_i[2] cmd_w_i
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.outputs text_o[0] text_o[1] text_o[2] text_o[3] text_o[4] text_o[5] text_o[6] text_o[7] text_o[8] text_o[9] text_o[10] text_o[11] text_o[12] text_o[13] text_o[14] text_o[15] text_o[16] text_o[17] text_o[18] text_o[19] text_o[20] text_o[21] text_o[22] text_o[23] text_o[24] text_o[25] text_o[26] text_o[27] text_o[28] text_o[29] text_o[30] text_o[31] cmd_o[0] cmd_o[1] cmd_o[2] cmd_o[3]
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.names $false
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.names $true
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1
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.names $undef
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.subckt $add A[0]=A[27] A[1]=A[28] A[2]=A[29] A[3]=A[30] A[4]=A[31] A[5]=A[0] A[6]=A[1] A[7]=A[2] A[8]=A[3] A[9]=A[4] A[10]=A[5] A[11]=A[6] A[12]=A[7] A[13]=A[8] A[14]=A[9] A[15]=A[10] A[16]=A[11] A[17]=A[12] A[18]=A[13] A[19]=A[14] A[20]=A[15] A[21]=A[16] A[22]=A[17] A[23]=A[18] A[24]=A[19] A[25]=A[20] A[26]=A[21] A[27]=A[22] A[28]=A[23] A[29]=A[24] A[30]=A[25] A[31]=A[26] B[0]=SHA1_ft_BCD[0] B[1]=SHA1_ft_BCD[1] B[2]=SHA1_ft_BCD[2] B[3]=SHA1_ft_BCD[3] B[4]=SHA1_ft_BCD[4] B[5]=SHA1_ft_BCD[5] B[6]=SHA1_ft_BCD[6] B[7]=SHA1_ft_BCD[7] B[8]=SHA1_ft_BCD[8] B[9]=SHA1_ft_BCD[9] B[10]=SHA1_ft_BCD[10] B[11]=SHA1_ft_BCD[11] B[12]=SHA1_ft_BCD[12] B[13]=SHA1_ft_BCD[13] B[14]=SHA1_ft_BCD[14] B[15]=SHA1_ft_BCD[15] B[16]=SHA1_ft_BCD[16] B[17]=SHA1_ft_BCD[17] B[18]=SHA1_ft_BCD[18] B[19]=SHA1_ft_BCD[19] B[20]=SHA1_ft_BCD[20] B[21]=SHA1_ft_BCD[21] B[22]=SHA1_ft_BCD[22] B[23]=SHA1_ft_BCD[23] B[24]=SHA1_ft_BCD[24] B[25]=SHA1_ft_BCD[25] B[26]=SHA1_ft_BCD[26] B[27]=SHA1_ft_BCD[27] B[28]=SHA1_ft_BCD[28] B[29]=SHA1_ft_BCD[29] B[30]=SHA1_ft_BCD[30] B[31]=SHA1_ft_BCD[31] Y[0]=$add$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:138$23_Y[0] Y[1]=$add$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:138$23_Y[1] Y[2]=$add$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:138$23_Y[2] Y[3]=$add$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:138$23_Y[3] Y[4]=$add$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:138$23_Y[4] Y[5]=$add$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:138$23_Y[5] Y[6]=$add$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:138$23_Y[6] Y[7]=$add$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:138$23_Y[7] Y[8]=$add$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:138$23_Y[8] Y[9]=$add$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:138$23_Y[9] Y[10]=$add$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:138$23_Y[10] Y[11]=$add$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:138$23_Y[11] Y[12]=$add$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:138$23_Y[12] Y[13]=$add$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:138$23_Y[13] Y[14]=$add$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:138$23_Y[14] Y[15]=$add$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:138$23_Y[15] Y[16]=$add$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:138$23_Y[16] Y[17]=$add$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:138$23_Y[17] Y[18]=$add$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:138$23_Y[18] Y[19]=$add$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:138$23_Y[19] Y[20]=$add$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:138$23_Y[20] Y[21]=$add$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:138$23_Y[21] Y[22]=$add$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:138$23_Y[22] Y[23]=$add$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:138$23_Y[23] Y[24]=$add$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:138$23_Y[24] Y[25]=$add$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:138$23_Y[25] Y[26]=$add$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:138$23_Y[26] Y[27]=$add$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:138$23_Y[27] Y[28]=$add$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:138$23_Y[28] Y[29]=$add$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:138$23_Y[29] Y[30]=$add$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:138$23_Y[30] Y[31]=$add$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:138$23_Y[31]
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.cname $add$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:138$23
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.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:138"
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.param A_SIGNED 00000000000000000000000000000000
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.param A_WIDTH 00000000000000000000000000100000
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.param B_SIGNED 00000000000000000000000000000000
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.param B_WIDTH 00000000000000000000000000100000
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.param Y_WIDTH 00000000000000000000000000100000
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.subckt $add A[0]=$add$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:138$23_Y[0] A[1]=$add$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:138$23_Y[1] A[2]=$add$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:138$23_Y[2] A[3]=$add$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:138$23_Y[3] A[4]=$add$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:138$23_Y[4] A[5]=$add$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:138$23_Y[5] A[6]=$add$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:138$23_Y[6] A[7]=$add$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:138$23_Y[7] A[8]=$add$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:138$23_Y[8] A[9]=$add$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:138$23_Y[9] A[10]=$add$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:138$23_Y[10] A[11]=$add$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:138$23_Y[11] A[12]=$add$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:138$23_Y[12] A[13]=$add$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:138$23_Y[13] A[14]=$add$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:138$23_Y[14] A[15]=$add$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:138$23_Y[15] A[16]=$add$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:138$23_Y[16] A[17]=$add$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:138$23_Y[17] A[18]=$add$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:138$23_Y[18] A[19]=$add$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:138$23_Y[19] A[20]=$add$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:138$23_Y[20] A[21]=$add$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:138$23_Y[21] A[22]=$add$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:138$23_Y[22] A[23]=$add$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:138$23_Y[23] A[24]=$add$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:138$23_Y[24] A[25]=$add$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:138$23_Y[25] A[26]=$add$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:138$23_Y[26] A[27]=$add$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:138$23_Y[27] A[28]=$add$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:138$23_Y[28] A[29]=$add$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:138$23_Y[29] A[30]=$add$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:138$23_Y[30] A[31]=$add$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:138$23_Y[31] B[0]=E[0] B[1]=E[1] B[2]=E[2] B[3]=E[3] B[4]=E[4] B[5]=E[5] B[6]=E[6] B[7]=E[7] B[8]=E[8] B[9]=E[9] B[10]=E[10] B[11]=E[11] B[12]=E[12] B[13]=E[13] B[14]=E[14] B[15]=E[15] B[16]=E[16] B[17]=E[17] B[18]=E[18] B[19]=E[19] B[20]=E[20] B[21]=E[21] B[22]=E[22] B[23]=E[23] B[24]=E[24] B[25]=E[25] B[26]=E[26] B[27]=E[27] B[28]=E[28] B[29]=E[29] B[30]=E[30] B[31]=E[31] Y[0]=$add$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:138$24_Y[0] Y[1]=$add$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:138$24_Y[1] Y[2]=$add$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:138$24_Y[2] Y[3]=$add$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:138$24_Y[3] Y[4]=$add$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:138$24_Y[4] Y[5]=$add$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:138$24_Y[5] Y[6]=$add$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:138$24_Y[6] Y[7]=$add$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:138$24_Y[7] Y[8]=$add$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:138$24_Y[8] Y[9]=$add$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:138$24_Y[9] Y[10]=$add$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:138$24_Y[10] Y[11]=$add$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:138$24_Y[11] Y[12]=$add$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:138$24_Y[12] Y[13]=$add$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:138$24_Y[13] Y[14]=$add$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:138$24_Y[14] Y[15]=$add$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:138$24_Y[15] Y[16]=$add$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.
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.cname $add$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:138$24
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.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:138"
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.param A_SIGNED 00000000000000000000000000000000
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.param A_WIDTH 00000000000000000000000000100000
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.param B_SIGNED 00000000000000000000000000000000
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.param B_WIDTH 00000000000000000000000000100000
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.param Y_WIDTH 00000000000000000000000000100000
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.subckt $add A[0]=$add$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:138$24_Y[0] A[1]=$add$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:138$24_Y[1] A[2]=$add$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:138$24_Y[2] A[3]=$add$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:138$24_Y[3] A[4]=$add$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:138$24_Y[4] A[5]=$add$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:138$24_Y[5] A[6]=$add$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:138$24_Y[6] A[7]=$add$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:138$24_Y[7] A[8]=$add$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:138$24_Y[8] A[9]=$add$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:138$24_Y[9] A[10]=$add$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:138$24_Y[10] A[11]=$add$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:138$24_Y[11] A[12]=$add$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:138$24_Y[12] A[13]=$add$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:138$24_Y[13] A[14]=$add$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:138$24_Y[14] A[15]=$add$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:138$24_Y[15] A[16]=$add$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:138$24_Y[16] A[17]=$add$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:138$24_Y[17] A[18]=$add$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:138$24_Y[18] A[19]=$add$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:138$24_Y[19] A[20]=$add$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:138$24_Y[20] A[21]=$add$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:138$24_Y[21] A[22]=$add$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:138$24_Y[22] A[23]=$add$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:138$24_Y[23] A[24]=$add$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:138$24_Y[24] A[25]=$add$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:138$24_Y[25] A[26]=$add$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:138$24_Y[26] A[27]=$add$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:138$24_Y[27] A[28]=$add$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:138$24_Y[28] A[29]=$add$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:138$24_Y[29] A[30]=$add$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:138$24_Y[30] A[31]=$add$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:138$24_Y[31] B[0]=Kt[0] B[1]=Kt[1] B[2]=Kt[2] B[3]=Kt[3] B[4]=Kt[4] B[5]=Kt[5] B[6]=Kt[6] B[7]=Kt[7] B[8]=Kt[8] B[9]=Kt[9] B[10]=Kt[10] B[11]=Kt[11] B[12]=Kt[12] B[13]=Kt[13] B[14]=Kt[14] B[15]=Kt[15] B[16]=Kt[16] B[17]=Kt[17] B[18]=Kt[18] B[19]=Kt[19] B[20]=Kt[20] B[21]=Kt[21] B[22]=Kt[22] B[23]=Kt[23] B[24]=Kt[24] B[25]=Kt[25] B[26]=Kt[26] B[27]=Kt[27] B[28]=Kt[28] B[29]=Kt[29] B[30]=Kt[30] B[31]=Kt[31] Y[0]=$add$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:138$25_Y[0] Y[1]=$add$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:138$25_Y[1] Y[2]=$add$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:138$25_Y[2] Y[3]=$add$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:138$25_Y[3] Y[4]=$add$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:138$25_Y[4] Y[5]=$add$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:138$25_Y[5] Y[6]=$add$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:138$25_Y[6] Y[7]=$add$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:138$25_Y[7] Y[8]=$add$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:138$25_Y[8] Y[9]=$add$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:138$25_Y[9] Y[10]=$add$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:138$25_Y[10] Y[11]=$add$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:138$25_Y[11] Y[12]=$add$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:138$25_Y[12] Y[13]=$add$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:138$25_Y[13] Y[14]=$add$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:138$25_Y[14] Y[15]=$add$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:138$25_Y[15] Y[16]=$add$/project/trees/vtr/
|
||
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.cname $add$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:138$25
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.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:138"
|
||
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.param A_SIGNED 00000000000000000000000000000000
|
||
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.param A_WIDTH 00000000000000000000000000100000
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||
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.param B_SIGNED 00000000000000000000000000000000
|
||
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.param B_WIDTH 00000000000000000000000000100000
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||
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.param Y_WIDTH 00000000000000000000000000100000
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||
|
|
.subckt $add A[0]=$add$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:138$25_Y[0] A[1]=$add$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:138$25_Y[1] A[2]=$add$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:138$25_Y[2] A[3]=$add$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:138$25_Y[3] A[4]=$add$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:138$25_Y[4] A[5]=$add$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:138$25_Y[5] A[6]=$add$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:138$25_Y[6] A[7]=$add$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:138$25_Y[7] A[8]=$add$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:138$25_Y[8] A[9]=$add$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:138$25_Y[9] A[10]=$add$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:138$25_Y[10] A[11]=$add$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:138$25_Y[11] A[12]=$add$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:138$25_Y[12] A[13]=$add$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:138$25_Y[13] A[14]=$add$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:138$25_Y[14] A[15]=$add$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:138$25_Y[15] A[16]=$add$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:138$25_Y[16] A[17]=$add$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:138$25_Y[17] A[18]=$add$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:138$25_Y[18] A[19]=$add$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:138$25_Y[19] A[20]=$add$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:138$25_Y[20] A[21]=$add$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:138$25_Y[21] A[22]=$add$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:138$25_Y[22] A[23]=$add$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:138$25_Y[23] A[24]=$add$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:138$25_Y[24] A[25]=$add$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:138$25_Y[25] A[26]=$add$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:138$25_Y[26] A[27]=$add$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:138$25_Y[27] A[28]=$add$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:138$25_Y[28] A[29]=$add$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:138$25_Y[29] A[30]=$add$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:138$25_Y[30] A[31]=$add$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:138$25_Y[31] B[0]=Wt[0] B[1]=Wt[1] B[2]=Wt[2] B[3]=Wt[3] B[4]=Wt[4] B[5]=Wt[5] B[6]=Wt[6] B[7]=Wt[7] B[8]=Wt[8] B[9]=Wt[9] B[10]=Wt[10] B[11]=Wt[11] B[12]=Wt[12] B[13]=Wt[13] B[14]=Wt[14] B[15]=Wt[15] B[16]=Wt[16] B[17]=Wt[17] B[18]=Wt[18] B[19]=Wt[19] B[20]=Wt[20] B[21]=Wt[21] B[22]=Wt[22] B[23]=Wt[23] B[24]=Wt[24] B[25]=Wt[25] B[26]=Wt[26] B[27]=Wt[27] B[28]=Wt[28] B[29]=Wt[29] B[30]=Wt[30] B[31]=Wt[31] Y[0]=$add$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:138$26_Y[0] Y[1]=$add$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:138$26_Y[1] Y[2]=$add$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:138$26_Y[2] Y[3]=$add$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:138$26_Y[3] Y[4]=$add$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:138$26_Y[4] Y[5]=$add$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:138$26_Y[5] Y[6]=$add$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:138$26_Y[6] Y[7]=$add$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:138$26_Y[7] Y[8]=$add$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:138$26_Y[8] Y[9]=$add$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:138$26_Y[9] Y[10]=$add$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:138$26_Y[10] Y[11]=$add$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:138$26_Y[11] Y[12]=$add$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:138$26_Y[12] Y[13]=$add$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:138$26_Y[13] Y[14]=$add$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:138$26_Y[14] Y[15]=$add$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:138$26_Y[15] Y[16]=$add$/project/trees/vtr/
|
||
|
|
.cname $add$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:138$26
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:138"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000100000
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000100000
|
||
|
|
.param Y_WIDTH 00000000000000000000000000100000
|
||
|
|
.subckt $add A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$true B[1]=$false B[2]=$false B[3]=$false B[4]=$false B[5]=$false B[6]=$false B[7]=$false B[8]=$false B[9]=$false B[10]=$false B[11]=$false B[12]=$false B[13]=$false B[14]=$false B[15]=$false B[16]=$false B[17]=$false B[18]=$false B[19]=$false B[20]=$false B[21]=$false B[22]=$false B[23]=$false B[24]=$false B[25]=$false B[26]=$false B[27]=$false B[28]=$false B[29]=$false B[30]=$false B[31]=$false Y[0]=$add$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:143$27_Y[0] Y[1]=$add$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:143$27_Y[1] Y[2]=$add$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:143$27_Y[2] Y[3]=$add$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:143$27_Y[3] Y[4]=$add$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:143$27_Y[4] Y[5]=$add$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:143$27_Y[5] Y[6]=$add$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:143$27_Y[6] Y[7]=$add$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:143$27_Y[7] Y[8]=$add$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:143$27_Y[8] Y[9]=$add$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:143$27_Y[9] Y[10]=$add$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:143$27_Y[10] Y[11]=$add$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:143$27_Y[11] Y[12]=$add$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:143$27_Y[12] Y[13]=$add$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:143$27_Y[13] Y[14]=$add$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:143$27_Y[14] Y[15]=$add$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:143$27_Y[15] Y[16]=$add$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:143$27_Y[16] Y[17]=$add$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:143$27_Y[17] Y[18]=$add$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:143$27_Y[18] Y[19]=$add$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:143$27_Y[19] Y[20]=$add$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:143$27_Y[20] Y[21]=$add$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:143$27_Y[21] Y[22]=$add$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:143$27_Y[22] Y[23]=$add$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:143$27_Y[23] Y[24]=$add$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:143$27_Y[24] Y[25]=$add$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:143$27_Y[25] Y[26]=$add$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:143$27_Y[26] Y[27]=$add$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:143$27_Y[27] Y[28]=$add$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:143$27_Y[28] Y[29]=$add$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:143$27_Y[29] Y[30]=$add$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:143$27_Y[30] Y[31]=$add$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:143$27_Y[31]
|
||
|
|
.cname $add$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:143$27
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:143"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000100000
|
||
|
|
.param Y_WIDTH 00000000000000000000000000100000
|
||
|
|
.subckt $add A[0]=next_A[0] A[1]=next_A[1] A[2]=next_A[2] A[3]=next_A[3] A[4]=next_A[4] A[5]=next_A[5] A[6]=next_A[6] A[7]=next_A[7] A[8]=next_A[8] A[9]=next_A[9] A[10]=next_A[10] A[11]=next_A[11] A[12]=next_A[12] A[13]=next_A[13] A[14]=next_A[14] A[15]=next_A[15] A[16]=next_A[16] A[17]=next_A[17] A[18]=next_A[18] A[19]=next_A[19] A[20]=next_A[20] A[21]=next_A[21] A[22]=next_A[22] A[23]=next_A[23] A[24]=next_A[24] A[25]=next_A[25] A[26]=next_A[26] A[27]=next_A[27] A[28]=next_A[28] A[29]=next_A[29] A[30]=next_A[30] A[31]=next_A[31] B[0]=H0[0] B[1]=H0[1] B[2]=H0[2] B[3]=H0[3] B[4]=H0[4] B[5]=H0[5] B[6]=H0[6] B[7]=H0[7] B[8]=H0[8] B[9]=H0[9] B[10]=H0[10] B[11]=H0[11] B[12]=H0[12] B[13]=H0[13] B[14]=H0[14] B[15]=H0[15] B[16]=H0[16] B[17]=H0[17] B[18]=H0[18] B[19]=H0[19] B[20]=H0[20] B[21]=H0[21] B[22]=H0[22] B[23]=H0[23] B[24]=H0[24] B[25]=H0[25] B[26]=H0[26] B[27]=H0[27] B[28]=H0[28] B[29]=H0[29] B[30]=H0[30] B[31]=H0[31] Y[0]=$add$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:2089$29_Y[0] Y[1]=$add$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:2089$29_Y[1] Y[2]=$add$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:2089$29_Y[2] Y[3]=$add$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:2089$29_Y[3] Y[4]=$add$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:2089$29_Y[4] Y[5]=$add$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:2089$29_Y[5] Y[6]=$add$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:2089$29_Y[6] Y[7]=$add$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:2089$29_Y[7] Y[8]=$add$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:2089$29_Y[8] Y[9]=$add$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:2089$29_Y[9] Y[10]=$add$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:2089$29_Y[10] Y[11]=$add$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:2089$29_Y[11] Y[12]=$add$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:2089$29_Y[12] Y[13]=$add$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:2089$29_Y[13] Y[14]=$add$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:2089$29_Y[14] Y[15]=$add$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:2089$29_Y[15] Y[16]=$add$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:2089$29_Y[16] Y[17]=$add$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:2089$29_Y[17] Y[18]=$add$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:2089$29_Y[18] Y[19]=$add$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:2089$29_Y[19] Y[20]=$add$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:2089$29_Y[20] Y[21]=$add$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:2089$29_Y[21] Y[22]=$add$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:2089$29_Y[22] Y[23]=$add$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:2089$29_Y[23] Y[24]=$add$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:2089$29_Y[24] Y[25]=$add$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:2089$29_Y[25] Y[26]=$add$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:2089$29_Y[26] Y[27]=$add$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:2089$29_Y[27] Y[28]=$add$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:2089$29_Y[28] Y[29]=$add$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:2089$29_Y[29] Y[30]=$add$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:2089$29_Y[30] Y[31]=$add$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:2089$29_Y[31]
|
||
|
|
.cname $add$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:2089$29
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:2089"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000100000
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000100000
|
||
|
|
.param Y_WIDTH 00000000000000000000000000100000
|
||
|
|
.subckt $add A[0]=A[0] A[1]=A[1] A[2]=A[2] A[3]=A[3] A[4]=A[4] A[5]=A[5] A[6]=A[6] A[7]=A[7] A[8]=A[8] A[9]=A[9] A[10]=A[10] A[11]=A[11] A[12]=A[12] A[13]=A[13] A[14]=A[14] A[15]=A[15] A[16]=A[16] A[17]=A[17] A[18]=A[18] A[19]=A[19] A[20]=A[20] A[21]=A[21] A[22]=A[22] A[23]=A[23] A[24]=A[24] A[25]=A[25] A[26]=A[26] A[27]=A[27] A[28]=A[28] A[29]=A[29] A[30]=A[30] A[31]=A[31] B[0]=H1[0] B[1]=H1[1] B[2]=H1[2] B[3]=H1[3] B[4]=H1[4] B[5]=H1[5] B[6]=H1[6] B[7]=H1[7] B[8]=H1[8] B[9]=H1[9] B[10]=H1[10] B[11]=H1[11] B[12]=H1[12] B[13]=H1[13] B[14]=H1[14] B[15]=H1[15] B[16]=H1[16] B[17]=H1[17] B[18]=H1[18] B[19]=H1[19] B[20]=H1[20] B[21]=H1[21] B[22]=H1[22] B[23]=H1[23] B[24]=H1[24] B[25]=H1[25] B[26]=H1[26] B[27]=H1[27] B[28]=H1[28] B[29]=H1[29] B[30]=H1[30] B[31]=H1[31] Y[0]=$add$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:2090$30_Y[0] Y[1]=$add$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:2090$30_Y[1] Y[2]=$add$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:2090$30_Y[2] Y[3]=$add$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:2090$30_Y[3] Y[4]=$add$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:2090$30_Y[4] Y[5]=$add$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:2090$30_Y[5] Y[6]=$add$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:2090$30_Y[6] Y[7]=$add$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:2090$30_Y[7] Y[8]=$add$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:2090$30_Y[8] Y[9]=$add$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:2090$30_Y[9] Y[10]=$add$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:2090$30_Y[10] Y[11]=$add$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:2090$30_Y[11] Y[12]=$add$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:2090$30_Y[12] Y[13]=$add$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:2090$30_Y[13] Y[14]=$add$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:2090$30_Y[14] Y[15]=$add$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:2090$30_Y[15] Y[16]=$add$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:2090$30_Y[16] Y[17]=$add$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:2090$30_Y[17] Y[18]=$add$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:2090$30_Y[18] Y[19]=$add$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:2090$30_Y[19] Y[20]=$add$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:2090$30_Y[20] Y[21]=$add$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:2090$30_Y[21] Y[22]=$add$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:2090$30_Y[22] Y[23]=$add$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:2090$30_Y[23] Y[24]=$add$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:2090$30_Y[24] Y[25]=$add$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:2090$30_Y[25] Y[26]=$add$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:2090$30_Y[26] Y[27]=$add$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:2090$30_Y[27] Y[28]=$add$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:2090$30_Y[28] Y[29]=$add$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:2090$30_Y[29] Y[30]=$add$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:2090$30_Y[30] Y[31]=$add$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:2090$30_Y[31]
|
||
|
|
.cname $add$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:2090$30
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:2090"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000100000
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000100000
|
||
|
|
.param Y_WIDTH 00000000000000000000000000100000
|
||
|
|
.subckt $add A[0]=next_C[0] A[1]=next_C[1] A[2]=next_C[2] A[3]=next_C[3] A[4]=next_C[4] A[5]=next_C[5] A[6]=next_C[6] A[7]=next_C[7] A[8]=next_C[8] A[9]=next_C[9] A[10]=next_C[10] A[11]=next_C[11] A[12]=next_C[12] A[13]=next_C[13] A[14]=next_C[14] A[15]=next_C[15] A[16]=next_C[16] A[17]=next_C[17] A[18]=next_C[18] A[19]=next_C[19] A[20]=next_C[20] A[21]=next_C[21] A[22]=next_C[22] A[23]=next_C[23] A[24]=next_C[24] A[25]=next_C[25] A[26]=next_C[26] A[27]=next_C[27] A[28]=next_C[28] A[29]=next_C[29] A[30]=next_C[30] A[31]=next_C[31] B[0]=H2[0] B[1]=H2[1] B[2]=H2[2] B[3]=H2[3] B[4]=H2[4] B[5]=H2[5] B[6]=H2[6] B[7]=H2[7] B[8]=H2[8] B[9]=H2[9] B[10]=H2[10] B[11]=H2[11] B[12]=H2[12] B[13]=H2[13] B[14]=H2[14] B[15]=H2[15] B[16]=H2[16] B[17]=H2[17] B[18]=H2[18] B[19]=H2[19] B[20]=H2[20] B[21]=H2[21] B[22]=H2[22] B[23]=H2[23] B[24]=H2[24] B[25]=H2[25] B[26]=H2[26] B[27]=H2[27] B[28]=H2[28] B[29]=H2[29] B[30]=H2[30] B[31]=H2[31] Y[0]=$add$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:2091$31_Y[0] Y[1]=$add$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:2091$31_Y[1] Y[2]=$add$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:2091$31_Y[2] Y[3]=$add$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:2091$31_Y[3] Y[4]=$add$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:2091$31_Y[4] Y[5]=$add$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:2091$31_Y[5] Y[6]=$add$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:2091$31_Y[6] Y[7]=$add$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:2091$31_Y[7] Y[8]=$add$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:2091$31_Y[8] Y[9]=$add$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:2091$31_Y[9] Y[10]=$add$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:2091$31_Y[10] Y[11]=$add$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:2091$31_Y[11] Y[12]=$add$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:2091$31_Y[12] Y[13]=$add$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:2091$31_Y[13] Y[14]=$add$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:2091$31_Y[14] Y[15]=$add$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:2091$31_Y[15] Y[16]=$add$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:2091$31_Y[16] Y[17]=$add$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:2091$31_Y[17] Y[18]=$add$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:2091$31_Y[18] Y[19]=$add$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:2091$31_Y[19] Y[20]=$add$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:2091$31_Y[20] Y[21]=$add$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:2091$31_Y[21] Y[22]=$add$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:2091$31_Y[22] Y[23]=$add$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:2091$31_Y[23] Y[24]=$add$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:2091$31_Y[24] Y[25]=$add$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:2091$31_Y[25] Y[26]=$add$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:2091$31_Y[26] Y[27]=$add$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:2091$31_Y[27] Y[28]=$add$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:2091$31_Y[28] Y[29]=$add$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:2091$31_Y[29] Y[30]=$add$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:2091$31_Y[30] Y[31]=$add$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:2091$31_Y[31]
|
||
|
|
.cname $add$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:2091$31
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:2091"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000100000
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000100000
|
||
|
|
.param Y_WIDTH 00000000000000000000000000100000
|
||
|
|
.subckt $add A[0]=C[0] A[1]=C[1] A[2]=C[2] A[3]=C[3] A[4]=C[4] A[5]=C[5] A[6]=C[6] A[7]=C[7] A[8]=C[8] A[9]=C[9] A[10]=C[10] A[11]=C[11] A[12]=C[12] A[13]=C[13] A[14]=C[14] A[15]=C[15] A[16]=C[16] A[17]=C[17] A[18]=C[18] A[19]=C[19] A[20]=C[20] A[21]=C[21] A[22]=C[22] A[23]=C[23] A[24]=C[24] A[25]=C[25] A[26]=C[26] A[27]=C[27] A[28]=C[28] A[29]=C[29] A[30]=C[30] A[31]=C[31] B[0]=H3[0] B[1]=H3[1] B[2]=H3[2] B[3]=H3[3] B[4]=H3[4] B[5]=H3[5] B[6]=H3[6] B[7]=H3[7] B[8]=H3[8] B[9]=H3[9] B[10]=H3[10] B[11]=H3[11] B[12]=H3[12] B[13]=H3[13] B[14]=H3[14] B[15]=H3[15] B[16]=H3[16] B[17]=H3[17] B[18]=H3[18] B[19]=H3[19] B[20]=H3[20] B[21]=H3[21] B[22]=H3[22] B[23]=H3[23] B[24]=H3[24] B[25]=H3[25] B[26]=H3[26] B[27]=H3[27] B[28]=H3[28] B[29]=H3[29] B[30]=H3[30] B[31]=H3[31] Y[0]=$add$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:2092$32_Y[0] Y[1]=$add$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:2092$32_Y[1] Y[2]=$add$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:2092$32_Y[2] Y[3]=$add$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:2092$32_Y[3] Y[4]=$add$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:2092$32_Y[4] Y[5]=$add$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:2092$32_Y[5] Y[6]=$add$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:2092$32_Y[6] Y[7]=$add$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:2092$32_Y[7] Y[8]=$add$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:2092$32_Y[8] Y[9]=$add$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:2092$32_Y[9] Y[10]=$add$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:2092$32_Y[10] Y[11]=$add$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:2092$32_Y[11] Y[12]=$add$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:2092$32_Y[12] Y[13]=$add$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:2092$32_Y[13] Y[14]=$add$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:2092$32_Y[14] Y[15]=$add$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:2092$32_Y[15] Y[16]=$add$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:2092$32_Y[16] Y[17]=$add$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:2092$32_Y[17] Y[18]=$add$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:2092$32_Y[18] Y[19]=$add$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:2092$32_Y[19] Y[20]=$add$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:2092$32_Y[20] Y[21]=$add$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:2092$32_Y[21] Y[22]=$add$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:2092$32_Y[22] Y[23]=$add$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:2092$32_Y[23] Y[24]=$add$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:2092$32_Y[24] Y[25]=$add$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:2092$32_Y[25] Y[26]=$add$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:2092$32_Y[26] Y[27]=$add$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:2092$32_Y[27] Y[28]=$add$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:2092$32_Y[28] Y[29]=$add$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:2092$32_Y[29] Y[30]=$add$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:2092$32_Y[30] Y[31]=$add$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:2092$32_Y[31]
|
||
|
|
.cname $add$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:2092$32
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:2092"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000100000
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000100000
|
||
|
|
.param Y_WIDTH 00000000000000000000000000100000
|
||
|
|
.subckt $add A[0]=D[0] A[1]=D[1] A[2]=D[2] A[3]=D[3] A[4]=D[4] A[5]=D[5] A[6]=D[6] A[7]=D[7] A[8]=D[8] A[9]=D[9] A[10]=D[10] A[11]=D[11] A[12]=D[12] A[13]=D[13] A[14]=D[14] A[15]=D[15] A[16]=D[16] A[17]=D[17] A[18]=D[18] A[19]=D[19] A[20]=D[20] A[21]=D[21] A[22]=D[22] A[23]=D[23] A[24]=D[24] A[25]=D[25] A[26]=D[26] A[27]=D[27] A[28]=D[28] A[29]=D[29] A[30]=D[30] A[31]=D[31] B[0]=H4[0] B[1]=H4[1] B[2]=H4[2] B[3]=H4[3] B[4]=H4[4] B[5]=H4[5] B[6]=H4[6] B[7]=H4[7] B[8]=H4[8] B[9]=H4[9] B[10]=H4[10] B[11]=H4[11] B[12]=H4[12] B[13]=H4[13] B[14]=H4[14] B[15]=H4[15] B[16]=H4[16] B[17]=H4[17] B[18]=H4[18] B[19]=H4[19] B[20]=H4[20] B[21]=H4[21] B[22]=H4[22] B[23]=H4[23] B[24]=H4[24] B[25]=H4[25] B[26]=H4[26] B[27]=H4[27] B[28]=H4[28] B[29]=H4[29] B[30]=H4[30] B[31]=H4[31] Y[0]=$add$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:2093$33_Y[0] Y[1]=$add$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:2093$33_Y[1] Y[2]=$add$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:2093$33_Y[2] Y[3]=$add$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:2093$33_Y[3] Y[4]=$add$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:2093$33_Y[4] Y[5]=$add$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:2093$33_Y[5] Y[6]=$add$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:2093$33_Y[6] Y[7]=$add$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:2093$33_Y[7] Y[8]=$add$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:2093$33_Y[8] Y[9]=$add$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:2093$33_Y[9] Y[10]=$add$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:2093$33_Y[10] Y[11]=$add$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:2093$33_Y[11] Y[12]=$add$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:2093$33_Y[12] Y[13]=$add$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:2093$33_Y[13] Y[14]=$add$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:2093$33_Y[14] Y[15]=$add$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:2093$33_Y[15] Y[16]=$add$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:2093$33_Y[16] Y[17]=$add$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:2093$33_Y[17] Y[18]=$add$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:2093$33_Y[18] Y[19]=$add$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:2093$33_Y[19] Y[20]=$add$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:2093$33_Y[20] Y[21]=$add$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:2093$33_Y[21] Y[22]=$add$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:2093$33_Y[22] Y[23]=$add$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:2093$33_Y[23] Y[24]=$add$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:2093$33_Y[24] Y[25]=$add$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:2093$33_Y[25] Y[26]=$add$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:2093$33_Y[26] Y[27]=$add$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:2093$33_Y[27] Y[28]=$add$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:2093$33_Y[28] Y[29]=$add$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:2093$33_Y[29] Y[30]=$add$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:2093$33_Y[30] Y[31]=$add$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:2093$33_Y[31]
|
||
|
|
.cname $add$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:2093$33
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:2093"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000100000
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000100000
|
||
|
|
.param Y_WIDTH 00000000000000000000000000100000
|
||
|
|
.subckt $and A[0]=B[0] A[1]=B[1] A[2]=B[2] A[3]=B[3] A[4]=B[4] A[5]=B[5] A[6]=B[6] A[7]=B[7] A[8]=B[8] A[9]=B[9] A[10]=B[10] A[11]=B[11] A[12]=B[12] A[13]=B[13] A[14]=B[14] A[15]=B[15] A[16]=B[16] A[17]=B[17] A[18]=B[18] A[19]=B[19] A[20]=B[20] A[21]=B[21] A[22]=B[22] A[23]=B[23] A[24]=B[24] A[25]=B[25] A[26]=B[26] A[27]=B[27] A[28]=B[28] A[29]=B[29] A[30]=B[30] A[31]=B[31] B[0]=C[0] B[1]=C[1] B[2]=C[2] B[3]=C[3] B[4]=C[4] B[5]=C[5] B[6]=C[6] B[7]=C[7] B[8]=C[8] B[9]=C[9] B[10]=C[10] B[11]=C[11] B[12]=C[12] B[13]=C[13] B[14]=C[14] B[15]=C[15] B[16]=C[16] B[17]=C[17] B[18]=C[18] B[19]=C[19] B[20]=C[20] B[21]=C[21] B[22]=C[22] B[23]=C[23] B[24]=C[24] B[25]=C[25] B[26]=C[26] B[27]=C[27] B[28]=C[28] B[29]=C[29] B[30]=C[30] B[31]=C[31] Y[0]=$and$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:127$3_Y[0] Y[1]=$and$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:127$3_Y[1] Y[2]=$and$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:127$3_Y[2] Y[3]=$and$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:127$3_Y[3] Y[4]=$and$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:127$3_Y[4] Y[5]=$and$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:127$3_Y[5] Y[6]=$and$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:127$3_Y[6] Y[7]=$and$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:127$3_Y[7] Y[8]=$and$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:127$3_Y[8] Y[9]=$and$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:127$3_Y[9] Y[10]=$and$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:127$3_Y[10] Y[11]=$and$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:127$3_Y[11] Y[12]=$and$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:127$3_Y[12] Y[13]=$and$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:127$3_Y[13] Y[14]=$and$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:127$3_Y[14] Y[15]=$and$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:127$3_Y[15] Y[16]=$and$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:127$3_Y[16] Y[17]=$and$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:127$3_Y[17] Y[18]=$and$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:127$3_Y[18] Y[19]=$and$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:127$3_Y[19] Y[20]=$and$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:127$3_Y[20] Y[21]=$and$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:127$3_Y[21] Y[22]=$and$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:127$3_Y[22] Y[23]=$and$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:127$3_Y[23] Y[24]=$and$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:127$3_Y[24] Y[25]=$and$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:127$3_Y[25] Y[26]=$and$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:127$3_Y[26] Y[27]=$and$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:127$3_Y[27] Y[28]=$and$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:127$3_Y[28] Y[29]=$and$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:127$3_Y[29] Y[30]=$and$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:127$3_Y[30] Y[31]=$and$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:127$3_Y[31]
|
||
|
|
.cname $and$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:127$3
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:127"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000100000
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000100000
|
||
|
|
.param Y_WIDTH 00000000000000000000000000100000
|
||
|
|
.subckt $and A[0]=$not$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:127$4_Y[0] A[1]=$not$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:127$4_Y[1] A[2]=$not$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:127$4_Y[2] A[3]=$not$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:127$4_Y[3] A[4]=$not$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:127$4_Y[4] A[5]=$not$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:127$4_Y[5] A[6]=$not$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:127$4_Y[6] A[7]=$not$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:127$4_Y[7] A[8]=$not$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:127$4_Y[8] A[9]=$not$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:127$4_Y[9] A[10]=$not$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:127$4_Y[10] A[11]=$not$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:127$4_Y[11] A[12]=$not$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:127$4_Y[12] A[13]=$not$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:127$4_Y[13] A[14]=$not$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:127$4_Y[14] A[15]=$not$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:127$4_Y[15] A[16]=$not$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:127$4_Y[16] A[17]=$not$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:127$4_Y[17] A[18]=$not$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:127$4_Y[18] A[19]=$not$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:127$4_Y[19] A[20]=$not$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:127$4_Y[20] A[21]=$not$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:127$4_Y[21] A[22]=$not$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:127$4_Y[22] A[23]=$not$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:127$4_Y[23] A[24]=$not$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:127$4_Y[24] A[25]=$not$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:127$4_Y[25] A[26]=$not$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:127$4_Y[26] A[27]=$not$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:127$4_Y[27] A[28]=$not$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:127$4_Y[28] A[29]=$not$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:127$4_Y[29] A[30]=$not$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:127$4_Y[30] A[31]=$not$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:127$4_Y[31] B[0]=D[0] B[1]=D[1] B[2]=D[2] B[3]=D[3] B[4]=D[4] B[5]=D[5] B[6]=D[6] B[7]=D[7] B[8]=D[8] B[9]=D[9] B[10]=D[10] B[11]=D[11] B[12]=D[12] B[13]=D[13] B[14]=D[14] B[15]=D[15] B[16]=D[16] B[17]=D[17] B[18]=D[18] B[19]=D[19] B[20]=D[20] B[21]=D[21] B[22]=D[22] B[23]=D[23] B[24]=D[24] B[25]=D[25] B[26]=D[26] B[27]=D[27] B[28]=D[28] B[29]=D[29] B[30]=D[30] B[31]=D[31] Y[0]=$and$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:127$5_Y[0] Y[1]=$and$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:127$5_Y[1] Y[2]=$and$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:127$5_Y[2] Y[3]=$and$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:127$5_Y[3] Y[4]=$and$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:127$5_Y[4] Y[5]=$and$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:127$5_Y[5] Y[6]=$and$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:127$5_Y[6] Y[7]=$and$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:127$5_Y[7] Y[8]=$and$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:127$5_Y[8] Y[9]=$and$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:127$5_Y[9] Y[10]=$and$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:127$5_Y[10] Y[11]=$and$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:127$5_Y[11] Y[12]=$and$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:127$5_Y[12] Y[13]=$and$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:127$5_Y[13] Y[14]=$and$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:127$5_Y[14] Y[15]=$and$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:127$5_Y[15] Y[16]=$and$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:127$5_Y[16] Y[17]=$and$/project/trees/vtr/vtr_
|
||
|
|
.cname $and$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:127$5
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:127"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000100000
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000100000
|
||
|
|
.param Y_WIDTH 00000000000000000000000000100000
|
||
|
|
.subckt $and A[0]=C[0] A[1]=C[1] A[2]=C[2] A[3]=C[3] A[4]=C[4] A[5]=C[5] A[6]=C[6] A[7]=C[7] A[8]=C[8] A[9]=C[9] A[10]=C[10] A[11]=C[11] A[12]=C[12] A[13]=C[13] A[14]=C[14] A[15]=C[15] A[16]=C[16] A[17]=C[17] A[18]=C[18] A[19]=C[19] A[20]=C[20] A[21]=C[21] A[22]=C[22] A[23]=C[23] A[24]=C[24] A[25]=C[25] A[26]=C[26] A[27]=C[27] A[28]=C[28] A[29]=C[29] A[30]=C[30] A[31]=C[31] B[0]=D[0] B[1]=D[1] B[2]=D[2] B[3]=D[3] B[4]=D[4] B[5]=D[5] B[6]=D[6] B[7]=D[7] B[8]=D[8] B[9]=D[9] B[10]=D[10] B[11]=D[11] B[12]=D[12] B[13]=D[13] B[14]=D[14] B[15]=D[15] B[16]=D[16] B[17]=D[17] B[18]=D[18] B[19]=D[19] B[20]=D[20] B[21]=D[21] B[22]=D[22] B[23]=D[23] B[24]=D[24] B[25]=D[25] B[26]=D[26] B[27]=D[27] B[28]=D[28] B[29]=D[29] B[30]=D[30] B[31]=D[31] Y[0]=$and$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:129$10_Y[0] Y[1]=$and$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:129$10_Y[1] Y[2]=$and$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:129$10_Y[2] Y[3]=$and$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:129$10_Y[3] Y[4]=$and$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:129$10_Y[4] Y[5]=$and$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:129$10_Y[5] Y[6]=$and$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:129$10_Y[6] Y[7]=$and$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:129$10_Y[7] Y[8]=$and$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:129$10_Y[8] Y[9]=$and$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:129$10_Y[9] Y[10]=$and$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:129$10_Y[10] Y[11]=$and$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:129$10_Y[11] Y[12]=$and$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:129$10_Y[12] Y[13]=$and$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:129$10_Y[13] Y[14]=$and$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:129$10_Y[14] Y[15]=$and$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:129$10_Y[15] Y[16]=$and$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:129$10_Y[16] Y[17]=$and$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:129$10_Y[17] Y[18]=$and$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:129$10_Y[18] Y[19]=$and$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:129$10_Y[19] Y[20]=$and$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:129$10_Y[20] Y[21]=$and$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:129$10_Y[21] Y[22]=$and$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:129$10_Y[22] Y[23]=$and$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:129$10_Y[23] Y[24]=$and$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:129$10_Y[24] Y[25]=$and$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:129$10_Y[25] Y[26]=$and$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:129$10_Y[26] Y[27]=$and$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:129$10_Y[27] Y[28]=$and$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:129$10_Y[28] Y[29]=$and$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:129$10_Y[29] Y[30]=$and$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:129$10_Y[30] Y[31]=$and$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:129$10_Y[31]
|
||
|
|
.cname $and$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:129$10
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:129"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000100000
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000100000
|
||
|
|
.param Y_WIDTH 00000000000000000000000000100000
|
||
|
|
.subckt $and A[0]=B[0] A[1]=B[1] A[2]=B[2] A[3]=B[3] A[4]=B[4] A[5]=B[5] A[6]=B[6] A[7]=B[7] A[8]=B[8] A[9]=B[9] A[10]=B[10] A[11]=B[11] A[12]=B[12] A[13]=B[13] A[14]=B[14] A[15]=B[15] A[16]=B[16] A[17]=B[17] A[18]=B[18] A[19]=B[19] A[20]=B[20] A[21]=B[21] A[22]=B[22] A[23]=B[23] A[24]=B[24] A[25]=B[25] A[26]=B[26] A[27]=B[27] A[28]=B[28] A[29]=B[29] A[30]=B[30] A[31]=B[31] B[0]=D[0] B[1]=D[1] B[2]=D[2] B[3]=D[3] B[4]=D[4] B[5]=D[5] B[6]=D[6] B[7]=D[7] B[8]=D[8] B[9]=D[9] B[10]=D[10] B[11]=D[11] B[12]=D[12] B[13]=D[13] B[14]=D[14] B[15]=D[15] B[16]=D[16] B[17]=D[17] B[18]=D[18] B[19]=D[19] B[20]=D[20] B[21]=D[21] B[22]=D[22] B[23]=D[23] B[24]=D[24] B[25]=D[25] B[26]=D[26] B[27]=D[27] B[28]=D[28] B[29]=D[29] B[30]=D[30] B[31]=D[31] Y[0]=$and$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:129$12_Y[0] Y[1]=$and$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:129$12_Y[1] Y[2]=$and$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:129$12_Y[2] Y[3]=$and$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:129$12_Y[3] Y[4]=$and$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:129$12_Y[4] Y[5]=$and$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:129$12_Y[5] Y[6]=$and$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:129$12_Y[6] Y[7]=$and$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:129$12_Y[7] Y[8]=$and$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:129$12_Y[8] Y[9]=$and$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:129$12_Y[9] Y[10]=$and$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:129$12_Y[10] Y[11]=$and$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:129$12_Y[11] Y[12]=$and$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:129$12_Y[12] Y[13]=$and$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:129$12_Y[13] Y[14]=$and$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:129$12_Y[14] Y[15]=$and$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:129$12_Y[15] Y[16]=$and$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:129$12_Y[16] Y[17]=$and$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:129$12_Y[17] Y[18]=$and$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:129$12_Y[18] Y[19]=$and$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:129$12_Y[19] Y[20]=$and$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:129$12_Y[20] Y[21]=$and$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:129$12_Y[21] Y[22]=$and$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:129$12_Y[22] Y[23]=$and$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:129$12_Y[23] Y[24]=$and$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:129$12_Y[24] Y[25]=$and$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:129$12_Y[25] Y[26]=$and$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:129$12_Y[26] Y[27]=$and$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:129$12_Y[27] Y[28]=$and$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:129$12_Y[28] Y[29]=$and$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:129$12_Y[29] Y[30]=$and$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:129$12_Y[30] Y[31]=$and$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:129$12_Y[31]
|
||
|
|
.cname $and$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:129$12
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:129"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000100000
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000100000
|
||
|
|
.param Y_WIDTH 00000000000000000000000000100000
|
||
|
|
.subckt $and A[0]=B[0] A[1]=B[1] A[2]=B[2] A[3]=B[3] A[4]=B[4] A[5]=B[5] A[6]=B[6] A[7]=B[7] A[8]=B[8] A[9]=B[9] A[10]=B[10] A[11]=B[11] A[12]=B[12] A[13]=B[13] A[14]=B[14] A[15]=B[15] A[16]=B[16] A[17]=B[17] A[18]=B[18] A[19]=B[19] A[20]=B[20] A[21]=B[21] A[22]=B[22] A[23]=B[23] A[24]=B[24] A[25]=B[25] A[26]=B[26] A[27]=B[27] A[28]=B[28] A[29]=B[29] A[30]=B[30] A[31]=B[31] B[0]=C[0] B[1]=C[1] B[2]=C[2] B[3]=C[3] B[4]=C[4] B[5]=C[5] B[6]=C[6] B[7]=C[7] B[8]=C[8] B[9]=C[9] B[10]=C[10] B[11]=C[11] B[12]=C[12] B[13]=C[13] B[14]=C[14] B[15]=C[15] B[16]=C[16] B[17]=C[17] B[18]=C[18] B[19]=C[19] B[20]=C[20] B[21]=C[21] B[22]=C[22] B[23]=C[23] B[24]=C[24] B[25]=C[25] B[26]=C[26] B[27]=C[27] B[28]=C[28] B[29]=C[29] B[30]=C[30] B[31]=C[31] Y[0]=$and$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:129$9_Y[0] Y[1]=$and$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:129$9_Y[1] Y[2]=$and$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:129$9_Y[2] Y[3]=$and$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:129$9_Y[3] Y[4]=$and$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:129$9_Y[4] Y[5]=$and$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:129$9_Y[5] Y[6]=$and$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:129$9_Y[6] Y[7]=$and$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:129$9_Y[7] Y[8]=$and$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:129$9_Y[8] Y[9]=$and$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:129$9_Y[9] Y[10]=$and$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:129$9_Y[10] Y[11]=$and$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:129$9_Y[11] Y[12]=$and$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:129$9_Y[12] Y[13]=$and$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:129$9_Y[13] Y[14]=$and$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:129$9_Y[14] Y[15]=$and$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:129$9_Y[15] Y[16]=$and$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:129$9_Y[16] Y[17]=$and$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:129$9_Y[17] Y[18]=$and$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:129$9_Y[18] Y[19]=$and$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:129$9_Y[19] Y[20]=$and$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:129$9_Y[20] Y[21]=$and$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:129$9_Y[21] Y[22]=$and$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:129$9_Y[22] Y[23]=$and$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:129$9_Y[23] Y[24]=$and$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:129$9_Y[24] Y[25]=$and$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:129$9_Y[25] Y[26]=$and$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:129$9_Y[26] Y[27]=$and$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:129$9_Y[27] Y[28]=$and$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:129$9_Y[28] Y[29]=$and$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:129$9_Y[29] Y[30]=$and$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:129$9_Y[30] Y[31]=$and$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:129$9_Y[31]
|
||
|
|
.cname $and$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:129$9
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:129"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000100000
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000100000
|
||
|
|
.param Y_WIDTH 00000000000000000000000000100000
|
||
|
|
.subckt $lt A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$true B[1]=$false B[2]=$true B[3]=$false B[4]=$false B[5]=$true B[6]=$false Y=$lt$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:131$14_Y
|
||
|
|
.cname $lt$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:131$14
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:131"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $lt A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$true B[1]=$false B[2]=$false B[3]=$true B[4]=$false B[5]=$true B[6]=$false Y=$lt$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:131$15_Y
|
||
|
|
.cname $lt$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:131$15
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:131"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $lt A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$true B[1]=$false B[2]=$true B[3]=$true B[4]=$true B[5]=$true B[6]=$true Y=$lt$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:131$16_Y
|
||
|
|
.cname $lt$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:131$16
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:131"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $lt A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$false B[1]=$false B[2]=$false B[3]=$false B[4]=$false B[5]=$true B[6]=$false Y=$lt$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:2118$35_Y
|
||
|
|
.cname $lt$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:2118$35
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:2118"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $lt A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$false B[1]=$false B[2]=$false B[3]=$false B[4]=$true B[5]=$false B[6]=$true Y=$lt$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:2121$36_Y
|
||
|
|
.cname $lt$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:2121$36
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:2121"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $lt A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$false B[1]=$false B[2]=$true B[3]=$true B[4]=$true B[5]=$true B[6]=$true Y=$lt$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:2124$37_Y
|
||
|
|
.cname $lt$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:2124$37
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:2124"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $not A=busy Y=$not$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:116$2_Y
|
||
|
|
.cname $not$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:116$2
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:116"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000001
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $not A[0]=B[0] A[1]=B[1] A[2]=B[2] A[3]=B[3] A[4]=B[4] A[5]=B[5] A[6]=B[6] A[7]=B[7] A[8]=B[8] A[9]=B[9] A[10]=B[10] A[11]=B[11] A[12]=B[12] A[13]=B[13] A[14]=B[14] A[15]=B[15] A[16]=B[16] A[17]=B[17] A[18]=B[18] A[19]=B[19] A[20]=B[20] A[21]=B[21] A[22]=B[22] A[23]=B[23] A[24]=B[24] A[25]=B[25] A[26]=B[26] A[27]=B[27] A[28]=B[28] A[29]=B[29] A[30]=B[30] A[31]=B[31] Y[0]=$not$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:127$4_Y[0] Y[1]=$not$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:127$4_Y[1] Y[2]=$not$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:127$4_Y[2] Y[3]=$not$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:127$4_Y[3] Y[4]=$not$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:127$4_Y[4] Y[5]=$not$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:127$4_Y[5] Y[6]=$not$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:127$4_Y[6] Y[7]=$not$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:127$4_Y[7] Y[8]=$not$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:127$4_Y[8] Y[9]=$not$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:127$4_Y[9] Y[10]=$not$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:127$4_Y[10] Y[11]=$not$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:127$4_Y[11] Y[12]=$not$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:127$4_Y[12] Y[13]=$not$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:127$4_Y[13] Y[14]=$not$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:127$4_Y[14] Y[15]=$not$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:127$4_Y[15] Y[16]=$not$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:127$4_Y[16] Y[17]=$not$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:127$4_Y[17] Y[18]=$not$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:127$4_Y[18] Y[19]=$not$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:127$4_Y[19] Y[20]=$not$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:127$4_Y[20] Y[21]=$not$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:127$4_Y[21] Y[22]=$not$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:127$4_Y[22] Y[23]=$not$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:127$4_Y[23] Y[24]=$not$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:127$4_Y[24] Y[25]=$not$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:127$4_Y[25] Y[26]=$not$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:127$4_Y[26] Y[27]=$not$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:127$4_Y[27] Y[28]=$not$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:127$4_Y[28] Y[29]=$not$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:127$4_Y[29] Y[30]=$not$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:127$4_Y[30] Y[31]=$not$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:127$4_Y[31]
|
||
|
|
.cname $not$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:127$4
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:127"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000100000
|
||
|
|
.param Y_WIDTH 00000000000000000000000000100000
|
||
|
|
.subckt $not A=busy Y=$not$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:2149$39_Y
|
||
|
|
.cname $not$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:2149$39
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:2149"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000001
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $dff CLK=clk_i D[0]=$procmux$68_Y[0] D[1]=$procmux$68_Y[1] D[2]=$procmux$68_Y[2] D[3]=$procmux$68_Y[3] D[4]=$procmux$68_Y[4] D[5]=$procmux$68_Y[5] D[6]=$procmux$68_Y[6] D[7]=$procmux$68_Y[7] D[8]=$procmux$68_Y[8] D[9]=$procmux$68_Y[9] D[10]=$procmux$68_Y[10] D[11]=$procmux$68_Y[11] D[12]=$procmux$68_Y[12] D[13]=$procmux$68_Y[13] D[14]=$procmux$68_Y[14] D[15]=$procmux$68_Y[15] D[16]=$procmux$68_Y[16] D[17]=$procmux$68_Y[17] D[18]=$procmux$68_Y[18] D[19]=$procmux$68_Y[19] D[20]=$procmux$68_Y[20] D[21]=$procmux$68_Y[21] D[22]=$procmux$68_Y[22] D[23]=$procmux$68_Y[23] D[24]=$procmux$68_Y[24] D[25]=$procmux$68_Y[25] D[26]=$procmux$68_Y[26] D[27]=$procmux$68_Y[27] D[28]=$procmux$68_Y[28] D[29]=$procmux$68_Y[29] D[30]=$procmux$68_Y[30] D[31]=$procmux$68_Y[31] Q[0]=text_o[0] Q[1]=text_o[1] Q[2]=text_o[2] Q[3]=text_o[3] Q[4]=text_o[4] Q[5]=text_o[5] Q[6]=text_o[6] Q[7]=text_o[7] Q[8]=text_o[8] Q[9]=text_o[9] Q[10]=text_o[10] Q[11]=text_o[11] Q[12]=text_o[12] Q[13]=text_o[13] Q[14]=text_o[14] Q[15]=text_o[15] Q[16]=text_o[16] Q[17]=text_o[17] Q[18]=text_o[18] Q[19]=text_o[19] Q[20]=text_o[20] Q[21]=text_o[21] Q[22]=text_o[22] Q[23]=text_o[23] Q[24]=text_o[24] Q[25]=text_o[25] Q[26]=text_o[26] Q[27]=text_o[27] Q[28]=text_o[28] Q[29]=text_o[29] Q[30]=text_o[30] Q[31]=text_o[31]
|
||
|
|
.cname $procdff$2358
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:2134"
|
||
|
|
.param CLK_POLARITY 1
|
||
|
|
.param WIDTH 00000000000000000000000000100000
|
||
|
|
.subckt $dff CLK=clk_i D[0]=$procmux$52_Y[0] D[1]=$procmux$52_Y[1] D[2]=$procmux$52_Y[2] Q[0]=read_counter[0] Q[1]=read_counter[1] Q[2]=read_counter[2]
|
||
|
|
.cname $procdff$2359
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:2134"
|
||
|
|
.param CLK_POLARITY 1
|
||
|
|
.param WIDTH 00000000000000000000000000000011
|
||
|
|
.subckt $dff CLK=clk_i D[0]=$procmux$80_Y[0] D[1]=$procmux$80_Y[1] D[2]=$procmux$80_Y[2] D[3]=$procmux$80_Y[3] D[4]=$procmux$80_Y[4] D[5]=$procmux$80_Y[5] D[6]=$procmux$80_Y[6] D[7]=$procmux$80_Y[7] D[8]=$procmux$80_Y[8] D[9]=$procmux$80_Y[9] D[10]=$procmux$80_Y[10] D[11]=$procmux$80_Y[11] D[12]=$procmux$80_Y[12] D[13]=$procmux$80_Y[13] D[14]=$procmux$80_Y[14] D[15]=$procmux$80_Y[15] D[16]=$procmux$80_Y[16] D[17]=$procmux$80_Y[17] D[18]=$procmux$80_Y[18] D[19]=$procmux$80_Y[19] D[20]=$procmux$80_Y[20] D[21]=$procmux$80_Y[21] D[22]=$procmux$80_Y[22] D[23]=$procmux$80_Y[23] D[24]=$procmux$80_Y[24] D[25]=$procmux$80_Y[25] D[26]=$procmux$80_Y[26] D[27]=$procmux$80_Y[27] D[28]=$procmux$80_Y[28] D[29]=$procmux$80_Y[29] D[30]=$procmux$80_Y[30] D[31]=$procmux$80_Y[31] Q[0]=Kt[0] Q[1]=Kt[1] Q[2]=Kt[2] Q[3]=Kt[3] Q[4]=Kt[4] Q[5]=Kt[5] Q[6]=Kt[6] Q[7]=Kt[7] Q[8]=Kt[8] Q[9]=Kt[9] Q[10]=Kt[10] Q[11]=Kt[11] Q[12]=Kt[12] Q[13]=Kt[13] Q[14]=Kt[14] Q[15]=Kt[15] Q[16]=Kt[16] Q[17]=Kt[17] Q[18]=Kt[18] Q[19]=Kt[19] Q[20]=Kt[20] Q[21]=Kt[21] Q[22]=Kt[22] Q[23]=Kt[23] Q[24]=Kt[24] Q[25]=Kt[25] Q[26]=Kt[26] Q[27]=Kt[27] Q[28]=Kt[28] Q[29]=Kt[29] Q[30]=Kt[30] Q[31]=Kt[31]
|
||
|
|
.cname $procdff$2360
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:2110"
|
||
|
|
.param CLK_POLARITY 1
|
||
|
|
.param WIDTH 00000000000000000000000000100000
|
||
|
|
.subckt $dff CLK=clk_i D[0]=$procmux$2335_Y[0] D[1]=$procmux$2335_Y[1] D[2]=$procmux$2335_Y[2] D[3]=$procmux$2335_Y[3] D[4]=$procmux$2335_Y[4] D[5]=$procmux$2335_Y[5] D[6]=$procmux$2335_Y[6] D[7]=$procmux$2335_Y[7] D[8]=$procmux$2335_Y[8] D[9]=$procmux$2335_Y[9] D[10]=$procmux$2335_Y[10] D[11]=$procmux$2335_Y[11] D[12]=$procmux$2335_Y[12] D[13]=$procmux$2335_Y[13] D[14]=$procmux$2335_Y[14] D[15]=$procmux$2335_Y[15] D[16]=$procmux$2335_Y[16] D[17]=$procmux$2335_Y[17] D[18]=$procmux$2335_Y[18] D[19]=$procmux$2335_Y[19] D[20]=$procmux$2335_Y[20] D[21]=$procmux$2335_Y[21] D[22]=$procmux$2335_Y[22] D[23]=$procmux$2335_Y[23] D[24]=$procmux$2335_Y[24] D[25]=$procmux$2335_Y[25] D[26]=$procmux$2335_Y[26] D[27]=$procmux$2335_Y[27] D[28]=$procmux$2335_Y[28] D[29]=$procmux$2335_Y[29] D[30]=$procmux$2335_Y[30] D[31]=$procmux$2335_Y[31] Q[0]=A[0] Q[1]=A[1] Q[2]=A[2] Q[3]=A[3] Q[4]=A[4] Q[5]=A[5] Q[6]=A[6] Q[7]=A[7] Q[8]=A[8] Q[9]=A[9] Q[10]=A[10] Q[11]=A[11] Q[12]=A[12] Q[13]=A[13] Q[14]=A[14] Q[15]=A[15] Q[16]=A[16] Q[17]=A[17] Q[18]=A[18] Q[19]=A[19] Q[20]=A[20] Q[21]=A[21] Q[22]=A[22] Q[23]=A[23] Q[24]=A[24] Q[25]=A[25] Q[26]=A[26] Q[27]=A[27] Q[28]=A[28] Q[29]=A[29] Q[30]=A[30] Q[31]=A[31]
|
||
|
|
.cname $procdff$2361
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:148"
|
||
|
|
.param CLK_POLARITY 1
|
||
|
|
.param WIDTH 00000000000000000000000000100000
|
||
|
|
.subckt $dff CLK=clk_i D[0]=$procmux$2243_Y[0] D[1]=$procmux$2243_Y[1] D[2]=$procmux$2243_Y[2] D[3]=$procmux$2243_Y[3] D[4]=$procmux$2243_Y[4] D[5]=$procmux$2243_Y[5] D[6]=$procmux$2243_Y[6] D[7]=$procmux$2243_Y[7] D[8]=$procmux$2243_Y[8] D[9]=$procmux$2243_Y[9] D[10]=$procmux$2243_Y[10] D[11]=$procmux$2243_Y[11] D[12]=$procmux$2243_Y[12] D[13]=$procmux$2243_Y[13] D[14]=$procmux$2243_Y[14] D[15]=$procmux$2243_Y[15] D[16]=$procmux$2243_Y[16] D[17]=$procmux$2243_Y[17] D[18]=$procmux$2243_Y[18] D[19]=$procmux$2243_Y[19] D[20]=$procmux$2243_Y[20] D[21]=$procmux$2243_Y[21] D[22]=$procmux$2243_Y[22] D[23]=$procmux$2243_Y[23] D[24]=$procmux$2243_Y[24] D[25]=$procmux$2243_Y[25] D[26]=$procmux$2243_Y[26] D[27]=$procmux$2243_Y[27] D[28]=$procmux$2243_Y[28] D[29]=$procmux$2243_Y[29] D[30]=$procmux$2243_Y[30] D[31]=$procmux$2243_Y[31] Q[0]=B[0] Q[1]=B[1] Q[2]=B[2] Q[3]=B[3] Q[4]=B[4] Q[5]=B[5] Q[6]=B[6] Q[7]=B[7] Q[8]=B[8] Q[9]=B[9] Q[10]=B[10] Q[11]=B[11] Q[12]=B[12] Q[13]=B[13] Q[14]=B[14] Q[15]=B[15] Q[16]=B[16] Q[17]=B[17] Q[18]=B[18] Q[19]=B[19] Q[20]=B[20] Q[21]=B[21] Q[22]=B[22] Q[23]=B[23] Q[24]=B[24] Q[25]=B[25] Q[26]=B[26] Q[27]=B[27] Q[28]=B[28] Q[29]=B[29] Q[30]=B[30] Q[31]=B[31]
|
||
|
|
.cname $procdff$2362
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:148"
|
||
|
|
.param CLK_POLARITY 1
|
||
|
|
.param WIDTH 00000000000000000000000000100000
|
||
|
|
.subckt $dff CLK=clk_i D[0]=$procmux$2151_Y[0] D[1]=$procmux$2151_Y[1] D[2]=$procmux$2151_Y[2] D[3]=$procmux$2151_Y[3] D[4]=$procmux$2151_Y[4] D[5]=$procmux$2151_Y[5] D[6]=$procmux$2151_Y[6] D[7]=$procmux$2151_Y[7] D[8]=$procmux$2151_Y[8] D[9]=$procmux$2151_Y[9] D[10]=$procmux$2151_Y[10] D[11]=$procmux$2151_Y[11] D[12]=$procmux$2151_Y[12] D[13]=$procmux$2151_Y[13] D[14]=$procmux$2151_Y[14] D[15]=$procmux$2151_Y[15] D[16]=$procmux$2151_Y[16] D[17]=$procmux$2151_Y[17] D[18]=$procmux$2151_Y[18] D[19]=$procmux$2151_Y[19] D[20]=$procmux$2151_Y[20] D[21]=$procmux$2151_Y[21] D[22]=$procmux$2151_Y[22] D[23]=$procmux$2151_Y[23] D[24]=$procmux$2151_Y[24] D[25]=$procmux$2151_Y[25] D[26]=$procmux$2151_Y[26] D[27]=$procmux$2151_Y[27] D[28]=$procmux$2151_Y[28] D[29]=$procmux$2151_Y[29] D[30]=$procmux$2151_Y[30] D[31]=$procmux$2151_Y[31] Q[0]=C[0] Q[1]=C[1] Q[2]=C[2] Q[3]=C[3] Q[4]=C[4] Q[5]=C[5] Q[6]=C[6] Q[7]=C[7] Q[8]=C[8] Q[9]=C[9] Q[10]=C[10] Q[11]=C[11] Q[12]=C[12] Q[13]=C[13] Q[14]=C[14] Q[15]=C[15] Q[16]=C[16] Q[17]=C[17] Q[18]=C[18] Q[19]=C[19] Q[20]=C[20] Q[21]=C[21] Q[22]=C[22] Q[23]=C[23] Q[24]=C[24] Q[25]=C[25] Q[26]=C[26] Q[27]=C[27] Q[28]=C[28] Q[29]=C[29] Q[30]=C[30] Q[31]=C[31]
|
||
|
|
.cname $procdff$2363
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:148"
|
||
|
|
.param CLK_POLARITY 1
|
||
|
|
.param WIDTH 00000000000000000000000000100000
|
||
|
|
.subckt $dff CLK=clk_i D[0]=$procmux$2059_Y[0] D[1]=$procmux$2059_Y[1] D[2]=$procmux$2059_Y[2] D[3]=$procmux$2059_Y[3] D[4]=$procmux$2059_Y[4] D[5]=$procmux$2059_Y[5] D[6]=$procmux$2059_Y[6] D[7]=$procmux$2059_Y[7] D[8]=$procmux$2059_Y[8] D[9]=$procmux$2059_Y[9] D[10]=$procmux$2059_Y[10] D[11]=$procmux$2059_Y[11] D[12]=$procmux$2059_Y[12] D[13]=$procmux$2059_Y[13] D[14]=$procmux$2059_Y[14] D[15]=$procmux$2059_Y[15] D[16]=$procmux$2059_Y[16] D[17]=$procmux$2059_Y[17] D[18]=$procmux$2059_Y[18] D[19]=$procmux$2059_Y[19] D[20]=$procmux$2059_Y[20] D[21]=$procmux$2059_Y[21] D[22]=$procmux$2059_Y[22] D[23]=$procmux$2059_Y[23] D[24]=$procmux$2059_Y[24] D[25]=$procmux$2059_Y[25] D[26]=$procmux$2059_Y[26] D[27]=$procmux$2059_Y[27] D[28]=$procmux$2059_Y[28] D[29]=$procmux$2059_Y[29] D[30]=$procmux$2059_Y[30] D[31]=$procmux$2059_Y[31] Q[0]=D[0] Q[1]=D[1] Q[2]=D[2] Q[3]=D[3] Q[4]=D[4] Q[5]=D[5] Q[6]=D[6] Q[7]=D[7] Q[8]=D[8] Q[9]=D[9] Q[10]=D[10] Q[11]=D[11] Q[12]=D[12] Q[13]=D[13] Q[14]=D[14] Q[15]=D[15] Q[16]=D[16] Q[17]=D[17] Q[18]=D[18] Q[19]=D[19] Q[20]=D[20] Q[21]=D[21] Q[22]=D[22] Q[23]=D[23] Q[24]=D[24] Q[25]=D[25] Q[26]=D[26] Q[27]=D[27] Q[28]=D[28] Q[29]=D[29] Q[30]=D[30] Q[31]=D[31]
|
||
|
|
.cname $procdff$2364
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:148"
|
||
|
|
.param CLK_POLARITY 1
|
||
|
|
.param WIDTH 00000000000000000000000000100000
|
||
|
|
.subckt $dff CLK=clk_i D[0]=$procmux$1967_Y[0] D[1]=$procmux$1967_Y[1] D[2]=$procmux$1967_Y[2] D[3]=$procmux$1967_Y[3] D[4]=$procmux$1967_Y[4] D[5]=$procmux$1967_Y[5] D[6]=$procmux$1967_Y[6] D[7]=$procmux$1967_Y[7] D[8]=$procmux$1967_Y[8] D[9]=$procmux$1967_Y[9] D[10]=$procmux$1967_Y[10] D[11]=$procmux$1967_Y[11] D[12]=$procmux$1967_Y[12] D[13]=$procmux$1967_Y[13] D[14]=$procmux$1967_Y[14] D[15]=$procmux$1967_Y[15] D[16]=$procmux$1967_Y[16] D[17]=$procmux$1967_Y[17] D[18]=$procmux$1967_Y[18] D[19]=$procmux$1967_Y[19] D[20]=$procmux$1967_Y[20] D[21]=$procmux$1967_Y[21] D[22]=$procmux$1967_Y[22] D[23]=$procmux$1967_Y[23] D[24]=$procmux$1967_Y[24] D[25]=$procmux$1967_Y[25] D[26]=$procmux$1967_Y[26] D[27]=$procmux$1967_Y[27] D[28]=$procmux$1967_Y[28] D[29]=$procmux$1967_Y[29] D[30]=$procmux$1967_Y[30] D[31]=$procmux$1967_Y[31] Q[0]=E[0] Q[1]=E[1] Q[2]=E[2] Q[3]=E[3] Q[4]=E[4] Q[5]=E[5] Q[6]=E[6] Q[7]=E[7] Q[8]=E[8] Q[9]=E[9] Q[10]=E[10] Q[11]=E[11] Q[12]=E[12] Q[13]=E[13] Q[14]=E[14] Q[15]=E[15] Q[16]=E[16] Q[17]=E[17] Q[18]=E[18] Q[19]=E[19] Q[20]=E[20] Q[21]=E[21] Q[22]=E[22] Q[23]=E[23] Q[24]=E[24] Q[25]=E[25] Q[26]=E[26] Q[27]=E[27] Q[28]=E[28] Q[29]=E[29] Q[30]=E[30] Q[31]=E[31]
|
||
|
|
.cname $procdff$2365
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:148"
|
||
|
|
.param CLK_POLARITY 1
|
||
|
|
.param WIDTH 00000000000000000000000000100000
|
||
|
|
.subckt $dff CLK=clk_i D[0]=$procmux$1875_Y[0] D[1]=$procmux$1875_Y[1] D[2]=$procmux$1875_Y[2] D[3]=$procmux$1875_Y[3] D[4]=$procmux$1875_Y[4] D[5]=$procmux$1875_Y[5] D[6]=$procmux$1875_Y[6] Q[0]=round[0] Q[1]=round[1] Q[2]=round[2] Q[3]=round[3] Q[4]=round[4] Q[5]=round[5] Q[6]=round[6]
|
||
|
|
.cname $procdff$2366
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:148"
|
||
|
|
.param CLK_POLARITY 1
|
||
|
|
.param WIDTH 00000000000000000000000000000111
|
||
|
|
.subckt $dff CLK=clk_i D[0]=$procmux$1786_Y[0] D[1]=$procmux$1786_Y[1] D[2]=$procmux$1786_Y[2] D[3]=$procmux$1786_Y[3] D[4]=$procmux$1786_Y[4] D[5]=$procmux$1786_Y[5] D[6]=$procmux$1786_Y[6] D[7]=$procmux$1786_Y[7] D[8]=$procmux$1786_Y[8] D[9]=$procmux$1786_Y[9] D[10]=$procmux$1786_Y[10] D[11]=$procmux$1786_Y[11] D[12]=$procmux$1786_Y[12] D[13]=$procmux$1786_Y[13] D[14]=$procmux$1786_Y[14] D[15]=$procmux$1786_Y[15] D[16]=$procmux$1786_Y[16] D[17]=$procmux$1786_Y[17] D[18]=$procmux$1786_Y[18] D[19]=$procmux$1786_Y[19] D[20]=$procmux$1786_Y[20] D[21]=$procmux$1786_Y[21] D[22]=$procmux$1786_Y[22] D[23]=$procmux$1786_Y[23] D[24]=$procmux$1786_Y[24] D[25]=$procmux$1786_Y[25] D[26]=$procmux$1786_Y[26] D[27]=$procmux$1786_Y[27] D[28]=$procmux$1786_Y[28] D[29]=$procmux$1786_Y[29] D[30]=$procmux$1786_Y[30] D[31]=$procmux$1786_Y[31] Q[0]=H0[0] Q[1]=H0[1] Q[2]=H0[2] Q[3]=H0[3] Q[4]=H0[4] Q[5]=H0[5] Q[6]=H0[6] Q[7]=H0[7] Q[8]=H0[8] Q[9]=H0[9] Q[10]=H0[10] Q[11]=H0[11] Q[12]=H0[12] Q[13]=H0[13] Q[14]=H0[14] Q[15]=H0[15] Q[16]=H0[16] Q[17]=H0[17] Q[18]=H0[18] Q[19]=H0[19] Q[20]=H0[20] Q[21]=H0[21] Q[22]=H0[22] Q[23]=H0[23] Q[24]=H0[24] Q[25]=H0[25] Q[26]=H0[26] Q[27]=H0[27] Q[28]=H0[28] Q[29]=H0[29] Q[30]=H0[30] Q[31]=H0[31]
|
||
|
|
.cname $procdff$2367
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:148"
|
||
|
|
.param CLK_POLARITY 1
|
||
|
|
.param WIDTH 00000000000000000000000000100000
|
||
|
|
.subckt $dff CLK=clk_i D[0]=$procmux$1694_Y[0] D[1]=$procmux$1694_Y[1] D[2]=$procmux$1694_Y[2] D[3]=$procmux$1694_Y[3] D[4]=$procmux$1694_Y[4] D[5]=$procmux$1694_Y[5] D[6]=$procmux$1694_Y[6] D[7]=$procmux$1694_Y[7] D[8]=$procmux$1694_Y[8] D[9]=$procmux$1694_Y[9] D[10]=$procmux$1694_Y[10] D[11]=$procmux$1694_Y[11] D[12]=$procmux$1694_Y[12] D[13]=$procmux$1694_Y[13] D[14]=$procmux$1694_Y[14] D[15]=$procmux$1694_Y[15] D[16]=$procmux$1694_Y[16] D[17]=$procmux$1694_Y[17] D[18]=$procmux$1694_Y[18] D[19]=$procmux$1694_Y[19] D[20]=$procmux$1694_Y[20] D[21]=$procmux$1694_Y[21] D[22]=$procmux$1694_Y[22] D[23]=$procmux$1694_Y[23] D[24]=$procmux$1694_Y[24] D[25]=$procmux$1694_Y[25] D[26]=$procmux$1694_Y[26] D[27]=$procmux$1694_Y[27] D[28]=$procmux$1694_Y[28] D[29]=$procmux$1694_Y[29] D[30]=$procmux$1694_Y[30] D[31]=$procmux$1694_Y[31] Q[0]=H1[0] Q[1]=H1[1] Q[2]=H1[2] Q[3]=H1[3] Q[4]=H1[4] Q[5]=H1[5] Q[6]=H1[6] Q[7]=H1[7] Q[8]=H1[8] Q[9]=H1[9] Q[10]=H1[10] Q[11]=H1[11] Q[12]=H1[12] Q[13]=H1[13] Q[14]=H1[14] Q[15]=H1[15] Q[16]=H1[16] Q[17]=H1[17] Q[18]=H1[18] Q[19]=H1[19] Q[20]=H1[20] Q[21]=H1[21] Q[22]=H1[22] Q[23]=H1[23] Q[24]=H1[24] Q[25]=H1[25] Q[26]=H1[26] Q[27]=H1[27] Q[28]=H1[28] Q[29]=H1[29] Q[30]=H1[30] Q[31]=H1[31]
|
||
|
|
.cname $procdff$2368
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:148"
|
||
|
|
.param CLK_POLARITY 1
|
||
|
|
.param WIDTH 00000000000000000000000000100000
|
||
|
|
.subckt $dff CLK=clk_i D[0]=$procmux$1602_Y[0] D[1]=$procmux$1602_Y[1] D[2]=$procmux$1602_Y[2] D[3]=$procmux$1602_Y[3] D[4]=$procmux$1602_Y[4] D[5]=$procmux$1602_Y[5] D[6]=$procmux$1602_Y[6] D[7]=$procmux$1602_Y[7] D[8]=$procmux$1602_Y[8] D[9]=$procmux$1602_Y[9] D[10]=$procmux$1602_Y[10] D[11]=$procmux$1602_Y[11] D[12]=$procmux$1602_Y[12] D[13]=$procmux$1602_Y[13] D[14]=$procmux$1602_Y[14] D[15]=$procmux$1602_Y[15] D[16]=$procmux$1602_Y[16] D[17]=$procmux$1602_Y[17] D[18]=$procmux$1602_Y[18] D[19]=$procmux$1602_Y[19] D[20]=$procmux$1602_Y[20] D[21]=$procmux$1602_Y[21] D[22]=$procmux$1602_Y[22] D[23]=$procmux$1602_Y[23] D[24]=$procmux$1602_Y[24] D[25]=$procmux$1602_Y[25] D[26]=$procmux$1602_Y[26] D[27]=$procmux$1602_Y[27] D[28]=$procmux$1602_Y[28] D[29]=$procmux$1602_Y[29] D[30]=$procmux$1602_Y[30] D[31]=$procmux$1602_Y[31] Q[0]=H2[0] Q[1]=H2[1] Q[2]=H2[2] Q[3]=H2[3] Q[4]=H2[4] Q[5]=H2[5] Q[6]=H2[6] Q[7]=H2[7] Q[8]=H2[8] Q[9]=H2[9] Q[10]=H2[10] Q[11]=H2[11] Q[12]=H2[12] Q[13]=H2[13] Q[14]=H2[14] Q[15]=H2[15] Q[16]=H2[16] Q[17]=H2[17] Q[18]=H2[18] Q[19]=H2[19] Q[20]=H2[20] Q[21]=H2[21] Q[22]=H2[22] Q[23]=H2[23] Q[24]=H2[24] Q[25]=H2[25] Q[26]=H2[26] Q[27]=H2[27] Q[28]=H2[28] Q[29]=H2[29] Q[30]=H2[30] Q[31]=H2[31]
|
||
|
|
.cname $procdff$2369
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:148"
|
||
|
|
.param CLK_POLARITY 1
|
||
|
|
.param WIDTH 00000000000000000000000000100000
|
||
|
|
.subckt $dff CLK=clk_i D[0]=$procmux$1510_Y[0] D[1]=$procmux$1510_Y[1] D[2]=$procmux$1510_Y[2] D[3]=$procmux$1510_Y[3] D[4]=$procmux$1510_Y[4] D[5]=$procmux$1510_Y[5] D[6]=$procmux$1510_Y[6] D[7]=$procmux$1510_Y[7] D[8]=$procmux$1510_Y[8] D[9]=$procmux$1510_Y[9] D[10]=$procmux$1510_Y[10] D[11]=$procmux$1510_Y[11] D[12]=$procmux$1510_Y[12] D[13]=$procmux$1510_Y[13] D[14]=$procmux$1510_Y[14] D[15]=$procmux$1510_Y[15] D[16]=$procmux$1510_Y[16] D[17]=$procmux$1510_Y[17] D[18]=$procmux$1510_Y[18] D[19]=$procmux$1510_Y[19] D[20]=$procmux$1510_Y[20] D[21]=$procmux$1510_Y[21] D[22]=$procmux$1510_Y[22] D[23]=$procmux$1510_Y[23] D[24]=$procmux$1510_Y[24] D[25]=$procmux$1510_Y[25] D[26]=$procmux$1510_Y[26] D[27]=$procmux$1510_Y[27] D[28]=$procmux$1510_Y[28] D[29]=$procmux$1510_Y[29] D[30]=$procmux$1510_Y[30] D[31]=$procmux$1510_Y[31] Q[0]=H3[0] Q[1]=H3[1] Q[2]=H3[2] Q[3]=H3[3] Q[4]=H3[4] Q[5]=H3[5] Q[6]=H3[6] Q[7]=H3[7] Q[8]=H3[8] Q[9]=H3[9] Q[10]=H3[10] Q[11]=H3[11] Q[12]=H3[12] Q[13]=H3[13] Q[14]=H3[14] Q[15]=H3[15] Q[16]=H3[16] Q[17]=H3[17] Q[18]=H3[18] Q[19]=H3[19] Q[20]=H3[20] Q[21]=H3[21] Q[22]=H3[22] Q[23]=H3[23] Q[24]=H3[24] Q[25]=H3[25] Q[26]=H3[26] Q[27]=H3[27] Q[28]=H3[28] Q[29]=H3[29] Q[30]=H3[30] Q[31]=H3[31]
|
||
|
|
.cname $procdff$2370
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:148"
|
||
|
|
.param CLK_POLARITY 1
|
||
|
|
.param WIDTH 00000000000000000000000000100000
|
||
|
|
.subckt $dff CLK=clk_i D[0]=$procmux$1418_Y[0] D[1]=$procmux$1418_Y[1] D[2]=$procmux$1418_Y[2] D[3]=$procmux$1418_Y[3] D[4]=$procmux$1418_Y[4] D[5]=$procmux$1418_Y[5] D[6]=$procmux$1418_Y[6] D[7]=$procmux$1418_Y[7] D[8]=$procmux$1418_Y[8] D[9]=$procmux$1418_Y[9] D[10]=$procmux$1418_Y[10] D[11]=$procmux$1418_Y[11] D[12]=$procmux$1418_Y[12] D[13]=$procmux$1418_Y[13] D[14]=$procmux$1418_Y[14] D[15]=$procmux$1418_Y[15] D[16]=$procmux$1418_Y[16] D[17]=$procmux$1418_Y[17] D[18]=$procmux$1418_Y[18] D[19]=$procmux$1418_Y[19] D[20]=$procmux$1418_Y[20] D[21]=$procmux$1418_Y[21] D[22]=$procmux$1418_Y[22] D[23]=$procmux$1418_Y[23] D[24]=$procmux$1418_Y[24] D[25]=$procmux$1418_Y[25] D[26]=$procmux$1418_Y[26] D[27]=$procmux$1418_Y[27] D[28]=$procmux$1418_Y[28] D[29]=$procmux$1418_Y[29] D[30]=$procmux$1418_Y[30] D[31]=$procmux$1418_Y[31] Q[0]=H4[0] Q[1]=H4[1] Q[2]=H4[2] Q[3]=H4[3] Q[4]=H4[4] Q[5]=H4[5] Q[6]=H4[6] Q[7]=H4[7] Q[8]=H4[8] Q[9]=H4[9] Q[10]=H4[10] Q[11]=H4[11] Q[12]=H4[12] Q[13]=H4[13] Q[14]=H4[14] Q[15]=H4[15] Q[16]=H4[16] Q[17]=H4[17] Q[18]=H4[18] Q[19]=H4[19] Q[20]=H4[20] Q[21]=H4[21] Q[22]=H4[22] Q[23]=H4[23] Q[24]=H4[24] Q[25]=H4[25] Q[26]=H4[26] Q[27]=H4[27] Q[28]=H4[28] Q[29]=H4[29] Q[30]=H4[30] Q[31]=H4[31]
|
||
|
|
.cname $procdff$2371
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:148"
|
||
|
|
.param CLK_POLARITY 1
|
||
|
|
.param WIDTH 00000000000000000000000000100000
|
||
|
|
.subckt $dff CLK=clk_i D[0]=$procmux$1326_Y[0] D[1]=$procmux$1326_Y[1] D[2]=$procmux$1326_Y[2] D[3]=$procmux$1326_Y[3] D[4]=$procmux$1326_Y[4] D[5]=$procmux$1326_Y[5] D[6]=$procmux$1326_Y[6] D[7]=$procmux$1326_Y[7] D[8]=$procmux$1326_Y[8] D[9]=$procmux$1326_Y[9] D[10]=$procmux$1326_Y[10] D[11]=$procmux$1326_Y[11] D[12]=$procmux$1326_Y[12] D[13]=$procmux$1326_Y[13] D[14]=$procmux$1326_Y[14] D[15]=$procmux$1326_Y[15] D[16]=$procmux$1326_Y[16] D[17]=$procmux$1326_Y[17] D[18]=$procmux$1326_Y[18] D[19]=$procmux$1326_Y[19] D[20]=$procmux$1326_Y[20] D[21]=$procmux$1326_Y[21] D[22]=$procmux$1326_Y[22] D[23]=$procmux$1326_Y[23] D[24]=$procmux$1326_Y[24] D[25]=$procmux$1326_Y[25] D[26]=$procmux$1326_Y[26] D[27]=$procmux$1326_Y[27] D[28]=$procmux$1326_Y[28] D[29]=$procmux$1326_Y[29] D[30]=$procmux$1326_Y[30] D[31]=$procmux$1326_Y[31] Q[0]=W0[0] Q[1]=W0[1] Q[2]=W0[2] Q[3]=W0[3] Q[4]=W0[4] Q[5]=W0[5] Q[6]=W0[6] Q[7]=W0[7] Q[8]=W0[8] Q[9]=W0[9] Q[10]=W0[10] Q[11]=W0[11] Q[12]=W0[12] Q[13]=W0[13] Q[14]=W0[14] Q[15]=W0[15] Q[16]=W0[16] Q[17]=W0[17] Q[18]=W0[18] Q[19]=W0[19] Q[20]=W0[20] Q[21]=W0[21] Q[22]=W0[22] Q[23]=W0[23] Q[24]=W0[24] Q[25]=W0[25] Q[26]=W0[26] Q[27]=W0[27] Q[28]=W0[28] Q[29]=W0[29] Q[30]=W0[30] Q[31]=W0[31]
|
||
|
|
.cname $procdff$2372
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:148"
|
||
|
|
.param CLK_POLARITY 1
|
||
|
|
.param WIDTH 00000000000000000000000000100000
|
||
|
|
.subckt $dff CLK=clk_i D[0]=$procmux$1252_Y[0] D[1]=$procmux$1252_Y[1] D[2]=$procmux$1252_Y[2] D[3]=$procmux$1252_Y[3] D[4]=$procmux$1252_Y[4] D[5]=$procmux$1252_Y[5] D[6]=$procmux$1252_Y[6] D[7]=$procmux$1252_Y[7] D[8]=$procmux$1252_Y[8] D[9]=$procmux$1252_Y[9] D[10]=$procmux$1252_Y[10] D[11]=$procmux$1252_Y[11] D[12]=$procmux$1252_Y[12] D[13]=$procmux$1252_Y[13] D[14]=$procmux$1252_Y[14] D[15]=$procmux$1252_Y[15] D[16]=$procmux$1252_Y[16] D[17]=$procmux$1252_Y[17] D[18]=$procmux$1252_Y[18] D[19]=$procmux$1252_Y[19] D[20]=$procmux$1252_Y[20] D[21]=$procmux$1252_Y[21] D[22]=$procmux$1252_Y[22] D[23]=$procmux$1252_Y[23] D[24]=$procmux$1252_Y[24] D[25]=$procmux$1252_Y[25] D[26]=$procmux$1252_Y[26] D[27]=$procmux$1252_Y[27] D[28]=$procmux$1252_Y[28] D[29]=$procmux$1252_Y[29] D[30]=$procmux$1252_Y[30] D[31]=$procmux$1252_Y[31] Q[0]=W1[0] Q[1]=W1[1] Q[2]=W1[2] Q[3]=W1[3] Q[4]=W1[4] Q[5]=W1[5] Q[6]=W1[6] Q[7]=W1[7] Q[8]=W1[8] Q[9]=W1[9] Q[10]=W1[10] Q[11]=W1[11] Q[12]=W1[12] Q[13]=W1[13] Q[14]=W1[14] Q[15]=W1[15] Q[16]=W1[16] Q[17]=W1[17] Q[18]=W1[18] Q[19]=W1[19] Q[20]=W1[20] Q[21]=W1[21] Q[22]=W1[22] Q[23]=W1[23] Q[24]=W1[24] Q[25]=W1[25] Q[26]=W1[26] Q[27]=W1[27] Q[28]=W1[28] Q[29]=W1[29] Q[30]=W1[30] Q[31]=W1[31]
|
||
|
|
.cname $procdff$2373
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:148"
|
||
|
|
.param CLK_POLARITY 1
|
||
|
|
.param WIDTH 00000000000000000000000000100000
|
||
|
|
.subckt $dff CLK=clk_i D[0]=$procmux$1181_Y[0] D[1]=$procmux$1181_Y[1] D[2]=$procmux$1181_Y[2] D[3]=$procmux$1181_Y[3] D[4]=$procmux$1181_Y[4] D[5]=$procmux$1181_Y[5] D[6]=$procmux$1181_Y[6] D[7]=$procmux$1181_Y[7] D[8]=$procmux$1181_Y[8] D[9]=$procmux$1181_Y[9] D[10]=$procmux$1181_Y[10] D[11]=$procmux$1181_Y[11] D[12]=$procmux$1181_Y[12] D[13]=$procmux$1181_Y[13] D[14]=$procmux$1181_Y[14] D[15]=$procmux$1181_Y[15] D[16]=$procmux$1181_Y[16] D[17]=$procmux$1181_Y[17] D[18]=$procmux$1181_Y[18] D[19]=$procmux$1181_Y[19] D[20]=$procmux$1181_Y[20] D[21]=$procmux$1181_Y[21] D[22]=$procmux$1181_Y[22] D[23]=$procmux$1181_Y[23] D[24]=$procmux$1181_Y[24] D[25]=$procmux$1181_Y[25] D[26]=$procmux$1181_Y[26] D[27]=$procmux$1181_Y[27] D[28]=$procmux$1181_Y[28] D[29]=$procmux$1181_Y[29] D[30]=$procmux$1181_Y[30] D[31]=$procmux$1181_Y[31] Q[0]=W2[0] Q[1]=W2[1] Q[2]=W2[2] Q[3]=W2[3] Q[4]=W2[4] Q[5]=W2[5] Q[6]=W2[6] Q[7]=W2[7] Q[8]=W2[8] Q[9]=W2[9] Q[10]=W2[10] Q[11]=W2[11] Q[12]=W2[12] Q[13]=W2[13] Q[14]=W2[14] Q[15]=W2[15] Q[16]=W2[16] Q[17]=W2[17] Q[18]=W2[18] Q[19]=W2[19] Q[20]=W2[20] Q[21]=W2[21] Q[22]=W2[22] Q[23]=W2[23] Q[24]=W2[24] Q[25]=W2[25] Q[26]=W2[26] Q[27]=W2[27] Q[28]=W2[28] Q[29]=W2[29] Q[30]=W2[30] Q[31]=W2[31]
|
||
|
|
.cname $procdff$2374
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:148"
|
||
|
|
.param CLK_POLARITY 1
|
||
|
|
.param WIDTH 00000000000000000000000000100000
|
||
|
|
.subckt $dff CLK=clk_i D[0]=$procmux$1110_Y[0] D[1]=$procmux$1110_Y[1] D[2]=$procmux$1110_Y[2] D[3]=$procmux$1110_Y[3] D[4]=$procmux$1110_Y[4] D[5]=$procmux$1110_Y[5] D[6]=$procmux$1110_Y[6] D[7]=$procmux$1110_Y[7] D[8]=$procmux$1110_Y[8] D[9]=$procmux$1110_Y[9] D[10]=$procmux$1110_Y[10] D[11]=$procmux$1110_Y[11] D[12]=$procmux$1110_Y[12] D[13]=$procmux$1110_Y[13] D[14]=$procmux$1110_Y[14] D[15]=$procmux$1110_Y[15] D[16]=$procmux$1110_Y[16] D[17]=$procmux$1110_Y[17] D[18]=$procmux$1110_Y[18] D[19]=$procmux$1110_Y[19] D[20]=$procmux$1110_Y[20] D[21]=$procmux$1110_Y[21] D[22]=$procmux$1110_Y[22] D[23]=$procmux$1110_Y[23] D[24]=$procmux$1110_Y[24] D[25]=$procmux$1110_Y[25] D[26]=$procmux$1110_Y[26] D[27]=$procmux$1110_Y[27] D[28]=$procmux$1110_Y[28] D[29]=$procmux$1110_Y[29] D[30]=$procmux$1110_Y[30] D[31]=$procmux$1110_Y[31] Q[0]=W3[0] Q[1]=W3[1] Q[2]=W3[2] Q[3]=W3[3] Q[4]=W3[4] Q[5]=W3[5] Q[6]=W3[6] Q[7]=W3[7] Q[8]=W3[8] Q[9]=W3[9] Q[10]=W3[10] Q[11]=W3[11] Q[12]=W3[12] Q[13]=W3[13] Q[14]=W3[14] Q[15]=W3[15] Q[16]=W3[16] Q[17]=W3[17] Q[18]=W3[18] Q[19]=W3[19] Q[20]=W3[20] Q[21]=W3[21] Q[22]=W3[22] Q[23]=W3[23] Q[24]=W3[24] Q[25]=W3[25] Q[26]=W3[26] Q[27]=W3[27] Q[28]=W3[28] Q[29]=W3[29] Q[30]=W3[30] Q[31]=W3[31]
|
||
|
|
.cname $procdff$2375
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:148"
|
||
|
|
.param CLK_POLARITY 1
|
||
|
|
.param WIDTH 00000000000000000000000000100000
|
||
|
|
.subckt $dff CLK=clk_i D[0]=$procmux$1039_Y[0] D[1]=$procmux$1039_Y[1] D[2]=$procmux$1039_Y[2] D[3]=$procmux$1039_Y[3] D[4]=$procmux$1039_Y[4] D[5]=$procmux$1039_Y[5] D[6]=$procmux$1039_Y[6] D[7]=$procmux$1039_Y[7] D[8]=$procmux$1039_Y[8] D[9]=$procmux$1039_Y[9] D[10]=$procmux$1039_Y[10] D[11]=$procmux$1039_Y[11] D[12]=$procmux$1039_Y[12] D[13]=$procmux$1039_Y[13] D[14]=$procmux$1039_Y[14] D[15]=$procmux$1039_Y[15] D[16]=$procmux$1039_Y[16] D[17]=$procmux$1039_Y[17] D[18]=$procmux$1039_Y[18] D[19]=$procmux$1039_Y[19] D[20]=$procmux$1039_Y[20] D[21]=$procmux$1039_Y[21] D[22]=$procmux$1039_Y[22] D[23]=$procmux$1039_Y[23] D[24]=$procmux$1039_Y[24] D[25]=$procmux$1039_Y[25] D[26]=$procmux$1039_Y[26] D[27]=$procmux$1039_Y[27] D[28]=$procmux$1039_Y[28] D[29]=$procmux$1039_Y[29] D[30]=$procmux$1039_Y[30] D[31]=$procmux$1039_Y[31] Q[0]=W4[0] Q[1]=W4[1] Q[2]=W4[2] Q[3]=W4[3] Q[4]=W4[4] Q[5]=W4[5] Q[6]=W4[6] Q[7]=W4[7] Q[8]=W4[8] Q[9]=W4[9] Q[10]=W4[10] Q[11]=W4[11] Q[12]=W4[12] Q[13]=W4[13] Q[14]=W4[14] Q[15]=W4[15] Q[16]=W4[16] Q[17]=W4[17] Q[18]=W4[18] Q[19]=W4[19] Q[20]=W4[20] Q[21]=W4[21] Q[22]=W4[22] Q[23]=W4[23] Q[24]=W4[24] Q[25]=W4[25] Q[26]=W4[26] Q[27]=W4[27] Q[28]=W4[28] Q[29]=W4[29] Q[30]=W4[30] Q[31]=W4[31]
|
||
|
|
.cname $procdff$2376
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:148"
|
||
|
|
.param CLK_POLARITY 1
|
||
|
|
.param WIDTH 00000000000000000000000000100000
|
||
|
|
.subckt $dff CLK=clk_i D[0]=$procmux$968_Y[0] D[1]=$procmux$968_Y[1] D[2]=$procmux$968_Y[2] D[3]=$procmux$968_Y[3] D[4]=$procmux$968_Y[4] D[5]=$procmux$968_Y[5] D[6]=$procmux$968_Y[6] D[7]=$procmux$968_Y[7] D[8]=$procmux$968_Y[8] D[9]=$procmux$968_Y[9] D[10]=$procmux$968_Y[10] D[11]=$procmux$968_Y[11] D[12]=$procmux$968_Y[12] D[13]=$procmux$968_Y[13] D[14]=$procmux$968_Y[14] D[15]=$procmux$968_Y[15] D[16]=$procmux$968_Y[16] D[17]=$procmux$968_Y[17] D[18]=$procmux$968_Y[18] D[19]=$procmux$968_Y[19] D[20]=$procmux$968_Y[20] D[21]=$procmux$968_Y[21] D[22]=$procmux$968_Y[22] D[23]=$procmux$968_Y[23] D[24]=$procmux$968_Y[24] D[25]=$procmux$968_Y[25] D[26]=$procmux$968_Y[26] D[27]=$procmux$968_Y[27] D[28]=$procmux$968_Y[28] D[29]=$procmux$968_Y[29] D[30]=$procmux$968_Y[30] D[31]=$procmux$968_Y[31] Q[0]=W5[0] Q[1]=W5[1] Q[2]=W5[2] Q[3]=W5[3] Q[4]=W5[4] Q[5]=W5[5] Q[6]=W5[6] Q[7]=W5[7] Q[8]=W5[8] Q[9]=W5[9] Q[10]=W5[10] Q[11]=W5[11] Q[12]=W5[12] Q[13]=W5[13] Q[14]=W5[14] Q[15]=W5[15] Q[16]=W5[16] Q[17]=W5[17] Q[18]=W5[18] Q[19]=W5[19] Q[20]=W5[20] Q[21]=W5[21] Q[22]=W5[22] Q[23]=W5[23] Q[24]=W5[24] Q[25]=W5[25] Q[26]=W5[26] Q[27]=W5[27] Q[28]=W5[28] Q[29]=W5[29] Q[30]=W5[30] Q[31]=W5[31]
|
||
|
|
.cname $procdff$2377
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:148"
|
||
|
|
.param CLK_POLARITY 1
|
||
|
|
.param WIDTH 00000000000000000000000000100000
|
||
|
|
.subckt $dff CLK=clk_i D[0]=$procmux$897_Y[0] D[1]=$procmux$897_Y[1] D[2]=$procmux$897_Y[2] D[3]=$procmux$897_Y[3] D[4]=$procmux$897_Y[4] D[5]=$procmux$897_Y[5] D[6]=$procmux$897_Y[6] D[7]=$procmux$897_Y[7] D[8]=$procmux$897_Y[8] D[9]=$procmux$897_Y[9] D[10]=$procmux$897_Y[10] D[11]=$procmux$897_Y[11] D[12]=$procmux$897_Y[12] D[13]=$procmux$897_Y[13] D[14]=$procmux$897_Y[14] D[15]=$procmux$897_Y[15] D[16]=$procmux$897_Y[16] D[17]=$procmux$897_Y[17] D[18]=$procmux$897_Y[18] D[19]=$procmux$897_Y[19] D[20]=$procmux$897_Y[20] D[21]=$procmux$897_Y[21] D[22]=$procmux$897_Y[22] D[23]=$procmux$897_Y[23] D[24]=$procmux$897_Y[24] D[25]=$procmux$897_Y[25] D[26]=$procmux$897_Y[26] D[27]=$procmux$897_Y[27] D[28]=$procmux$897_Y[28] D[29]=$procmux$897_Y[29] D[30]=$procmux$897_Y[30] D[31]=$procmux$897_Y[31] Q[0]=W6[0] Q[1]=W6[1] Q[2]=W6[2] Q[3]=W6[3] Q[4]=W6[4] Q[5]=W6[5] Q[6]=W6[6] Q[7]=W6[7] Q[8]=W6[8] Q[9]=W6[9] Q[10]=W6[10] Q[11]=W6[11] Q[12]=W6[12] Q[13]=W6[13] Q[14]=W6[14] Q[15]=W6[15] Q[16]=W6[16] Q[17]=W6[17] Q[18]=W6[18] Q[19]=W6[19] Q[20]=W6[20] Q[21]=W6[21] Q[22]=W6[22] Q[23]=W6[23] Q[24]=W6[24] Q[25]=W6[25] Q[26]=W6[26] Q[27]=W6[27] Q[28]=W6[28] Q[29]=W6[29] Q[30]=W6[30] Q[31]=W6[31]
|
||
|
|
.cname $procdff$2378
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:148"
|
||
|
|
.param CLK_POLARITY 1
|
||
|
|
.param WIDTH 00000000000000000000000000100000
|
||
|
|
.subckt $dff CLK=clk_i D[0]=$procmux$826_Y[0] D[1]=$procmux$826_Y[1] D[2]=$procmux$826_Y[2] D[3]=$procmux$826_Y[3] D[4]=$procmux$826_Y[4] D[5]=$procmux$826_Y[5] D[6]=$procmux$826_Y[6] D[7]=$procmux$826_Y[7] D[8]=$procmux$826_Y[8] D[9]=$procmux$826_Y[9] D[10]=$procmux$826_Y[10] D[11]=$procmux$826_Y[11] D[12]=$procmux$826_Y[12] D[13]=$procmux$826_Y[13] D[14]=$procmux$826_Y[14] D[15]=$procmux$826_Y[15] D[16]=$procmux$826_Y[16] D[17]=$procmux$826_Y[17] D[18]=$procmux$826_Y[18] D[19]=$procmux$826_Y[19] D[20]=$procmux$826_Y[20] D[21]=$procmux$826_Y[21] D[22]=$procmux$826_Y[22] D[23]=$procmux$826_Y[23] D[24]=$procmux$826_Y[24] D[25]=$procmux$826_Y[25] D[26]=$procmux$826_Y[26] D[27]=$procmux$826_Y[27] D[28]=$procmux$826_Y[28] D[29]=$procmux$826_Y[29] D[30]=$procmux$826_Y[30] D[31]=$procmux$826_Y[31] Q[0]=W7[0] Q[1]=W7[1] Q[2]=W7[2] Q[3]=W7[3] Q[4]=W7[4] Q[5]=W7[5] Q[6]=W7[6] Q[7]=W7[7] Q[8]=W7[8] Q[9]=W7[9] Q[10]=W7[10] Q[11]=W7[11] Q[12]=W7[12] Q[13]=W7[13] Q[14]=W7[14] Q[15]=W7[15] Q[16]=W7[16] Q[17]=W7[17] Q[18]=W7[18] Q[19]=W7[19] Q[20]=W7[20] Q[21]=W7[21] Q[22]=W7[22] Q[23]=W7[23] Q[24]=W7[24] Q[25]=W7[25] Q[26]=W7[26] Q[27]=W7[27] Q[28]=W7[28] Q[29]=W7[29] Q[30]=W7[30] Q[31]=W7[31]
|
||
|
|
.cname $procdff$2379
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:148"
|
||
|
|
.param CLK_POLARITY 1
|
||
|
|
.param WIDTH 00000000000000000000000000100000
|
||
|
|
.subckt $dff CLK=clk_i D[0]=$procmux$755_Y[0] D[1]=$procmux$755_Y[1] D[2]=$procmux$755_Y[2] D[3]=$procmux$755_Y[3] D[4]=$procmux$755_Y[4] D[5]=$procmux$755_Y[5] D[6]=$procmux$755_Y[6] D[7]=$procmux$755_Y[7] D[8]=$procmux$755_Y[8] D[9]=$procmux$755_Y[9] D[10]=$procmux$755_Y[10] D[11]=$procmux$755_Y[11] D[12]=$procmux$755_Y[12] D[13]=$procmux$755_Y[13] D[14]=$procmux$755_Y[14] D[15]=$procmux$755_Y[15] D[16]=$procmux$755_Y[16] D[17]=$procmux$755_Y[17] D[18]=$procmux$755_Y[18] D[19]=$procmux$755_Y[19] D[20]=$procmux$755_Y[20] D[21]=$procmux$755_Y[21] D[22]=$procmux$755_Y[22] D[23]=$procmux$755_Y[23] D[24]=$procmux$755_Y[24] D[25]=$procmux$755_Y[25] D[26]=$procmux$755_Y[26] D[27]=$procmux$755_Y[27] D[28]=$procmux$755_Y[28] D[29]=$procmux$755_Y[29] D[30]=$procmux$755_Y[30] D[31]=$procmux$755_Y[31] Q[0]=W8[0] Q[1]=W8[1] Q[2]=W8[2] Q[3]=W8[3] Q[4]=W8[4] Q[5]=W8[5] Q[6]=W8[6] Q[7]=W8[7] Q[8]=W8[8] Q[9]=W8[9] Q[10]=W8[10] Q[11]=W8[11] Q[12]=W8[12] Q[13]=W8[13] Q[14]=W8[14] Q[15]=W8[15] Q[16]=W8[16] Q[17]=W8[17] Q[18]=W8[18] Q[19]=W8[19] Q[20]=W8[20] Q[21]=W8[21] Q[22]=W8[22] Q[23]=W8[23] Q[24]=W8[24] Q[25]=W8[25] Q[26]=W8[26] Q[27]=W8[27] Q[28]=W8[28] Q[29]=W8[29] Q[30]=W8[30] Q[31]=W8[31]
|
||
|
|
.cname $procdff$2380
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:148"
|
||
|
|
.param CLK_POLARITY 1
|
||
|
|
.param WIDTH 00000000000000000000000000100000
|
||
|
|
.subckt $dff CLK=clk_i D[0]=$procmux$684_Y[0] D[1]=$procmux$684_Y[1] D[2]=$procmux$684_Y[2] D[3]=$procmux$684_Y[3] D[4]=$procmux$684_Y[4] D[5]=$procmux$684_Y[5] D[6]=$procmux$684_Y[6] D[7]=$procmux$684_Y[7] D[8]=$procmux$684_Y[8] D[9]=$procmux$684_Y[9] D[10]=$procmux$684_Y[10] D[11]=$procmux$684_Y[11] D[12]=$procmux$684_Y[12] D[13]=$procmux$684_Y[13] D[14]=$procmux$684_Y[14] D[15]=$procmux$684_Y[15] D[16]=$procmux$684_Y[16] D[17]=$procmux$684_Y[17] D[18]=$procmux$684_Y[18] D[19]=$procmux$684_Y[19] D[20]=$procmux$684_Y[20] D[21]=$procmux$684_Y[21] D[22]=$procmux$684_Y[22] D[23]=$procmux$684_Y[23] D[24]=$procmux$684_Y[24] D[25]=$procmux$684_Y[25] D[26]=$procmux$684_Y[26] D[27]=$procmux$684_Y[27] D[28]=$procmux$684_Y[28] D[29]=$procmux$684_Y[29] D[30]=$procmux$684_Y[30] D[31]=$procmux$684_Y[31] Q[0]=W9[0] Q[1]=W9[1] Q[2]=W9[2] Q[3]=W9[3] Q[4]=W9[4] Q[5]=W9[5] Q[6]=W9[6] Q[7]=W9[7] Q[8]=W9[8] Q[9]=W9[9] Q[10]=W9[10] Q[11]=W9[11] Q[12]=W9[12] Q[13]=W9[13] Q[14]=W9[14] Q[15]=W9[15] Q[16]=W9[16] Q[17]=W9[17] Q[18]=W9[18] Q[19]=W9[19] Q[20]=W9[20] Q[21]=W9[21] Q[22]=W9[22] Q[23]=W9[23] Q[24]=W9[24] Q[25]=W9[25] Q[26]=W9[26] Q[27]=W9[27] Q[28]=W9[28] Q[29]=W9[29] Q[30]=W9[30] Q[31]=W9[31]
|
||
|
|
.cname $procdff$2381
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:148"
|
||
|
|
.param CLK_POLARITY 1
|
||
|
|
.param WIDTH 00000000000000000000000000100000
|
||
|
|
.subckt $dff CLK=clk_i D[0]=$procmux$613_Y[0] D[1]=$procmux$613_Y[1] D[2]=$procmux$613_Y[2] D[3]=$procmux$613_Y[3] D[4]=$procmux$613_Y[4] D[5]=$procmux$613_Y[5] D[6]=$procmux$613_Y[6] D[7]=$procmux$613_Y[7] D[8]=$procmux$613_Y[8] D[9]=$procmux$613_Y[9] D[10]=$procmux$613_Y[10] D[11]=$procmux$613_Y[11] D[12]=$procmux$613_Y[12] D[13]=$procmux$613_Y[13] D[14]=$procmux$613_Y[14] D[15]=$procmux$613_Y[15] D[16]=$procmux$613_Y[16] D[17]=$procmux$613_Y[17] D[18]=$procmux$613_Y[18] D[19]=$procmux$613_Y[19] D[20]=$procmux$613_Y[20] D[21]=$procmux$613_Y[21] D[22]=$procmux$613_Y[22] D[23]=$procmux$613_Y[23] D[24]=$procmux$613_Y[24] D[25]=$procmux$613_Y[25] D[26]=$procmux$613_Y[26] D[27]=$procmux$613_Y[27] D[28]=$procmux$613_Y[28] D[29]=$procmux$613_Y[29] D[30]=$procmux$613_Y[30] D[31]=$procmux$613_Y[31] Q[0]=W10[0] Q[1]=W10[1] Q[2]=W10[2] Q[3]=W10[3] Q[4]=W10[4] Q[5]=W10[5] Q[6]=W10[6] Q[7]=W10[7] Q[8]=W10[8] Q[9]=W10[9] Q[10]=W10[10] Q[11]=W10[11] Q[12]=W10[12] Q[13]=W10[13] Q[14]=W10[14] Q[15]=W10[15] Q[16]=W10[16] Q[17]=W10[17] Q[18]=W10[18] Q[19]=W10[19] Q[20]=W10[20] Q[21]=W10[21] Q[22]=W10[22] Q[23]=W10[23] Q[24]=W10[24] Q[25]=W10[25] Q[26]=W10[26] Q[27]=W10[27] Q[28]=W10[28] Q[29]=W10[29] Q[30]=W10[30] Q[31]=W10[31]
|
||
|
|
.cname $procdff$2382
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:148"
|
||
|
|
.param CLK_POLARITY 1
|
||
|
|
.param WIDTH 00000000000000000000000000100000
|
||
|
|
.subckt $dff CLK=clk_i D[0]=$procmux$542_Y[0] D[1]=$procmux$542_Y[1] D[2]=$procmux$542_Y[2] D[3]=$procmux$542_Y[3] D[4]=$procmux$542_Y[4] D[5]=$procmux$542_Y[5] D[6]=$procmux$542_Y[6] D[7]=$procmux$542_Y[7] D[8]=$procmux$542_Y[8] D[9]=$procmux$542_Y[9] D[10]=$procmux$542_Y[10] D[11]=$procmux$542_Y[11] D[12]=$procmux$542_Y[12] D[13]=$procmux$542_Y[13] D[14]=$procmux$542_Y[14] D[15]=$procmux$542_Y[15] D[16]=$procmux$542_Y[16] D[17]=$procmux$542_Y[17] D[18]=$procmux$542_Y[18] D[19]=$procmux$542_Y[19] D[20]=$procmux$542_Y[20] D[21]=$procmux$542_Y[21] D[22]=$procmux$542_Y[22] D[23]=$procmux$542_Y[23] D[24]=$procmux$542_Y[24] D[25]=$procmux$542_Y[25] D[26]=$procmux$542_Y[26] D[27]=$procmux$542_Y[27] D[28]=$procmux$542_Y[28] D[29]=$procmux$542_Y[29] D[30]=$procmux$542_Y[30] D[31]=$procmux$542_Y[31] Q[0]=W11[0] Q[1]=W11[1] Q[2]=W11[2] Q[3]=W11[3] Q[4]=W11[4] Q[5]=W11[5] Q[6]=W11[6] Q[7]=W11[7] Q[8]=W11[8] Q[9]=W11[9] Q[10]=W11[10] Q[11]=W11[11] Q[12]=W11[12] Q[13]=W11[13] Q[14]=W11[14] Q[15]=W11[15] Q[16]=W11[16] Q[17]=W11[17] Q[18]=W11[18] Q[19]=W11[19] Q[20]=W11[20] Q[21]=W11[21] Q[22]=W11[22] Q[23]=W11[23] Q[24]=W11[24] Q[25]=W11[25] Q[26]=W11[26] Q[27]=W11[27] Q[28]=W11[28] Q[29]=W11[29] Q[30]=W11[30] Q[31]=W11[31]
|
||
|
|
.cname $procdff$2383
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:148"
|
||
|
|
.param CLK_POLARITY 1
|
||
|
|
.param WIDTH 00000000000000000000000000100000
|
||
|
|
.subckt $dff CLK=clk_i D[0]=$procmux$471_Y[0] D[1]=$procmux$471_Y[1] D[2]=$procmux$471_Y[2] D[3]=$procmux$471_Y[3] D[4]=$procmux$471_Y[4] D[5]=$procmux$471_Y[5] D[6]=$procmux$471_Y[6] D[7]=$procmux$471_Y[7] D[8]=$procmux$471_Y[8] D[9]=$procmux$471_Y[9] D[10]=$procmux$471_Y[10] D[11]=$procmux$471_Y[11] D[12]=$procmux$471_Y[12] D[13]=$procmux$471_Y[13] D[14]=$procmux$471_Y[14] D[15]=$procmux$471_Y[15] D[16]=$procmux$471_Y[16] D[17]=$procmux$471_Y[17] D[18]=$procmux$471_Y[18] D[19]=$procmux$471_Y[19] D[20]=$procmux$471_Y[20] D[21]=$procmux$471_Y[21] D[22]=$procmux$471_Y[22] D[23]=$procmux$471_Y[23] D[24]=$procmux$471_Y[24] D[25]=$procmux$471_Y[25] D[26]=$procmux$471_Y[26] D[27]=$procmux$471_Y[27] D[28]=$procmux$471_Y[28] D[29]=$procmux$471_Y[29] D[30]=$procmux$471_Y[30] D[31]=$procmux$471_Y[31] Q[0]=W12[0] Q[1]=W12[1] Q[2]=W12[2] Q[3]=W12[3] Q[4]=W12[4] Q[5]=W12[5] Q[6]=W12[6] Q[7]=W12[7] Q[8]=W12[8] Q[9]=W12[9] Q[10]=W12[10] Q[11]=W12[11] Q[12]=W12[12] Q[13]=W12[13] Q[14]=W12[14] Q[15]=W12[15] Q[16]=W12[16] Q[17]=W12[17] Q[18]=W12[18] Q[19]=W12[19] Q[20]=W12[20] Q[21]=W12[21] Q[22]=W12[22] Q[23]=W12[23] Q[24]=W12[24] Q[25]=W12[25] Q[26]=W12[26] Q[27]=W12[27] Q[28]=W12[28] Q[29]=W12[29] Q[30]=W12[30] Q[31]=W12[31]
|
||
|
|
.cname $procdff$2384
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:148"
|
||
|
|
.param CLK_POLARITY 1
|
||
|
|
.param WIDTH 00000000000000000000000000100000
|
||
|
|
.subckt $dff CLK=clk_i D[0]=$procmux$400_Y[0] D[1]=$procmux$400_Y[1] D[2]=$procmux$400_Y[2] D[3]=$procmux$400_Y[3] D[4]=$procmux$400_Y[4] D[5]=$procmux$400_Y[5] D[6]=$procmux$400_Y[6] D[7]=$procmux$400_Y[7] D[8]=$procmux$400_Y[8] D[9]=$procmux$400_Y[9] D[10]=$procmux$400_Y[10] D[11]=$procmux$400_Y[11] D[12]=$procmux$400_Y[12] D[13]=$procmux$400_Y[13] D[14]=$procmux$400_Y[14] D[15]=$procmux$400_Y[15] D[16]=$procmux$400_Y[16] D[17]=$procmux$400_Y[17] D[18]=$procmux$400_Y[18] D[19]=$procmux$400_Y[19] D[20]=$procmux$400_Y[20] D[21]=$procmux$400_Y[21] D[22]=$procmux$400_Y[22] D[23]=$procmux$400_Y[23] D[24]=$procmux$400_Y[24] D[25]=$procmux$400_Y[25] D[26]=$procmux$400_Y[26] D[27]=$procmux$400_Y[27] D[28]=$procmux$400_Y[28] D[29]=$procmux$400_Y[29] D[30]=$procmux$400_Y[30] D[31]=$procmux$400_Y[31] Q[0]=W13[0] Q[1]=W13[1] Q[2]=W13[2] Q[3]=W13[3] Q[4]=W13[4] Q[5]=W13[5] Q[6]=W13[6] Q[7]=W13[7] Q[8]=W13[8] Q[9]=W13[9] Q[10]=W13[10] Q[11]=W13[11] Q[12]=W13[12] Q[13]=W13[13] Q[14]=W13[14] Q[15]=W13[15] Q[16]=W13[16] Q[17]=W13[17] Q[18]=W13[18] Q[19]=W13[19] Q[20]=W13[20] Q[21]=W13[21] Q[22]=W13[22] Q[23]=W13[23] Q[24]=W13[24] Q[25]=W13[25] Q[26]=W13[26] Q[27]=W13[27] Q[28]=W13[28] Q[29]=W13[29] Q[30]=W13[30] Q[31]=W13[31]
|
||
|
|
.cname $procdff$2385
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:148"
|
||
|
|
.param CLK_POLARITY 1
|
||
|
|
.param WIDTH 00000000000000000000000000100000
|
||
|
|
.subckt $dff CLK=clk_i D[0]=$procmux$329_Y[0] D[1]=$procmux$329_Y[1] D[2]=$procmux$329_Y[2] D[3]=$procmux$329_Y[3] D[4]=$procmux$329_Y[4] D[5]=$procmux$329_Y[5] D[6]=$procmux$329_Y[6] D[7]=$procmux$329_Y[7] D[8]=$procmux$329_Y[8] D[9]=$procmux$329_Y[9] D[10]=$procmux$329_Y[10] D[11]=$procmux$329_Y[11] D[12]=$procmux$329_Y[12] D[13]=$procmux$329_Y[13] D[14]=$procmux$329_Y[14] D[15]=$procmux$329_Y[15] D[16]=$procmux$329_Y[16] D[17]=$procmux$329_Y[17] D[18]=$procmux$329_Y[18] D[19]=$procmux$329_Y[19] D[20]=$procmux$329_Y[20] D[21]=$procmux$329_Y[21] D[22]=$procmux$329_Y[22] D[23]=$procmux$329_Y[23] D[24]=$procmux$329_Y[24] D[25]=$procmux$329_Y[25] D[26]=$procmux$329_Y[26] D[27]=$procmux$329_Y[27] D[28]=$procmux$329_Y[28] D[29]=$procmux$329_Y[29] D[30]=$procmux$329_Y[30] D[31]=$procmux$329_Y[31] Q[0]=W14[0] Q[1]=W14[1] Q[2]=W14[2] Q[3]=W14[3] Q[4]=W14[4] Q[5]=W14[5] Q[6]=W14[6] Q[7]=W14[7] Q[8]=W14[8] Q[9]=W14[9] Q[10]=W14[10] Q[11]=W14[11] Q[12]=W14[12] Q[13]=W14[13] Q[14]=W14[14] Q[15]=W14[15] Q[16]=W14[16] Q[17]=W14[17] Q[18]=W14[18] Q[19]=W14[19] Q[20]=W14[20] Q[21]=W14[21] Q[22]=W14[22] Q[23]=W14[23] Q[24]=W14[24] Q[25]=W14[25] Q[26]=W14[26] Q[27]=W14[27] Q[28]=W14[28] Q[29]=W14[29] Q[30]=W14[30] Q[31]=W14[31]
|
||
|
|
.cname $procdff$2386
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:148"
|
||
|
|
.param CLK_POLARITY 1
|
||
|
|
.param WIDTH 00000000000000000000000000100000
|
||
|
|
.subckt $dff CLK=clk_i D[0]=$procmux$258_Y[0] D[1]=$procmux$258_Y[1] D[2]=$procmux$258_Y[2] D[3]=$procmux$258_Y[3] D[4]=$procmux$258_Y[4] D[5]=$procmux$258_Y[5] D[6]=$procmux$258_Y[6] D[7]=$procmux$258_Y[7] D[8]=$procmux$258_Y[8] D[9]=$procmux$258_Y[9] D[10]=$procmux$258_Y[10] D[11]=$procmux$258_Y[11] D[12]=$procmux$258_Y[12] D[13]=$procmux$258_Y[13] D[14]=$procmux$258_Y[14] D[15]=$procmux$258_Y[15] D[16]=$procmux$258_Y[16] D[17]=$procmux$258_Y[17] D[18]=$procmux$258_Y[18] D[19]=$procmux$258_Y[19] D[20]=$procmux$258_Y[20] D[21]=$procmux$258_Y[21] D[22]=$procmux$258_Y[22] D[23]=$procmux$258_Y[23] D[24]=$procmux$258_Y[24] D[25]=$procmux$258_Y[25] D[26]=$procmux$258_Y[26] D[27]=$procmux$258_Y[27] D[28]=$procmux$258_Y[28] D[29]=$procmux$258_Y[29] D[30]=$procmux$258_Y[30] D[31]=$procmux$258_Y[31] Q[0]=Wt[0] Q[1]=Wt[1] Q[2]=Wt[2] Q[3]=Wt[3] Q[4]=Wt[4] Q[5]=Wt[5] Q[6]=Wt[6] Q[7]=Wt[7] Q[8]=Wt[8] Q[9]=Wt[9] Q[10]=Wt[10] Q[11]=Wt[11] Q[12]=Wt[12] Q[13]=Wt[13] Q[14]=Wt[14] Q[15]=Wt[15] Q[16]=Wt[16] Q[17]=Wt[17] Q[18]=Wt[18] Q[19]=Wt[19] Q[20]=Wt[20] Q[21]=Wt[21] Q[22]=Wt[22] Q[23]=Wt[23] Q[24]=Wt[24] Q[25]=Wt[25] Q[26]=Wt[26] Q[27]=Wt[27] Q[28]=Wt[28] Q[29]=Wt[29] Q[30]=Wt[30] Q[31]=Wt[31]
|
||
|
|
.cname $procdff$2387
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:148"
|
||
|
|
.param CLK_POLARITY 1
|
||
|
|
.param WIDTH 00000000000000000000000000100000
|
||
|
|
.subckt $dff CLK=clk_i D=$procmux$169_Y Q=busy
|
||
|
|
.cname $procdff$2388
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:148"
|
||
|
|
.param CLK_POLARITY 1
|
||
|
|
.param WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $dff CLK=clk_i D[0]=$procmux$2350_Y[0] D[1]=$procmux$2350_Y[1] D[2]=$procmux$2341_Y D[3]=$procmux$2356_Y Q[0]=cmd[0] Q[1]=cmd[1] Q[2]=cmd[2] Q[3]=cmd[3]
|
||
|
|
.cname $procdff$2389
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:106"
|
||
|
|
.param CLK_POLARITY 1
|
||
|
|
.param WIDTH 00000000000000000000000000000100
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$false B[1]=$false B[2]=$true B[3]=$false B[4]=$true B[5]=$true B[6]=$false Y=$procmux$1000_CMP
|
||
|
|
.cname $procmux$1000_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$true B[1]=$true B[2]=$false B[3]=$false B[4]=$true B[5]=$true B[6]=$false Y=$procmux$1001_CMP
|
||
|
|
.cname $procmux$1001_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$false B[1]=$true B[2]=$false B[3]=$false B[4]=$true B[5]=$true B[6]=$false Y=$procmux$1002_CMP
|
||
|
|
.cname $procmux$1002_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$true B[1]=$false B[2]=$false B[3]=$false B[4]=$true B[5]=$true B[6]=$false Y=$procmux$1003_CMP
|
||
|
|
.cname $procmux$1003_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$false B[1]=$false B[2]=$false B[3]=$false B[4]=$true B[5]=$true B[6]=$false Y=$procmux$1004_CMP
|
||
|
|
.cname $procmux$1004_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$true B[1]=$true B[2]=$true B[3]=$true B[4]=$false B[5]=$true B[6]=$false Y=$procmux$1005_CMP
|
||
|
|
.cname $procmux$1005_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$false B[1]=$true B[2]=$true B[3]=$true B[4]=$false B[5]=$true B[6]=$false Y=$procmux$1006_CMP
|
||
|
|
.cname $procmux$1006_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$true B[1]=$false B[2]=$true B[3]=$true B[4]=$false B[5]=$true B[6]=$false Y=$procmux$1007_CMP
|
||
|
|
.cname $procmux$1007_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$false B[1]=$false B[2]=$true B[3]=$true B[4]=$false B[5]=$true B[6]=$false Y=$procmux$1008_CMP
|
||
|
|
.cname $procmux$1008_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$true B[1]=$true B[2]=$false B[3]=$true B[4]=$false B[5]=$true B[6]=$false Y=$procmux$1009_CMP
|
||
|
|
.cname $procmux$1009_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$false B[1]=$false B[2]=$false B[3]=$false B[4]=$false B[5]=$false B[6]=$true Y=$procmux$100_CMP
|
||
|
|
.cname $procmux$100_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$false B[1]=$true B[2]=$false B[3]=$true B[4]=$false B[5]=$true B[6]=$false Y=$procmux$1010_CMP
|
||
|
|
.cname $procmux$1010_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$true B[1]=$false B[2]=$false B[3]=$true B[4]=$false B[5]=$true B[6]=$false Y=$procmux$1011_CMP
|
||
|
|
.cname $procmux$1011_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$false B[1]=$false B[2]=$false B[3]=$true B[4]=$false B[5]=$true B[6]=$false Y=$procmux$1012_CMP
|
||
|
|
.cname $procmux$1012_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$true B[1]=$true B[2]=$true B[3]=$false B[4]=$false B[5]=$true B[6]=$false Y=$procmux$1013_CMP
|
||
|
|
.cname $procmux$1013_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$false B[1]=$true B[2]=$true B[3]=$false B[4]=$false B[5]=$true B[6]=$false Y=$procmux$1014_CMP
|
||
|
|
.cname $procmux$1014_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$true B[1]=$false B[2]=$true B[3]=$false B[4]=$false B[5]=$true B[6]=$false Y=$procmux$1015_CMP
|
||
|
|
.cname $procmux$1015_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$false B[1]=$false B[2]=$true B[3]=$false B[4]=$false B[5]=$true B[6]=$false Y=$procmux$1016_CMP
|
||
|
|
.cname $procmux$1016_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$true B[1]=$true B[2]=$false B[3]=$false B[4]=$false B[5]=$true B[6]=$false Y=$procmux$1017_CMP
|
||
|
|
.cname $procmux$1017_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$false B[1]=$true B[2]=$false B[3]=$false B[4]=$false B[5]=$true B[6]=$false Y=$procmux$1018_CMP
|
||
|
|
.cname $procmux$1018_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$true B[1]=$false B[2]=$false B[3]=$false B[4]=$false B[5]=$true B[6]=$false Y=$procmux$1019_CMP
|
||
|
|
.cname $procmux$1019_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$true B[1]=$true B[2]=$true B[3]=$true B[4]=$true B[5]=$true B[6]=$false Y=$procmux$101_CMP
|
||
|
|
.cname $procmux$101_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$false B[1]=$false B[2]=$false B[3]=$false B[4]=$false B[5]=$true B[6]=$false Y=$procmux$1020_CMP
|
||
|
|
.cname $procmux$1020_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$true B[1]=$true B[2]=$true B[3]=$true B[4]=$true B[5]=$false B[6]=$false Y=$procmux$1021_CMP
|
||
|
|
.cname $procmux$1021_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$false B[1]=$true B[2]=$true B[3]=$true B[4]=$true B[5]=$false B[6]=$false Y=$procmux$1022_CMP
|
||
|
|
.cname $procmux$1022_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$true B[1]=$false B[2]=$true B[3]=$true B[4]=$true B[5]=$false B[6]=$false Y=$procmux$1023_CMP
|
||
|
|
.cname $procmux$1023_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$false B[1]=$false B[2]=$true B[3]=$true B[4]=$true B[5]=$false B[6]=$false Y=$procmux$1024_CMP
|
||
|
|
.cname $procmux$1024_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$true B[1]=$true B[2]=$false B[3]=$true B[4]=$true B[5]=$false B[6]=$false Y=$procmux$1025_CMP
|
||
|
|
.cname $procmux$1025_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$false B[1]=$true B[2]=$false B[3]=$true B[4]=$true B[5]=$false B[6]=$false Y=$procmux$1026_CMP
|
||
|
|
.cname $procmux$1026_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$true B[1]=$false B[2]=$false B[3]=$true B[4]=$true B[5]=$false B[6]=$false Y=$procmux$1027_CMP
|
||
|
|
.cname $procmux$1027_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$false B[1]=$false B[2]=$false B[3]=$true B[4]=$true B[5]=$false B[6]=$false Y=$procmux$1028_CMP
|
||
|
|
.cname $procmux$1028_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$true B[1]=$true B[2]=$true B[3]=$false B[4]=$true B[5]=$false B[6]=$false Y=$procmux$1029_CMP
|
||
|
|
.cname $procmux$1029_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$false B[1]=$true B[2]=$true B[3]=$true B[4]=$true B[5]=$true B[6]=$false Y=$procmux$102_CMP
|
||
|
|
.cname $procmux$102_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$false B[1]=$true B[2]=$true B[3]=$false B[4]=$true B[5]=$false B[6]=$false Y=$procmux$1030_CMP
|
||
|
|
.cname $procmux$1030_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$true B[1]=$false B[2]=$true B[3]=$false B[4]=$true B[5]=$false B[6]=$false Y=$procmux$1031_CMP
|
||
|
|
.cname $procmux$1031_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$false B[1]=$false B[2]=$true B[3]=$false B[4]=$true B[5]=$false B[6]=$false Y=$procmux$1032_CMP
|
||
|
|
.cname $procmux$1032_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$true B[1]=$true B[2]=$false B[3]=$false B[4]=$true B[5]=$false B[6]=$false Y=$procmux$1033_CMP
|
||
|
|
.cname $procmux$1033_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$false B[1]=$true B[2]=$false B[3]=$false B[4]=$true B[5]=$false B[6]=$false Y=$procmux$1034_CMP
|
||
|
|
.cname $procmux$1034_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$true B[1]=$false B[2]=$false B[3]=$false B[4]=$true B[5]=$false B[6]=$false Y=$procmux$1035_CMP
|
||
|
|
.cname $procmux$1035_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$false B[1]=$false B[2]=$false B[3]=$false B[4]=$true B[5]=$false B[6]=$false Y=$procmux$1036_CMP
|
||
|
|
.cname $procmux$1036_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$false B[1]=$false B[2]=$true B[3]=$false B[4]=$false B[5]=$false B[6]=$false Y=$procmux$1037_CMP
|
||
|
|
.cname $procmux$1037_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $mux A[0]=$procmux$972_Y[0] A[1]=$procmux$972_Y[1] A[2]=$procmux$972_Y[2] A[3]=$procmux$972_Y[3] A[4]=$procmux$972_Y[4] A[5]=$procmux$972_Y[5] A[6]=$procmux$972_Y[6] A[7]=$procmux$972_Y[7] A[8]=$procmux$972_Y[8] A[9]=$procmux$972_Y[9] A[10]=$procmux$972_Y[10] A[11]=$procmux$972_Y[11] A[12]=$procmux$972_Y[12] A[13]=$procmux$972_Y[13] A[14]=$procmux$972_Y[14] A[15]=$procmux$972_Y[15] A[16]=$procmux$972_Y[16] A[17]=$procmux$972_Y[17] A[18]=$procmux$972_Y[18] A[19]=$procmux$972_Y[19] A[20]=$procmux$972_Y[20] A[21]=$procmux$972_Y[21] A[22]=$procmux$972_Y[22] A[23]=$procmux$972_Y[23] A[24]=$procmux$972_Y[24] A[25]=$procmux$972_Y[25] A[26]=$procmux$972_Y[26] A[27]=$procmux$972_Y[27] A[28]=$procmux$972_Y[28] A[29]=$procmux$972_Y[29] A[30]=$procmux$972_Y[30] A[31]=$procmux$972_Y[31] B[0]=$false B[1]=$false B[2]=$false B[3]=$false B[4]=$false B[5]=$false B[6]=$false B[7]=$false B[8]=$false B[9]=$false B[10]=$false B[11]=$false B[12]=$false B[13]=$false B[14]=$false B[15]=$false B[16]=$false B[17]=$false B[18]=$false B[19]=$false B[20]=$false B[21]=$false B[22]=$false B[23]=$false B[24]=$false B[25]=$false B[26]=$false B[27]=$false B[28]=$false B[29]=$false B[30]=$false B[31]=$false S=$procmux$1040_CMP Y[0]=$procmux$1039_Y[0] Y[1]=$procmux$1039_Y[1] Y[2]=$procmux$1039_Y[2] Y[3]=$procmux$1039_Y[3] Y[4]=$procmux$1039_Y[4] Y[5]=$procmux$1039_Y[5] Y[6]=$procmux$1039_Y[6] Y[7]=$procmux$1039_Y[7] Y[8]=$procmux$1039_Y[8] Y[9]=$procmux$1039_Y[9] Y[10]=$procmux$1039_Y[10] Y[11]=$procmux$1039_Y[11] Y[12]=$procmux$1039_Y[12] Y[13]=$procmux$1039_Y[13] Y[14]=$procmux$1039_Y[14] Y[15]=$procmux$1039_Y[15] Y[16]=$procmux$1039_Y[16] Y[17]=$procmux$1039_Y[17] Y[18]=$procmux$1039_Y[18] Y[19]=$procmux$1039_Y[19] Y[20]=$procmux$1039_Y[20] Y[21]=$procmux$1039_Y[21] Y[22]=$procmux$1039_Y[22] Y[23]=$procmux$1039_Y[23] Y[24]=$procmux$1039_Y[24] Y[25]=$procmux$1039_Y[25] Y[26]=$procmux$1039_Y[26] Y[27]=$procmux$1039_Y[27] Y[28]=$procmux$1039_Y[28] Y[29]=$procmux$1039_Y[29] Y[30]=$procmux$1039_Y[30] Y[31]=$procmux$1039_Y[31]
|
||
|
|
.cname $procmux$1039
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:150"
|
||
|
|
.param WIDTH 00000000000000000000000000100000
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$true B[1]=$false B[2]=$true B[3]=$true B[4]=$true B[5]=$true B[6]=$false Y=$procmux$103_CMP
|
||
|
|
.cname $procmux$103_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $pmux A[0]=W3[0] A[1]=W3[1] A[2]=W3[2] A[3]=W3[3] A[4]=W3[4] A[5]=W3[5] A[6]=W3[6] A[7]=W3[7] A[8]=W3[8] A[9]=W3[9] A[10]=W3[10] A[11]=W3[11] A[12]=W3[12] A[13]=W3[13] A[14]=W3[14] A[15]=W3[15] A[16]=W3[16] A[17]=W3[17] A[18]=W3[18] A[19]=W3[19] A[20]=W3[20] A[21]=W3[21] A[22]=W3[22] A[23]=W3[23] A[24]=W3[24] A[25]=W3[25] A[26]=W3[26] A[27]=W3[27] A[28]=W3[28] A[29]=W3[29] A[30]=W3[30] A[31]=W3[31] B[0]=W4[0] B[1]=W4[1] B[2]=W4[2] B[3]=W4[3] B[4]=W4[4] B[5]=W4[5] B[6]=W4[6] B[7]=W4[7] B[8]=W4[8] B[9]=W4[9] B[10]=W4[10] B[11]=W4[11] B[12]=W4[12] B[13]=W4[13] B[14]=W4[14] B[15]=W4[15] B[16]=W4[16] B[17]=W4[17] B[18]=W4[18] B[19]=W4[19] B[20]=W4[20] B[21]=W4[21] B[22]=W4[22] B[23]=W4[23] B[24]=W4[24] B[25]=W4[25] B[26]=W4[26] B[27]=W4[27] B[28]=W4[28] B[29]=W4[29] B[30]=W4[30] B[31]=W4[31] B[32]=W4[0] B[33]=W4[1] B[34]=W4[2] B[35]=W4[3] B[36]=W4[4] B[37]=W4[5] B[38]=W4[6] B[39]=W4[7] B[40]=W4[8] B[41]=W4[9] B[42]=W4[10] B[43]=W4[11] B[44]=W4[12] B[45]=W4[13] B[46]=W4[14] B[47]=W4[15] B[48]=W4[16] B[49]=W4[17] B[50]=W4[18] B[51]=W4[19] B[52]=W4[20] B[53]=W4[21] B[54]=W4[22] B[55]=W4[23] B[56]=W4[24] B[57]=W4[25] B[58]=W4[26] B[59]=W4[27] B[60]=W4[28] B[61]=W4[29] B[62]=W4[30] B[63]=W4[31] B[64]=W4[0] B[65]=W4[1] B[66]=W4[2] B[67]=W4[3] B[68]=W4[4] B[69]=W4[5] B[70]=W4[6] B[71]=W4[7] B[72]=W4[8] B[73]=W4[9] B[74]=W4[10] B[75]=W4[11] B[76]=W4[12] B[77]=W4[13] B[78]=W4[14] B[79]=W4[15] B[80]=W4[16] B[81]=W4[17] B[82]=W4[18] B[83]=W4[19] B[84]=W4[20] B[85]=W4[21] B[86]=W4[22] B[87]=W4[23] B[88]=W4[24] B[89]=W4[25] B[90]=W4[26] B[91]=W4[27] B[92]=W4[28] B[93]=W4[29] B[94]=W4[30] B[95]=W4[31] B[96]=W4[0] B[97]=W4[1] B[98]=W4[2] B[99]=W4[3] B[100]=W4[4] B[101]=W4[5] B[102]=W4[6] B[103]=W4[7] B[104]=W4[8] B[105]=W4[9] B[106]=W4[10] B[107]=W4[11] B[108]=W4[12] B[109]=W4[13] B[110]=W4[14] B[111]=W4[15] B[112]=W4[16] B[113]=W4[17] B[114]=W4[18] B[115]=W4[19] B[116]=W4[20] B[117]=W4[21] B[118]=W4[22] B[119]=W4[23] B[120]=W4[24] B[121]=W4[25] B[122]=W4[26] B[123]=W4[27] B[124]=W4[28] B[125]=W4[29] B[126]=W4[30] B[127]=W4[31] B[128]=W4[0] B[129]=W4[1] B[130]=W4[2] B[131]=W4[3] B[132]=W4[4] B[133]=W4[5] B[134]=W4[6] B[135]=W4[7] B[136]=W4[8] B[137]=W4[9] B[138]=W4[10] B[139]=W4[11] B[140]=W4[12] B[141]=W4[13] B[142]=W4[14] B[143]=W4[15] B[144]=W4[16] B[145]=W4[17] B[146]=W4[18] B[147]=W4[19] B[148]=W4[20] B[149]=W4[21] B[150]=W4[22] B[151]=W4[23] B[152]=W4[24] B[153]=W4[25] B[154]=W4[26] B[155]=W4[27] B[156]=W4[28] B[157]=W4[29] B[158]=W4[30] B[159]=W4[31] B[160]=W4[0] B[161]=W4[1] B[162]=W4[2] B[163]=W4[3] B[164]=W4[4] B[165]=W4[5] B[166]=W4[6] B[167]=W4[7] B[168]=W4[8] B[169]=W4[9] B[170]=W4[10] B[171]=W4[11] B[172]=W4[12] B[173]=W4[13] B[174]=W4[14] B[175]=W4[15] B[176]=W4[16] B[177]=W4[17] B[178]=W4[18] B[179]=W4[19] B[180]=W4[20] B[181]=W4[21] B[182]=W4[22] B[183]=W4[23] B[184]=W4[24] B[185]=W4[25] B[186]=W4[26] B[187]=W4[27] B[188]=W4[28] B[189]=W4[29] B[190]=W4[30] B[191]=W4[31] B[192]=W4[0] B[193]=W4[1] B[194]=W4[2] B[195]=W4[3] B[196]=W4[4] B[197]=W4[5] B[198]=W4[6] B[199]=W4[7] B[200]=W4[8] B[201]=W4[9] B[202]=W4[10] B[203]=W4[11] B[204]=W4[12] B[205]=W4[13] B[206]=W4[14] B[207]=W4[15] B[208]=W4[16] B[209]=W4[17] B[210]=W4[18] B[211]=W4[19] B[212]=W4[20] B[213]=W4[21] B[214]=W4[22] B[215]=W4[23] B[216]=W4[24] B[217]=W4[25] B[218]=W4[26] B[219]=W4[27] B[220]=W4[28] B[221]=W4[29] B[222]=W4[30] B[223]=W4[31] B[224]=W4[0] B[225]=W4[1] B[226]=W4[2] B[227]=W4[3] B[228]=W4[4] B[229]=W4[5] B[230]=W4[6] B[231]=W4[7] B[232]=W4[8] B[233]=W4[9] B[234]=W4[10] B[235]=W4[11] B[236]=W4[12] B[237]=W4[13] B[238]=W4[14] B[239]=W4[15] B[240]=W4[16] B[241]=W4[17] B[242]=W4[18] B[243]=W4[19] B[244]=W4[20] B[245]=W4[21] B[246]=W4[22] B[247]=W4[23] B[248]=W4[24] B[249]=W4[25] B[250]=W4[26] B[251]=W4[27] B[252]=W4[28] B[253]=W4[29] B[254]=W4[30] B[255]=W4[31] B[256]=W4[0] B[257]=W4[1] B[258]=W4[2] B[259]=W4[3] B[260]=W4[4] B[261]=W4[5] B[262]=W4[6] B[263]=W4[7] B[264]=W4[8] B[265]=W4[9] B[266]=W4[10] B[267]=W4[11] B[268]=W4[12] B[269]=W4[13] B[270]=W4[14] B[271]=W4[15] B[272]=W4[16] B[273]=W4[17] B[274]=W4[18] B[275]=W4[19] B[276]=W4[20] B[277]=
|
||
|
|
.cname $procmux$1043
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param S_WIDTH 00000000000000000000000001000001
|
||
|
|
.param WIDTH 00000000000000000000000000100000
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$true B[1]=$true B[2]=$true B[3]=$true B[4]=$false B[5]=$false B[6]=$true Y=$procmux$1044_CMP
|
||
|
|
.cname $procmux$1044_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$false B[1]=$true B[2]=$true B[3]=$true B[4]=$false B[5]=$false B[6]=$true Y=$procmux$1045_CMP
|
||
|
|
.cname $procmux$1045_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$true B[1]=$false B[2]=$true B[3]=$true B[4]=$false B[5]=$false B[6]=$true Y=$procmux$1046_CMP
|
||
|
|
.cname $procmux$1046_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$false B[1]=$false B[2]=$true B[3]=$true B[4]=$false B[5]=$false B[6]=$true Y=$procmux$1047_CMP
|
||
|
|
.cname $procmux$1047_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$true B[1]=$true B[2]=$false B[3]=$true B[4]=$false B[5]=$false B[6]=$true Y=$procmux$1048_CMP
|
||
|
|
.cname $procmux$1048_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$false B[1]=$true B[2]=$false B[3]=$true B[4]=$false B[5]=$false B[6]=$true Y=$procmux$1049_CMP
|
||
|
|
.cname $procmux$1049_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$false B[1]=$false B[2]=$true B[3]=$true B[4]=$true B[5]=$true B[6]=$false Y=$procmux$104_CMP
|
||
|
|
.cname $procmux$104_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$true B[1]=$false B[2]=$false B[3]=$true B[4]=$false B[5]=$false B[6]=$true Y=$procmux$1050_CMP
|
||
|
|
.cname $procmux$1050_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$false B[1]=$false B[2]=$false B[3]=$true B[4]=$false B[5]=$false B[6]=$true Y=$procmux$1051_CMP
|
||
|
|
.cname $procmux$1051_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$true B[1]=$true B[2]=$true B[3]=$false B[4]=$false B[5]=$false B[6]=$true Y=$procmux$1052_CMP
|
||
|
|
.cname $procmux$1052_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$false B[1]=$true B[2]=$true B[3]=$false B[4]=$false B[5]=$false B[6]=$true Y=$procmux$1053_CMP
|
||
|
|
.cname $procmux$1053_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$true B[1]=$false B[2]=$true B[3]=$false B[4]=$false B[5]=$false B[6]=$true Y=$procmux$1054_CMP
|
||
|
|
.cname $procmux$1054_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$false B[1]=$false B[2]=$true B[3]=$false B[4]=$false B[5]=$false B[6]=$true Y=$procmux$1055_CMP
|
||
|
|
.cname $procmux$1055_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$true B[1]=$true B[2]=$false B[3]=$false B[4]=$false B[5]=$false B[6]=$true Y=$procmux$1056_CMP
|
||
|
|
.cname $procmux$1056_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$false B[1]=$true B[2]=$false B[3]=$false B[4]=$false B[5]=$false B[6]=$true Y=$procmux$1057_CMP
|
||
|
|
.cname $procmux$1057_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$true B[1]=$false B[2]=$false B[3]=$false B[4]=$false B[5]=$false B[6]=$true Y=$procmux$1058_CMP
|
||
|
|
.cname $procmux$1058_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$false B[1]=$false B[2]=$false B[3]=$false B[4]=$false B[5]=$false B[6]=$true Y=$procmux$1059_CMP
|
||
|
|
.cname $procmux$1059_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$true B[1]=$true B[2]=$false B[3]=$true B[4]=$true B[5]=$true B[6]=$false Y=$procmux$105_CMP
|
||
|
|
.cname $procmux$105_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$true B[1]=$true B[2]=$true B[3]=$true B[4]=$true B[5]=$true B[6]=$false Y=$procmux$1060_CMP
|
||
|
|
.cname $procmux$1060_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$false B[1]=$true B[2]=$true B[3]=$true B[4]=$true B[5]=$true B[6]=$false Y=$procmux$1061_CMP
|
||
|
|
.cname $procmux$1061_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$true B[1]=$false B[2]=$true B[3]=$true B[4]=$true B[5]=$true B[6]=$false Y=$procmux$1062_CMP
|
||
|
|
.cname $procmux$1062_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$false B[1]=$false B[2]=$true B[3]=$true B[4]=$true B[5]=$true B[6]=$false Y=$procmux$1063_CMP
|
||
|
|
.cname $procmux$1063_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$true B[1]=$true B[2]=$false B[3]=$true B[4]=$true B[5]=$true B[6]=$false Y=$procmux$1064_CMP
|
||
|
|
.cname $procmux$1064_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$false B[1]=$true B[2]=$false B[3]=$true B[4]=$true B[5]=$true B[6]=$false Y=$procmux$1065_CMP
|
||
|
|
.cname $procmux$1065_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$true B[1]=$false B[2]=$false B[3]=$true B[4]=$true B[5]=$true B[6]=$false Y=$procmux$1066_CMP
|
||
|
|
.cname $procmux$1066_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$false B[1]=$false B[2]=$false B[3]=$true B[4]=$true B[5]=$true B[6]=$false Y=$procmux$1067_CMP
|
||
|
|
.cname $procmux$1067_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$true B[1]=$true B[2]=$true B[3]=$false B[4]=$true B[5]=$true B[6]=$false Y=$procmux$1068_CMP
|
||
|
|
.cname $procmux$1068_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$false B[1]=$true B[2]=$true B[3]=$false B[4]=$true B[5]=$true B[6]=$false Y=$procmux$1069_CMP
|
||
|
|
.cname $procmux$1069_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$false B[1]=$true B[2]=$false B[3]=$true B[4]=$true B[5]=$true B[6]=$false Y=$procmux$106_CMP
|
||
|
|
.cname $procmux$106_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$true B[1]=$false B[2]=$true B[3]=$false B[4]=$true B[5]=$true B[6]=$false Y=$procmux$1070_CMP
|
||
|
|
.cname $procmux$1070_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$false B[1]=$false B[2]=$true B[3]=$false B[4]=$true B[5]=$true B[6]=$false Y=$procmux$1071_CMP
|
||
|
|
.cname $procmux$1071_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$true B[1]=$true B[2]=$false B[3]=$false B[4]=$true B[5]=$true B[6]=$false Y=$procmux$1072_CMP
|
||
|
|
.cname $procmux$1072_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$false B[1]=$true B[2]=$false B[3]=$false B[4]=$true B[5]=$true B[6]=$false Y=$procmux$1073_CMP
|
||
|
|
.cname $procmux$1073_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$true B[1]=$false B[2]=$false B[3]=$false B[4]=$true B[5]=$true B[6]=$false Y=$procmux$1074_CMP
|
||
|
|
.cname $procmux$1074_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$false B[1]=$false B[2]=$false B[3]=$false B[4]=$true B[5]=$true B[6]=$false Y=$procmux$1075_CMP
|
||
|
|
.cname $procmux$1075_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$true B[1]=$true B[2]=$true B[3]=$true B[4]=$false B[5]=$true B[6]=$false Y=$procmux$1076_CMP
|
||
|
|
.cname $procmux$1076_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$false B[1]=$true B[2]=$true B[3]=$true B[4]=$false B[5]=$true B[6]=$false Y=$procmux$1077_CMP
|
||
|
|
.cname $procmux$1077_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$true B[1]=$false B[2]=$true B[3]=$true B[4]=$false B[5]=$true B[6]=$false Y=$procmux$1078_CMP
|
||
|
|
.cname $procmux$1078_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$false B[1]=$false B[2]=$true B[3]=$true B[4]=$false B[5]=$true B[6]=$false Y=$procmux$1079_CMP
|
||
|
|
.cname $procmux$1079_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$true B[1]=$false B[2]=$false B[3]=$true B[4]=$true B[5]=$true B[6]=$false Y=$procmux$107_CMP
|
||
|
|
.cname $procmux$107_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$true B[1]=$true B[2]=$false B[3]=$true B[4]=$false B[5]=$true B[6]=$false Y=$procmux$1080_CMP
|
||
|
|
.cname $procmux$1080_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$false B[1]=$true B[2]=$false B[3]=$true B[4]=$false B[5]=$true B[6]=$false Y=$procmux$1081_CMP
|
||
|
|
.cname $procmux$1081_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$true B[1]=$false B[2]=$false B[3]=$true B[4]=$false B[5]=$true B[6]=$false Y=$procmux$1082_CMP
|
||
|
|
.cname $procmux$1082_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$false B[1]=$false B[2]=$false B[3]=$true B[4]=$false B[5]=$true B[6]=$false Y=$procmux$1083_CMP
|
||
|
|
.cname $procmux$1083_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$true B[1]=$true B[2]=$true B[3]=$false B[4]=$false B[5]=$true B[6]=$false Y=$procmux$1084_CMP
|
||
|
|
.cname $procmux$1084_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$false B[1]=$true B[2]=$true B[3]=$false B[4]=$false B[5]=$true B[6]=$false Y=$procmux$1085_CMP
|
||
|
|
.cname $procmux$1085_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$true B[1]=$false B[2]=$true B[3]=$false B[4]=$false B[5]=$true B[6]=$false Y=$procmux$1086_CMP
|
||
|
|
.cname $procmux$1086_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$false B[1]=$false B[2]=$true B[3]=$false B[4]=$false B[5]=$true B[6]=$false Y=$procmux$1087_CMP
|
||
|
|
.cname $procmux$1087_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$true B[1]=$true B[2]=$false B[3]=$false B[4]=$false B[5]=$true B[6]=$false Y=$procmux$1088_CMP
|
||
|
|
.cname $procmux$1088_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$false B[1]=$true B[2]=$false B[3]=$false B[4]=$false B[5]=$true B[6]=$false Y=$procmux$1089_CMP
|
||
|
|
.cname $procmux$1089_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$false B[1]=$false B[2]=$false B[3]=$true B[4]=$true B[5]=$true B[6]=$false Y=$procmux$108_CMP
|
||
|
|
.cname $procmux$108_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$true B[1]=$false B[2]=$false B[3]=$false B[4]=$false B[5]=$true B[6]=$false Y=$procmux$1090_CMP
|
||
|
|
.cname $procmux$1090_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$false B[1]=$false B[2]=$false B[3]=$false B[4]=$false B[5]=$true B[6]=$false Y=$procmux$1091_CMP
|
||
|
|
.cname $procmux$1091_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$true B[1]=$true B[2]=$true B[3]=$true B[4]=$true B[5]=$false B[6]=$false Y=$procmux$1092_CMP
|
||
|
|
.cname $procmux$1092_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$false B[1]=$true B[2]=$true B[3]=$true B[4]=$true B[5]=$false B[6]=$false Y=$procmux$1093_CMP
|
||
|
|
.cname $procmux$1093_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$true B[1]=$false B[2]=$true B[3]=$true B[4]=$true B[5]=$false B[6]=$false Y=$procmux$1094_CMP
|
||
|
|
.cname $procmux$1094_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$false B[1]=$false B[2]=$true B[3]=$true B[4]=$true B[5]=$false B[6]=$false Y=$procmux$1095_CMP
|
||
|
|
.cname $procmux$1095_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$true B[1]=$true B[2]=$false B[3]=$true B[4]=$true B[5]=$false B[6]=$false Y=$procmux$1096_CMP
|
||
|
|
.cname $procmux$1096_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$false B[1]=$true B[2]=$false B[3]=$true B[4]=$true B[5]=$false B[6]=$false Y=$procmux$1097_CMP
|
||
|
|
.cname $procmux$1097_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$true B[1]=$false B[2]=$false B[3]=$true B[4]=$true B[5]=$false B[6]=$false Y=$procmux$1098_CMP
|
||
|
|
.cname $procmux$1098_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$false B[1]=$false B[2]=$false B[3]=$true B[4]=$true B[5]=$false B[6]=$false Y=$procmux$1099_CMP
|
||
|
|
.cname $procmux$1099_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$true B[1]=$true B[2]=$true B[3]=$false B[4]=$true B[5]=$true B[6]=$false Y=$procmux$109_CMP
|
||
|
|
.cname $procmux$109_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$true B[1]=$true B[2]=$true B[3]=$false B[4]=$true B[5]=$false B[6]=$false Y=$procmux$1100_CMP
|
||
|
|
.cname $procmux$1100_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$false B[1]=$true B[2]=$true B[3]=$false B[4]=$true B[5]=$false B[6]=$false Y=$procmux$1101_CMP
|
||
|
|
.cname $procmux$1101_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$true B[1]=$false B[2]=$true B[3]=$false B[4]=$true B[5]=$false B[6]=$false Y=$procmux$1102_CMP
|
||
|
|
.cname $procmux$1102_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$false B[1]=$false B[2]=$true B[3]=$false B[4]=$true B[5]=$false B[6]=$false Y=$procmux$1103_CMP
|
||
|
|
.cname $procmux$1103_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$true B[1]=$true B[2]=$false B[3]=$false B[4]=$true B[5]=$false B[6]=$false Y=$procmux$1104_CMP
|
||
|
|
.cname $procmux$1104_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$false B[1]=$true B[2]=$false B[3]=$false B[4]=$true B[5]=$false B[6]=$false Y=$procmux$1105_CMP
|
||
|
|
.cname $procmux$1105_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$true B[1]=$false B[2]=$false B[3]=$false B[4]=$true B[5]=$false B[6]=$false Y=$procmux$1106_CMP
|
||
|
|
.cname $procmux$1106_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$false B[1]=$false B[2]=$false B[3]=$false B[4]=$true B[5]=$false B[6]=$false Y=$procmux$1107_CMP
|
||
|
|
.cname $procmux$1107_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$true B[1]=$true B[2]=$false B[3]=$false B[4]=$false B[5]=$false B[6]=$false Y=$procmux$1108_CMP
|
||
|
|
.cname $procmux$1108_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$false B[1]=$true B[2]=$true B[3]=$false B[4]=$true B[5]=$true B[6]=$false Y=$procmux$110_CMP
|
||
|
|
.cname $procmux$110_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $mux A[0]=$procmux$1043_Y[0] A[1]=$procmux$1043_Y[1] A[2]=$procmux$1043_Y[2] A[3]=$procmux$1043_Y[3] A[4]=$procmux$1043_Y[4] A[5]=$procmux$1043_Y[5] A[6]=$procmux$1043_Y[6] A[7]=$procmux$1043_Y[7] A[8]=$procmux$1043_Y[8] A[9]=$procmux$1043_Y[9] A[10]=$procmux$1043_Y[10] A[11]=$procmux$1043_Y[11] A[12]=$procmux$1043_Y[12] A[13]=$procmux$1043_Y[13] A[14]=$procmux$1043_Y[14] A[15]=$procmux$1043_Y[15] A[16]=$procmux$1043_Y[16] A[17]=$procmux$1043_Y[17] A[18]=$procmux$1043_Y[18] A[19]=$procmux$1043_Y[19] A[20]=$procmux$1043_Y[20] A[21]=$procmux$1043_Y[21] A[22]=$procmux$1043_Y[22] A[23]=$procmux$1043_Y[23] A[24]=$procmux$1043_Y[24] A[25]=$procmux$1043_Y[25] A[26]=$procmux$1043_Y[26] A[27]=$procmux$1043_Y[27] A[28]=$procmux$1043_Y[28] A[29]=$procmux$1043_Y[29] A[30]=$procmux$1043_Y[30] A[31]=$procmux$1043_Y[31] B[0]=$false B[1]=$false B[2]=$false B[3]=$false B[4]=$false B[5]=$false B[6]=$false B[7]=$false B[8]=$false B[9]=$false B[10]=$false B[11]=$false B[12]=$false B[13]=$false B[14]=$false B[15]=$false B[16]=$false B[17]=$false B[18]=$false B[19]=$false B[20]=$false B[21]=$false B[22]=$false B[23]=$false B[24]=$false B[25]=$false B[26]=$false B[27]=$false B[28]=$false B[29]=$false B[30]=$false B[31]=$false S=$procmux$1111_CMP Y[0]=$procmux$1110_Y[0] Y[1]=$procmux$1110_Y[1] Y[2]=$procmux$1110_Y[2] Y[3]=$procmux$1110_Y[3] Y[4]=$procmux$1110_Y[4] Y[5]=$procmux$1110_Y[5] Y[6]=$procmux$1110_Y[6] Y[7]=$procmux$1110_Y[7] Y[8]=$procmux$1110_Y[8] Y[9]=$procmux$1110_Y[9] Y[10]=$procmux$1110_Y[10] Y[11]=$procmux$1110_Y[11] Y[12]=$procmux$1110_Y[12] Y[13]=$procmux$1110_Y[13] Y[14]=$procmux$1110_Y[14] Y[15]=$procmux$1110_Y[15] Y[16]=$procmux$1110_Y[16] Y[17]=$procmux$1110_Y[17] Y[18]=$procmux$1110_Y[18] Y[19]=$procmux$1110_Y[19] Y[20]=$procmux$1110_Y[20] Y[21]=$procmux$1110_Y[21] Y[22]=$procmux$1110_Y[22] Y[23]=$procmux$1110_Y[23] Y[24]=$procmux$1110_Y[24] Y[25]=$procmux$1110_Y[25] Y[26]=$procmux$1110_Y[26] Y[27]=$procmux$1110_Y[27] Y[28]=$procmux$1110_Y[28] Y[29]=$procmux$1110_Y[29] Y[30]=$procmux$1110_Y[30] Y[31]=$procmux$1110_Y[31]
|
||
|
|
.cname $procmux$1110
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:150"
|
||
|
|
.param WIDTH 00000000000000000000000000100000
|
||
|
|
.subckt $pmux A[0]=W2[0] A[1]=W2[1] A[2]=W2[2] A[3]=W2[3] A[4]=W2[4] A[5]=W2[5] A[6]=W2[6] A[7]=W2[7] A[8]=W2[8] A[9]=W2[9] A[10]=W2[10] A[11]=W2[11] A[12]=W2[12] A[13]=W2[13] A[14]=W2[14] A[15]=W2[15] A[16]=W2[16] A[17]=W2[17] A[18]=W2[18] A[19]=W2[19] A[20]=W2[20] A[21]=W2[21] A[22]=W2[22] A[23]=W2[23] A[24]=W2[24] A[25]=W2[25] A[26]=W2[26] A[27]=W2[27] A[28]=W2[28] A[29]=W2[29] A[30]=W2[30] A[31]=W2[31] B[0]=W3[0] B[1]=W3[1] B[2]=W3[2] B[3]=W3[3] B[4]=W3[4] B[5]=W3[5] B[6]=W3[6] B[7]=W3[7] B[8]=W3[8] B[9]=W3[9] B[10]=W3[10] B[11]=W3[11] B[12]=W3[12] B[13]=W3[13] B[14]=W3[14] B[15]=W3[15] B[16]=W3[16] B[17]=W3[17] B[18]=W3[18] B[19]=W3[19] B[20]=W3[20] B[21]=W3[21] B[22]=W3[22] B[23]=W3[23] B[24]=W3[24] B[25]=W3[25] B[26]=W3[26] B[27]=W3[27] B[28]=W3[28] B[29]=W3[29] B[30]=W3[30] B[31]=W3[31] B[32]=W3[0] B[33]=W3[1] B[34]=W3[2] B[35]=W3[3] B[36]=W3[4] B[37]=W3[5] B[38]=W3[6] B[39]=W3[7] B[40]=W3[8] B[41]=W3[9] B[42]=W3[10] B[43]=W3[11] B[44]=W3[12] B[45]=W3[13] B[46]=W3[14] B[47]=W3[15] B[48]=W3[16] B[49]=W3[17] B[50]=W3[18] B[51]=W3[19] B[52]=W3[20] B[53]=W3[21] B[54]=W3[22] B[55]=W3[23] B[56]=W3[24] B[57]=W3[25] B[58]=W3[26] B[59]=W3[27] B[60]=W3[28] B[61]=W3[29] B[62]=W3[30] B[63]=W3[31] B[64]=W3[0] B[65]=W3[1] B[66]=W3[2] B[67]=W3[3] B[68]=W3[4] B[69]=W3[5] B[70]=W3[6] B[71]=W3[7] B[72]=W3[8] B[73]=W3[9] B[74]=W3[10] B[75]=W3[11] B[76]=W3[12] B[77]=W3[13] B[78]=W3[14] B[79]=W3[15] B[80]=W3[16] B[81]=W3[17] B[82]=W3[18] B[83]=W3[19] B[84]=W3[20] B[85]=W3[21] B[86]=W3[22] B[87]=W3[23] B[88]=W3[24] B[89]=W3[25] B[90]=W3[26] B[91]=W3[27] B[92]=W3[28] B[93]=W3[29] B[94]=W3[30] B[95]=W3[31] B[96]=W3[0] B[97]=W3[1] B[98]=W3[2] B[99]=W3[3] B[100]=W3[4] B[101]=W3[5] B[102]=W3[6] B[103]=W3[7] B[104]=W3[8] B[105]=W3[9] B[106]=W3[10] B[107]=W3[11] B[108]=W3[12] B[109]=W3[13] B[110]=W3[14] B[111]=W3[15] B[112]=W3[16] B[113]=W3[17] B[114]=W3[18] B[115]=W3[19] B[116]=W3[20] B[117]=W3[21] B[118]=W3[22] B[119]=W3[23] B[120]=W3[24] B[121]=W3[25] B[122]=W3[26] B[123]=W3[27] B[124]=W3[28] B[125]=W3[29] B[126]=W3[30] B[127]=W3[31] B[128]=W3[0] B[129]=W3[1] B[130]=W3[2] B[131]=W3[3] B[132]=W3[4] B[133]=W3[5] B[134]=W3[6] B[135]=W3[7] B[136]=W3[8] B[137]=W3[9] B[138]=W3[10] B[139]=W3[11] B[140]=W3[12] B[141]=W3[13] B[142]=W3[14] B[143]=W3[15] B[144]=W3[16] B[145]=W3[17] B[146]=W3[18] B[147]=W3[19] B[148]=W3[20] B[149]=W3[21] B[150]=W3[22] B[151]=W3[23] B[152]=W3[24] B[153]=W3[25] B[154]=W3[26] B[155]=W3[27] B[156]=W3[28] B[157]=W3[29] B[158]=W3[30] B[159]=W3[31] B[160]=W3[0] B[161]=W3[1] B[162]=W3[2] B[163]=W3[3] B[164]=W3[4] B[165]=W3[5] B[166]=W3[6] B[167]=W3[7] B[168]=W3[8] B[169]=W3[9] B[170]=W3[10] B[171]=W3[11] B[172]=W3[12] B[173]=W3[13] B[174]=W3[14] B[175]=W3[15] B[176]=W3[16] B[177]=W3[17] B[178]=W3[18] B[179]=W3[19] B[180]=W3[20] B[181]=W3[21] B[182]=W3[22] B[183]=W3[23] B[184]=W3[24] B[185]=W3[25] B[186]=W3[26] B[187]=W3[27] B[188]=W3[28] B[189]=W3[29] B[190]=W3[30] B[191]=W3[31] B[192]=W3[0] B[193]=W3[1] B[194]=W3[2] B[195]=W3[3] B[196]=W3[4] B[197]=W3[5] B[198]=W3[6] B[199]=W3[7] B[200]=W3[8] B[201]=W3[9] B[202]=W3[10] B[203]=W3[11] B[204]=W3[12] B[205]=W3[13] B[206]=W3[14] B[207]=W3[15] B[208]=W3[16] B[209]=W3[17] B[210]=W3[18] B[211]=W3[19] B[212]=W3[20] B[213]=W3[21] B[214]=W3[22] B[215]=W3[23] B[216]=W3[24] B[217]=W3[25] B[218]=W3[26] B[219]=W3[27] B[220]=W3[28] B[221]=W3[29] B[222]=W3[30] B[223]=W3[31] B[224]=W3[0] B[225]=W3[1] B[226]=W3[2] B[227]=W3[3] B[228]=W3[4] B[229]=W3[5] B[230]=W3[6] B[231]=W3[7] B[232]=W3[8] B[233]=W3[9] B[234]=W3[10] B[235]=W3[11] B[236]=W3[12] B[237]=W3[13] B[238]=W3[14] B[239]=W3[15] B[240]=W3[16] B[241]=W3[17] B[242]=W3[18] B[243]=W3[19] B[244]=W3[20] B[245]=W3[21] B[246]=W3[22] B[247]=W3[23] B[248]=W3[24] B[249]=W3[25] B[250]=W3[26] B[251]=W3[27] B[252]=W3[28] B[253]=W3[29] B[254]=W3[30] B[255]=W3[31] B[256]=W3[0] B[257]=W3[1] B[258]=W3[2] B[259]=W3[3] B[260]=W3[4] B[261]=W3[5] B[262]=W3[6] B[263]=W3[7] B[264]=W3[8] B[265]=W3[9] B[266]=W3[10] B[267]=W3[11] B[268]=W3[12] B[269]=W3[13] B[270]=W3[14] B[271]=W3[15] B[272]=W3[16] B[273]=W3[17] B[274]=W3[18] B[275]=W3[19] B[276]=W3[20] B[277]=
|
||
|
|
.cname $procmux$1114
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param S_WIDTH 00000000000000000000000001000001
|
||
|
|
.param WIDTH 00000000000000000000000000100000
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$true B[1]=$true B[2]=$true B[3]=$true B[4]=$false B[5]=$false B[6]=$true Y=$procmux$1115_CMP
|
||
|
|
.cname $procmux$1115_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$false B[1]=$true B[2]=$true B[3]=$true B[4]=$false B[5]=$false B[6]=$true Y=$procmux$1116_CMP
|
||
|
|
.cname $procmux$1116_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$true B[1]=$false B[2]=$true B[3]=$true B[4]=$false B[5]=$false B[6]=$true Y=$procmux$1117_CMP
|
||
|
|
.cname $procmux$1117_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$false B[1]=$false B[2]=$true B[3]=$true B[4]=$false B[5]=$false B[6]=$true Y=$procmux$1118_CMP
|
||
|
|
.cname $procmux$1118_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$true B[1]=$true B[2]=$false B[3]=$true B[4]=$false B[5]=$false B[6]=$true Y=$procmux$1119_CMP
|
||
|
|
.cname $procmux$1119_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$true B[1]=$false B[2]=$true B[3]=$false B[4]=$true B[5]=$true B[6]=$false Y=$procmux$111_CMP
|
||
|
|
.cname $procmux$111_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$false B[1]=$true B[2]=$false B[3]=$true B[4]=$false B[5]=$false B[6]=$true Y=$procmux$1120_CMP
|
||
|
|
.cname $procmux$1120_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$true B[1]=$false B[2]=$false B[3]=$true B[4]=$false B[5]=$false B[6]=$true Y=$procmux$1121_CMP
|
||
|
|
.cname $procmux$1121_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$false B[1]=$false B[2]=$false B[3]=$true B[4]=$false B[5]=$false B[6]=$true Y=$procmux$1122_CMP
|
||
|
|
.cname $procmux$1122_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$true B[1]=$true B[2]=$true B[3]=$false B[4]=$false B[5]=$false B[6]=$true Y=$procmux$1123_CMP
|
||
|
|
.cname $procmux$1123_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$false B[1]=$true B[2]=$true B[3]=$false B[4]=$false B[5]=$false B[6]=$true Y=$procmux$1124_CMP
|
||
|
|
.cname $procmux$1124_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$true B[1]=$false B[2]=$true B[3]=$false B[4]=$false B[5]=$false B[6]=$true Y=$procmux$1125_CMP
|
||
|
|
.cname $procmux$1125_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$false B[1]=$false B[2]=$true B[3]=$false B[4]=$false B[5]=$false B[6]=$true Y=$procmux$1126_CMP
|
||
|
|
.cname $procmux$1126_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$true B[1]=$true B[2]=$false B[3]=$false B[4]=$false B[5]=$false B[6]=$true Y=$procmux$1127_CMP
|
||
|
|
.cname $procmux$1127_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$false B[1]=$true B[2]=$false B[3]=$false B[4]=$false B[5]=$false B[6]=$true Y=$procmux$1128_CMP
|
||
|
|
.cname $procmux$1128_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$true B[1]=$false B[2]=$false B[3]=$false B[4]=$false B[5]=$false B[6]=$true Y=$procmux$1129_CMP
|
||
|
|
.cname $procmux$1129_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$false B[1]=$false B[2]=$true B[3]=$false B[4]=$true B[5]=$true B[6]=$false Y=$procmux$112_CMP
|
||
|
|
.cname $procmux$112_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$false B[1]=$false B[2]=$false B[3]=$false B[4]=$false B[5]=$false B[6]=$true Y=$procmux$1130_CMP
|
||
|
|
.cname $procmux$1130_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$true B[1]=$true B[2]=$true B[3]=$true B[4]=$true B[5]=$true B[6]=$false Y=$procmux$1131_CMP
|
||
|
|
.cname $procmux$1131_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$false B[1]=$true B[2]=$true B[3]=$true B[4]=$true B[5]=$true B[6]=$false Y=$procmux$1132_CMP
|
||
|
|
.cname $procmux$1132_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$true B[1]=$false B[2]=$true B[3]=$true B[4]=$true B[5]=$true B[6]=$false Y=$procmux$1133_CMP
|
||
|
|
.cname $procmux$1133_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$false B[1]=$false B[2]=$true B[3]=$true B[4]=$true B[5]=$true B[6]=$false Y=$procmux$1134_CMP
|
||
|
|
.cname $procmux$1134_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$true B[1]=$true B[2]=$false B[3]=$true B[4]=$true B[5]=$true B[6]=$false Y=$procmux$1135_CMP
|
||
|
|
.cname $procmux$1135_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$false B[1]=$true B[2]=$false B[3]=$true B[4]=$true B[5]=$true B[6]=$false Y=$procmux$1136_CMP
|
||
|
|
.cname $procmux$1136_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$true B[1]=$false B[2]=$false B[3]=$true B[4]=$true B[5]=$true B[6]=$false Y=$procmux$1137_CMP
|
||
|
|
.cname $procmux$1137_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$false B[1]=$false B[2]=$false B[3]=$true B[4]=$true B[5]=$true B[6]=$false Y=$procmux$1138_CMP
|
||
|
|
.cname $procmux$1138_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$true B[1]=$true B[2]=$true B[3]=$false B[4]=$true B[5]=$true B[6]=$false Y=$procmux$1139_CMP
|
||
|
|
.cname $procmux$1139_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$true B[1]=$true B[2]=$false B[3]=$false B[4]=$true B[5]=$true B[6]=$false Y=$procmux$113_CMP
|
||
|
|
.cname $procmux$113_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$false B[1]=$true B[2]=$true B[3]=$false B[4]=$true B[5]=$true B[6]=$false Y=$procmux$1140_CMP
|
||
|
|
.cname $procmux$1140_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$true B[1]=$false B[2]=$true B[3]=$false B[4]=$true B[5]=$true B[6]=$false Y=$procmux$1141_CMP
|
||
|
|
.cname $procmux$1141_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$false B[1]=$false B[2]=$true B[3]=$false B[4]=$true B[5]=$true B[6]=$false Y=$procmux$1142_CMP
|
||
|
|
.cname $procmux$1142_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$true B[1]=$true B[2]=$false B[3]=$false B[4]=$true B[5]=$true B[6]=$false Y=$procmux$1143_CMP
|
||
|
|
.cname $procmux$1143_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$false B[1]=$true B[2]=$false B[3]=$false B[4]=$true B[5]=$true B[6]=$false Y=$procmux$1144_CMP
|
||
|
|
.cname $procmux$1144_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$true B[1]=$false B[2]=$false B[3]=$false B[4]=$true B[5]=$true B[6]=$false Y=$procmux$1145_CMP
|
||
|
|
.cname $procmux$1145_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$false B[1]=$false B[2]=$false B[3]=$false B[4]=$true B[5]=$true B[6]=$false Y=$procmux$1146_CMP
|
||
|
|
.cname $procmux$1146_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$true B[1]=$true B[2]=$true B[3]=$true B[4]=$false B[5]=$true B[6]=$false Y=$procmux$1147_CMP
|
||
|
|
.cname $procmux$1147_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$false B[1]=$true B[2]=$true B[3]=$true B[4]=$false B[5]=$true B[6]=$false Y=$procmux$1148_CMP
|
||
|
|
.cname $procmux$1148_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$true B[1]=$false B[2]=$true B[3]=$true B[4]=$false B[5]=$true B[6]=$false Y=$procmux$1149_CMP
|
||
|
|
.cname $procmux$1149_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$false B[1]=$true B[2]=$false B[3]=$false B[4]=$true B[5]=$true B[6]=$false Y=$procmux$114_CMP
|
||
|
|
.cname $procmux$114_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$false B[1]=$false B[2]=$true B[3]=$true B[4]=$false B[5]=$true B[6]=$false Y=$procmux$1150_CMP
|
||
|
|
.cname $procmux$1150_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$true B[1]=$true B[2]=$false B[3]=$true B[4]=$false B[5]=$true B[6]=$false Y=$procmux$1151_CMP
|
||
|
|
.cname $procmux$1151_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$false B[1]=$true B[2]=$false B[3]=$true B[4]=$false B[5]=$true B[6]=$false Y=$procmux$1152_CMP
|
||
|
|
.cname $procmux$1152_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$true B[1]=$false B[2]=$false B[3]=$true B[4]=$false B[5]=$true B[6]=$false Y=$procmux$1153_CMP
|
||
|
|
.cname $procmux$1153_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$false B[1]=$false B[2]=$false B[3]=$true B[4]=$false B[5]=$true B[6]=$false Y=$procmux$1154_CMP
|
||
|
|
.cname $procmux$1154_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$true B[1]=$true B[2]=$true B[3]=$false B[4]=$false B[5]=$true B[6]=$false Y=$procmux$1155_CMP
|
||
|
|
.cname $procmux$1155_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$false B[1]=$true B[2]=$true B[3]=$false B[4]=$false B[5]=$true B[6]=$false Y=$procmux$1156_CMP
|
||
|
|
.cname $procmux$1156_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$true B[1]=$false B[2]=$true B[3]=$false B[4]=$false B[5]=$true B[6]=$false Y=$procmux$1157_CMP
|
||
|
|
.cname $procmux$1157_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$false B[1]=$false B[2]=$true B[3]=$false B[4]=$false B[5]=$true B[6]=$false Y=$procmux$1158_CMP
|
||
|
|
.cname $procmux$1158_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$true B[1]=$true B[2]=$false B[3]=$false B[4]=$false B[5]=$true B[6]=$false Y=$procmux$1159_CMP
|
||
|
|
.cname $procmux$1159_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$true B[1]=$false B[2]=$false B[3]=$false B[4]=$true B[5]=$true B[6]=$false Y=$procmux$115_CMP
|
||
|
|
.cname $procmux$115_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$false B[1]=$true B[2]=$false B[3]=$false B[4]=$false B[5]=$true B[6]=$false Y=$procmux$1160_CMP
|
||
|
|
.cname $procmux$1160_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$true B[1]=$false B[2]=$false B[3]=$false B[4]=$false B[5]=$true B[6]=$false Y=$procmux$1161_CMP
|
||
|
|
.cname $procmux$1161_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$false B[1]=$false B[2]=$false B[3]=$false B[4]=$false B[5]=$true B[6]=$false Y=$procmux$1162_CMP
|
||
|
|
.cname $procmux$1162_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$true B[1]=$true B[2]=$true B[3]=$true B[4]=$true B[5]=$false B[6]=$false Y=$procmux$1163_CMP
|
||
|
|
.cname $procmux$1163_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$false B[1]=$true B[2]=$true B[3]=$true B[4]=$true B[5]=$false B[6]=$false Y=$procmux$1164_CMP
|
||
|
|
.cname $procmux$1164_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$true B[1]=$false B[2]=$true B[3]=$true B[4]=$true B[5]=$false B[6]=$false Y=$procmux$1165_CMP
|
||
|
|
.cname $procmux$1165_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$false B[1]=$false B[2]=$true B[3]=$true B[4]=$true B[5]=$false B[6]=$false Y=$procmux$1166_CMP
|
||
|
|
.cname $procmux$1166_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$true B[1]=$true B[2]=$false B[3]=$true B[4]=$true B[5]=$false B[6]=$false Y=$procmux$1167_CMP
|
||
|
|
.cname $procmux$1167_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$false B[1]=$true B[2]=$false B[3]=$true B[4]=$true B[5]=$false B[6]=$false Y=$procmux$1168_CMP
|
||
|
|
.cname $procmux$1168_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$true B[1]=$false B[2]=$false B[3]=$true B[4]=$true B[5]=$false B[6]=$false Y=$procmux$1169_CMP
|
||
|
|
.cname $procmux$1169_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$false B[1]=$false B[2]=$false B[3]=$false B[4]=$true B[5]=$true B[6]=$false Y=$procmux$116_CMP
|
||
|
|
.cname $procmux$116_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$false B[1]=$false B[2]=$false B[3]=$true B[4]=$true B[5]=$false B[6]=$false Y=$procmux$1170_CMP
|
||
|
|
.cname $procmux$1170_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$true B[1]=$true B[2]=$true B[3]=$false B[4]=$true B[5]=$false B[6]=$false Y=$procmux$1171_CMP
|
||
|
|
.cname $procmux$1171_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$false B[1]=$true B[2]=$true B[3]=$false B[4]=$true B[5]=$false B[6]=$false Y=$procmux$1172_CMP
|
||
|
|
.cname $procmux$1172_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$true B[1]=$false B[2]=$true B[3]=$false B[4]=$true B[5]=$false B[6]=$false Y=$procmux$1173_CMP
|
||
|
|
.cname $procmux$1173_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$false B[1]=$false B[2]=$true B[3]=$false B[4]=$true B[5]=$false B[6]=$false Y=$procmux$1174_CMP
|
||
|
|
.cname $procmux$1174_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$true B[1]=$true B[2]=$false B[3]=$false B[4]=$true B[5]=$false B[6]=$false Y=$procmux$1175_CMP
|
||
|
|
.cname $procmux$1175_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$false B[1]=$true B[2]=$false B[3]=$false B[4]=$true B[5]=$false B[6]=$false Y=$procmux$1176_CMP
|
||
|
|
.cname $procmux$1176_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$true B[1]=$false B[2]=$false B[3]=$false B[4]=$true B[5]=$false B[6]=$false Y=$procmux$1177_CMP
|
||
|
|
.cname $procmux$1177_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$false B[1]=$false B[2]=$false B[3]=$false B[4]=$true B[5]=$false B[6]=$false Y=$procmux$1178_CMP
|
||
|
|
.cname $procmux$1178_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$false B[1]=$true B[2]=$false B[3]=$false B[4]=$false B[5]=$false B[6]=$false Y=$procmux$1179_CMP
|
||
|
|
.cname $procmux$1179_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$true B[1]=$true B[2]=$true B[3]=$true B[4]=$false B[5]=$true B[6]=$false Y=$procmux$117_CMP
|
||
|
|
.cname $procmux$117_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $mux A[0]=$procmux$1114_Y[0] A[1]=$procmux$1114_Y[1] A[2]=$procmux$1114_Y[2] A[3]=$procmux$1114_Y[3] A[4]=$procmux$1114_Y[4] A[5]=$procmux$1114_Y[5] A[6]=$procmux$1114_Y[6] A[7]=$procmux$1114_Y[7] A[8]=$procmux$1114_Y[8] A[9]=$procmux$1114_Y[9] A[10]=$procmux$1114_Y[10] A[11]=$procmux$1114_Y[11] A[12]=$procmux$1114_Y[12] A[13]=$procmux$1114_Y[13] A[14]=$procmux$1114_Y[14] A[15]=$procmux$1114_Y[15] A[16]=$procmux$1114_Y[16] A[17]=$procmux$1114_Y[17] A[18]=$procmux$1114_Y[18] A[19]=$procmux$1114_Y[19] A[20]=$procmux$1114_Y[20] A[21]=$procmux$1114_Y[21] A[22]=$procmux$1114_Y[22] A[23]=$procmux$1114_Y[23] A[24]=$procmux$1114_Y[24] A[25]=$procmux$1114_Y[25] A[26]=$procmux$1114_Y[26] A[27]=$procmux$1114_Y[27] A[28]=$procmux$1114_Y[28] A[29]=$procmux$1114_Y[29] A[30]=$procmux$1114_Y[30] A[31]=$procmux$1114_Y[31] B[0]=$false B[1]=$false B[2]=$false B[3]=$false B[4]=$false B[5]=$false B[6]=$false B[7]=$false B[8]=$false B[9]=$false B[10]=$false B[11]=$false B[12]=$false B[13]=$false B[14]=$false B[15]=$false B[16]=$false B[17]=$false B[18]=$false B[19]=$false B[20]=$false B[21]=$false B[22]=$false B[23]=$false B[24]=$false B[25]=$false B[26]=$false B[27]=$false B[28]=$false B[29]=$false B[30]=$false B[31]=$false S=$procmux$1182_CMP Y[0]=$procmux$1181_Y[0] Y[1]=$procmux$1181_Y[1] Y[2]=$procmux$1181_Y[2] Y[3]=$procmux$1181_Y[3] Y[4]=$procmux$1181_Y[4] Y[5]=$procmux$1181_Y[5] Y[6]=$procmux$1181_Y[6] Y[7]=$procmux$1181_Y[7] Y[8]=$procmux$1181_Y[8] Y[9]=$procmux$1181_Y[9] Y[10]=$procmux$1181_Y[10] Y[11]=$procmux$1181_Y[11] Y[12]=$procmux$1181_Y[12] Y[13]=$procmux$1181_Y[13] Y[14]=$procmux$1181_Y[14] Y[15]=$procmux$1181_Y[15] Y[16]=$procmux$1181_Y[16] Y[17]=$procmux$1181_Y[17] Y[18]=$procmux$1181_Y[18] Y[19]=$procmux$1181_Y[19] Y[20]=$procmux$1181_Y[20] Y[21]=$procmux$1181_Y[21] Y[22]=$procmux$1181_Y[22] Y[23]=$procmux$1181_Y[23] Y[24]=$procmux$1181_Y[24] Y[25]=$procmux$1181_Y[25] Y[26]=$procmux$1181_Y[26] Y[27]=$procmux$1181_Y[27] Y[28]=$procmux$1181_Y[28] Y[29]=$procmux$1181_Y[29] Y[30]=$procmux$1181_Y[30] Y[31]=$procmux$1181_Y[31]
|
||
|
|
.cname $procmux$1181
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:150"
|
||
|
|
.param WIDTH 00000000000000000000000000100000
|
||
|
|
.subckt $pmux A[0]=W1[0] A[1]=W1[1] A[2]=W1[2] A[3]=W1[3] A[4]=W1[4] A[5]=W1[5] A[6]=W1[6] A[7]=W1[7] A[8]=W1[8] A[9]=W1[9] A[10]=W1[10] A[11]=W1[11] A[12]=W1[12] A[13]=W1[13] A[14]=W1[14] A[15]=W1[15] A[16]=W1[16] A[17]=W1[17] A[18]=W1[18] A[19]=W1[19] A[20]=W1[20] A[21]=W1[21] A[22]=W1[22] A[23]=W1[23] A[24]=W1[24] A[25]=W1[25] A[26]=W1[26] A[27]=W1[27] A[28]=W1[28] A[29]=W1[29] A[30]=W1[30] A[31]=W1[31] B[0]=W2[0] B[1]=W2[1] B[2]=W2[2] B[3]=W2[3] B[4]=W2[4] B[5]=W2[5] B[6]=W2[6] B[7]=W2[7] B[8]=W2[8] B[9]=W2[9] B[10]=W2[10] B[11]=W2[11] B[12]=W2[12] B[13]=W2[13] B[14]=W2[14] B[15]=W2[15] B[16]=W2[16] B[17]=W2[17] B[18]=W2[18] B[19]=W2[19] B[20]=W2[20] B[21]=W2[21] B[22]=W2[22] B[23]=W2[23] B[24]=W2[24] B[25]=W2[25] B[26]=W2[26] B[27]=W2[27] B[28]=W2[28] B[29]=W2[29] B[30]=W2[30] B[31]=W2[31] B[32]=W2[0] B[33]=W2[1] B[34]=W2[2] B[35]=W2[3] B[36]=W2[4] B[37]=W2[5] B[38]=W2[6] B[39]=W2[7] B[40]=W2[8] B[41]=W2[9] B[42]=W2[10] B[43]=W2[11] B[44]=W2[12] B[45]=W2[13] B[46]=W2[14] B[47]=W2[15] B[48]=W2[16] B[49]=W2[17] B[50]=W2[18] B[51]=W2[19] B[52]=W2[20] B[53]=W2[21] B[54]=W2[22] B[55]=W2[23] B[56]=W2[24] B[57]=W2[25] B[58]=W2[26] B[59]=W2[27] B[60]=W2[28] B[61]=W2[29] B[62]=W2[30] B[63]=W2[31] B[64]=W2[0] B[65]=W2[1] B[66]=W2[2] B[67]=W2[3] B[68]=W2[4] B[69]=W2[5] B[70]=W2[6] B[71]=W2[7] B[72]=W2[8] B[73]=W2[9] B[74]=W2[10] B[75]=W2[11] B[76]=W2[12] B[77]=W2[13] B[78]=W2[14] B[79]=W2[15] B[80]=W2[16] B[81]=W2[17] B[82]=W2[18] B[83]=W2[19] B[84]=W2[20] B[85]=W2[21] B[86]=W2[22] B[87]=W2[23] B[88]=W2[24] B[89]=W2[25] B[90]=W2[26] B[91]=W2[27] B[92]=W2[28] B[93]=W2[29] B[94]=W2[30] B[95]=W2[31] B[96]=W2[0] B[97]=W2[1] B[98]=W2[2] B[99]=W2[3] B[100]=W2[4] B[101]=W2[5] B[102]=W2[6] B[103]=W2[7] B[104]=W2[8] B[105]=W2[9] B[106]=W2[10] B[107]=W2[11] B[108]=W2[12] B[109]=W2[13] B[110]=W2[14] B[111]=W2[15] B[112]=W2[16] B[113]=W2[17] B[114]=W2[18] B[115]=W2[19] B[116]=W2[20] B[117]=W2[21] B[118]=W2[22] B[119]=W2[23] B[120]=W2[24] B[121]=W2[25] B[122]=W2[26] B[123]=W2[27] B[124]=W2[28] B[125]=W2[29] B[126]=W2[30] B[127]=W2[31] B[128]=W2[0] B[129]=W2[1] B[130]=W2[2] B[131]=W2[3] B[132]=W2[4] B[133]=W2[5] B[134]=W2[6] B[135]=W2[7] B[136]=W2[8] B[137]=W2[9] B[138]=W2[10] B[139]=W2[11] B[140]=W2[12] B[141]=W2[13] B[142]=W2[14] B[143]=W2[15] B[144]=W2[16] B[145]=W2[17] B[146]=W2[18] B[147]=W2[19] B[148]=W2[20] B[149]=W2[21] B[150]=W2[22] B[151]=W2[23] B[152]=W2[24] B[153]=W2[25] B[154]=W2[26] B[155]=W2[27] B[156]=W2[28] B[157]=W2[29] B[158]=W2[30] B[159]=W2[31] B[160]=W2[0] B[161]=W2[1] B[162]=W2[2] B[163]=W2[3] B[164]=W2[4] B[165]=W2[5] B[166]=W2[6] B[167]=W2[7] B[168]=W2[8] B[169]=W2[9] B[170]=W2[10] B[171]=W2[11] B[172]=W2[12] B[173]=W2[13] B[174]=W2[14] B[175]=W2[15] B[176]=W2[16] B[177]=W2[17] B[178]=W2[18] B[179]=W2[19] B[180]=W2[20] B[181]=W2[21] B[182]=W2[22] B[183]=W2[23] B[184]=W2[24] B[185]=W2[25] B[186]=W2[26] B[187]=W2[27] B[188]=W2[28] B[189]=W2[29] B[190]=W2[30] B[191]=W2[31] B[192]=W2[0] B[193]=W2[1] B[194]=W2[2] B[195]=W2[3] B[196]=W2[4] B[197]=W2[5] B[198]=W2[6] B[199]=W2[7] B[200]=W2[8] B[201]=W2[9] B[202]=W2[10] B[203]=W2[11] B[204]=W2[12] B[205]=W2[13] B[206]=W2[14] B[207]=W2[15] B[208]=W2[16] B[209]=W2[17] B[210]=W2[18] B[211]=W2[19] B[212]=W2[20] B[213]=W2[21] B[214]=W2[22] B[215]=W2[23] B[216]=W2[24] B[217]=W2[25] B[218]=W2[26] B[219]=W2[27] B[220]=W2[28] B[221]=W2[29] B[222]=W2[30] B[223]=W2[31] B[224]=W2[0] B[225]=W2[1] B[226]=W2[2] B[227]=W2[3] B[228]=W2[4] B[229]=W2[5] B[230]=W2[6] B[231]=W2[7] B[232]=W2[8] B[233]=W2[9] B[234]=W2[10] B[235]=W2[11] B[236]=W2[12] B[237]=W2[13] B[238]=W2[14] B[239]=W2[15] B[240]=W2[16] B[241]=W2[17] B[242]=W2[18] B[243]=W2[19] B[244]=W2[20] B[245]=W2[21] B[246]=W2[22] B[247]=W2[23] B[248]=W2[24] B[249]=W2[25] B[250]=W2[26] B[251]=W2[27] B[252]=W2[28] B[253]=W2[29] B[254]=W2[30] B[255]=W2[31] B[256]=W2[0] B[257]=W2[1] B[258]=W2[2] B[259]=W2[3] B[260]=W2[4] B[261]=W2[5] B[262]=W2[6] B[263]=W2[7] B[264]=W2[8] B[265]=W2[9] B[266]=W2[10] B[267]=W2[11] B[268]=W2[12] B[269]=W2[13] B[270]=W2[14] B[271]=W2[15] B[272]=W2[16] B[273]=W2[17] B[274]=W2[18] B[275]=W2[19] B[276]=W2[20] B[277]=
|
||
|
|
.cname $procmux$1185
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param S_WIDTH 00000000000000000000000001000001
|
||
|
|
.param WIDTH 00000000000000000000000000100000
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$true B[1]=$true B[2]=$true B[3]=$true B[4]=$false B[5]=$false B[6]=$true Y=$procmux$1186_CMP
|
||
|
|
.cname $procmux$1186_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$false B[1]=$true B[2]=$true B[3]=$true B[4]=$false B[5]=$false B[6]=$true Y=$procmux$1187_CMP
|
||
|
|
.cname $procmux$1187_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$true B[1]=$false B[2]=$true B[3]=$true B[4]=$false B[5]=$false B[6]=$true Y=$procmux$1188_CMP
|
||
|
|
.cname $procmux$1188_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$false B[1]=$false B[2]=$true B[3]=$true B[4]=$false B[5]=$false B[6]=$true Y=$procmux$1189_CMP
|
||
|
|
.cname $procmux$1189_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$false B[1]=$true B[2]=$true B[3]=$true B[4]=$false B[5]=$true B[6]=$false Y=$procmux$118_CMP
|
||
|
|
.cname $procmux$118_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$true B[1]=$true B[2]=$false B[3]=$true B[4]=$false B[5]=$false B[6]=$true Y=$procmux$1190_CMP
|
||
|
|
.cname $procmux$1190_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$false B[1]=$true B[2]=$false B[3]=$true B[4]=$false B[5]=$false B[6]=$true Y=$procmux$1191_CMP
|
||
|
|
.cname $procmux$1191_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$true B[1]=$false B[2]=$false B[3]=$true B[4]=$false B[5]=$false B[6]=$true Y=$procmux$1192_CMP
|
||
|
|
.cname $procmux$1192_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$false B[1]=$false B[2]=$false B[3]=$true B[4]=$false B[5]=$false B[6]=$true Y=$procmux$1193_CMP
|
||
|
|
.cname $procmux$1193_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$true B[1]=$true B[2]=$true B[3]=$false B[4]=$false B[5]=$false B[6]=$true Y=$procmux$1194_CMP
|
||
|
|
.cname $procmux$1194_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$false B[1]=$true B[2]=$true B[3]=$false B[4]=$false B[5]=$false B[6]=$true Y=$procmux$1195_CMP
|
||
|
|
.cname $procmux$1195_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$true B[1]=$false B[2]=$true B[3]=$false B[4]=$false B[5]=$false B[6]=$true Y=$procmux$1196_CMP
|
||
|
|
.cname $procmux$1196_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$false B[1]=$false B[2]=$true B[3]=$false B[4]=$false B[5]=$false B[6]=$true Y=$procmux$1197_CMP
|
||
|
|
.cname $procmux$1197_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$true B[1]=$true B[2]=$false B[3]=$false B[4]=$false B[5]=$false B[6]=$true Y=$procmux$1198_CMP
|
||
|
|
.cname $procmux$1198_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$false B[1]=$true B[2]=$false B[3]=$false B[4]=$false B[5]=$false B[6]=$true Y=$procmux$1199_CMP
|
||
|
|
.cname $procmux$1199_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$true B[1]=$false B[2]=$true B[3]=$true B[4]=$false B[5]=$true B[6]=$false Y=$procmux$119_CMP
|
||
|
|
.cname $procmux$119_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$true B[1]=$false B[2]=$false B[3]=$false B[4]=$false B[5]=$false B[6]=$true Y=$procmux$1200_CMP
|
||
|
|
.cname $procmux$1200_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$false B[1]=$false B[2]=$false B[3]=$false B[4]=$false B[5]=$false B[6]=$true Y=$procmux$1201_CMP
|
||
|
|
.cname $procmux$1201_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$true B[1]=$true B[2]=$true B[3]=$true B[4]=$true B[5]=$true B[6]=$false Y=$procmux$1202_CMP
|
||
|
|
.cname $procmux$1202_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$false B[1]=$true B[2]=$true B[3]=$true B[4]=$true B[5]=$true B[6]=$false Y=$procmux$1203_CMP
|
||
|
|
.cname $procmux$1203_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$true B[1]=$false B[2]=$true B[3]=$true B[4]=$true B[5]=$true B[6]=$false Y=$procmux$1204_CMP
|
||
|
|
.cname $procmux$1204_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$false B[1]=$false B[2]=$true B[3]=$true B[4]=$true B[5]=$true B[6]=$false Y=$procmux$1205_CMP
|
||
|
|
.cname $procmux$1205_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$true B[1]=$true B[2]=$false B[3]=$true B[4]=$true B[5]=$true B[6]=$false Y=$procmux$1206_CMP
|
||
|
|
.cname $procmux$1206_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$false B[1]=$true B[2]=$false B[3]=$true B[4]=$true B[5]=$true B[6]=$false Y=$procmux$1207_CMP
|
||
|
|
.cname $procmux$1207_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$true B[1]=$false B[2]=$false B[3]=$true B[4]=$true B[5]=$true B[6]=$false Y=$procmux$1208_CMP
|
||
|
|
.cname $procmux$1208_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$false B[1]=$false B[2]=$false B[3]=$true B[4]=$true B[5]=$true B[6]=$false Y=$procmux$1209_CMP
|
||
|
|
.cname $procmux$1209_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$false B[1]=$false B[2]=$true B[3]=$true B[4]=$false B[5]=$true B[6]=$false Y=$procmux$120_CMP
|
||
|
|
.cname $procmux$120_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$true B[1]=$true B[2]=$true B[3]=$false B[4]=$true B[5]=$true B[6]=$false Y=$procmux$1210_CMP
|
||
|
|
.cname $procmux$1210_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$false B[1]=$true B[2]=$true B[3]=$false B[4]=$true B[5]=$true B[6]=$false Y=$procmux$1211_CMP
|
||
|
|
.cname $procmux$1211_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$true B[1]=$false B[2]=$true B[3]=$false B[4]=$true B[5]=$true B[6]=$false Y=$procmux$1212_CMP
|
||
|
|
.cname $procmux$1212_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$false B[1]=$false B[2]=$true B[3]=$false B[4]=$true B[5]=$true B[6]=$false Y=$procmux$1213_CMP
|
||
|
|
.cname $procmux$1213_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$true B[1]=$true B[2]=$false B[3]=$false B[4]=$true B[5]=$true B[6]=$false Y=$procmux$1214_CMP
|
||
|
|
.cname $procmux$1214_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$false B[1]=$true B[2]=$false B[3]=$false B[4]=$true B[5]=$true B[6]=$false Y=$procmux$1215_CMP
|
||
|
|
.cname $procmux$1215_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$true B[1]=$false B[2]=$false B[3]=$false B[4]=$true B[5]=$true B[6]=$false Y=$procmux$1216_CMP
|
||
|
|
.cname $procmux$1216_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$false B[1]=$false B[2]=$false B[3]=$false B[4]=$true B[5]=$true B[6]=$false Y=$procmux$1217_CMP
|
||
|
|
.cname $procmux$1217_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$true B[1]=$true B[2]=$true B[3]=$true B[4]=$false B[5]=$true B[6]=$false Y=$procmux$1218_CMP
|
||
|
|
.cname $procmux$1218_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$false B[1]=$true B[2]=$true B[3]=$true B[4]=$false B[5]=$true B[6]=$false Y=$procmux$1219_CMP
|
||
|
|
.cname $procmux$1219_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$true B[1]=$true B[2]=$false B[3]=$true B[4]=$false B[5]=$true B[6]=$false Y=$procmux$121_CMP
|
||
|
|
.cname $procmux$121_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$true B[1]=$false B[2]=$true B[3]=$true B[4]=$false B[5]=$true B[6]=$false Y=$procmux$1220_CMP
|
||
|
|
.cname $procmux$1220_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$false B[1]=$false B[2]=$true B[3]=$true B[4]=$false B[5]=$true B[6]=$false Y=$procmux$1221_CMP
|
||
|
|
.cname $procmux$1221_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$true B[1]=$true B[2]=$false B[3]=$true B[4]=$false B[5]=$true B[6]=$false Y=$procmux$1222_CMP
|
||
|
|
.cname $procmux$1222_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$false B[1]=$true B[2]=$false B[3]=$true B[4]=$false B[5]=$true B[6]=$false Y=$procmux$1223_CMP
|
||
|
|
.cname $procmux$1223_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$true B[1]=$false B[2]=$false B[3]=$true B[4]=$false B[5]=$true B[6]=$false Y=$procmux$1224_CMP
|
||
|
|
.cname $procmux$1224_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$false B[1]=$false B[2]=$false B[3]=$true B[4]=$false B[5]=$true B[6]=$false Y=$procmux$1225_CMP
|
||
|
|
.cname $procmux$1225_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$true B[1]=$true B[2]=$true B[3]=$false B[4]=$false B[5]=$true B[6]=$false Y=$procmux$1226_CMP
|
||
|
|
.cname $procmux$1226_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$false B[1]=$true B[2]=$true B[3]=$false B[4]=$false B[5]=$true B[6]=$false Y=$procmux$1227_CMP
|
||
|
|
.cname $procmux$1227_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$true B[1]=$false B[2]=$true B[3]=$false B[4]=$false B[5]=$true B[6]=$false Y=$procmux$1228_CMP
|
||
|
|
.cname $procmux$1228_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$false B[1]=$false B[2]=$true B[3]=$false B[4]=$false B[5]=$true B[6]=$false Y=$procmux$1229_CMP
|
||
|
|
.cname $procmux$1229_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$false B[1]=$true B[2]=$false B[3]=$true B[4]=$false B[5]=$true B[6]=$false Y=$procmux$122_CMP
|
||
|
|
.cname $procmux$122_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$true B[1]=$true B[2]=$false B[3]=$false B[4]=$false B[5]=$true B[6]=$false Y=$procmux$1230_CMP
|
||
|
|
.cname $procmux$1230_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$false B[1]=$true B[2]=$false B[3]=$false B[4]=$false B[5]=$true B[6]=$false Y=$procmux$1231_CMP
|
||
|
|
.cname $procmux$1231_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$true B[1]=$false B[2]=$false B[3]=$false B[4]=$false B[5]=$true B[6]=$false Y=$procmux$1232_CMP
|
||
|
|
.cname $procmux$1232_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$false B[1]=$false B[2]=$false B[3]=$false B[4]=$false B[5]=$true B[6]=$false Y=$procmux$1233_CMP
|
||
|
|
.cname $procmux$1233_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$true B[1]=$true B[2]=$true B[3]=$true B[4]=$true B[5]=$false B[6]=$false Y=$procmux$1234_CMP
|
||
|
|
.cname $procmux$1234_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$false B[1]=$true B[2]=$true B[3]=$true B[4]=$true B[5]=$false B[6]=$false Y=$procmux$1235_CMP
|
||
|
|
.cname $procmux$1235_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$true B[1]=$false B[2]=$true B[3]=$true B[4]=$true B[5]=$false B[6]=$false Y=$procmux$1236_CMP
|
||
|
|
.cname $procmux$1236_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$false B[1]=$false B[2]=$true B[3]=$true B[4]=$true B[5]=$false B[6]=$false Y=$procmux$1237_CMP
|
||
|
|
.cname $procmux$1237_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$true B[1]=$true B[2]=$false B[3]=$true B[4]=$true B[5]=$false B[6]=$false Y=$procmux$1238_CMP
|
||
|
|
.cname $procmux$1238_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$false B[1]=$true B[2]=$false B[3]=$true B[4]=$true B[5]=$false B[6]=$false Y=$procmux$1239_CMP
|
||
|
|
.cname $procmux$1239_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$true B[1]=$false B[2]=$false B[3]=$true B[4]=$false B[5]=$true B[6]=$false Y=$procmux$123_CMP
|
||
|
|
.cname $procmux$123_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$true B[1]=$false B[2]=$false B[3]=$true B[4]=$true B[5]=$false B[6]=$false Y=$procmux$1240_CMP
|
||
|
|
.cname $procmux$1240_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$false B[1]=$false B[2]=$false B[3]=$true B[4]=$true B[5]=$false B[6]=$false Y=$procmux$1241_CMP
|
||
|
|
.cname $procmux$1241_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$true B[1]=$true B[2]=$true B[3]=$false B[4]=$true B[5]=$false B[6]=$false Y=$procmux$1242_CMP
|
||
|
|
.cname $procmux$1242_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$false B[1]=$true B[2]=$true B[3]=$false B[4]=$true B[5]=$false B[6]=$false Y=$procmux$1243_CMP
|
||
|
|
.cname $procmux$1243_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$true B[1]=$false B[2]=$true B[3]=$false B[4]=$true B[5]=$false B[6]=$false Y=$procmux$1244_CMP
|
||
|
|
.cname $procmux$1244_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$false B[1]=$false B[2]=$true B[3]=$false B[4]=$true B[5]=$false B[6]=$false Y=$procmux$1245_CMP
|
||
|
|
.cname $procmux$1245_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$true B[1]=$true B[2]=$false B[3]=$false B[4]=$true B[5]=$false B[6]=$false Y=$procmux$1246_CMP
|
||
|
|
.cname $procmux$1246_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$false B[1]=$true B[2]=$false B[3]=$false B[4]=$true B[5]=$false B[6]=$false Y=$procmux$1247_CMP
|
||
|
|
.cname $procmux$1247_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$true B[1]=$false B[2]=$false B[3]=$false B[4]=$true B[5]=$false B[6]=$false Y=$procmux$1248_CMP
|
||
|
|
.cname $procmux$1248_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$false B[1]=$false B[2]=$false B[3]=$false B[4]=$true B[5]=$false B[6]=$false Y=$procmux$1249_CMP
|
||
|
|
.cname $procmux$1249_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$false B[1]=$false B[2]=$false B[3]=$true B[4]=$false B[5]=$true B[6]=$false Y=$procmux$124_CMP
|
||
|
|
.cname $procmux$124_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$true B[1]=$false B[2]=$false B[3]=$false B[4]=$false B[5]=$false B[6]=$false Y=$procmux$1250_CMP
|
||
|
|
.cname $procmux$1250_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $mux A[0]=$procmux$1185_Y[0] A[1]=$procmux$1185_Y[1] A[2]=$procmux$1185_Y[2] A[3]=$procmux$1185_Y[3] A[4]=$procmux$1185_Y[4] A[5]=$procmux$1185_Y[5] A[6]=$procmux$1185_Y[6] A[7]=$procmux$1185_Y[7] A[8]=$procmux$1185_Y[8] A[9]=$procmux$1185_Y[9] A[10]=$procmux$1185_Y[10] A[11]=$procmux$1185_Y[11] A[12]=$procmux$1185_Y[12] A[13]=$procmux$1185_Y[13] A[14]=$procmux$1185_Y[14] A[15]=$procmux$1185_Y[15] A[16]=$procmux$1185_Y[16] A[17]=$procmux$1185_Y[17] A[18]=$procmux$1185_Y[18] A[19]=$procmux$1185_Y[19] A[20]=$procmux$1185_Y[20] A[21]=$procmux$1185_Y[21] A[22]=$procmux$1185_Y[22] A[23]=$procmux$1185_Y[23] A[24]=$procmux$1185_Y[24] A[25]=$procmux$1185_Y[25] A[26]=$procmux$1185_Y[26] A[27]=$procmux$1185_Y[27] A[28]=$procmux$1185_Y[28] A[29]=$procmux$1185_Y[29] A[30]=$procmux$1185_Y[30] A[31]=$procmux$1185_Y[31] B[0]=$false B[1]=$false B[2]=$false B[3]=$false B[4]=$false B[5]=$false B[6]=$false B[7]=$false B[8]=$false B[9]=$false B[10]=$false B[11]=$false B[12]=$false B[13]=$false B[14]=$false B[15]=$false B[16]=$false B[17]=$false B[18]=$false B[19]=$false B[20]=$false B[21]=$false B[22]=$false B[23]=$false B[24]=$false B[25]=$false B[26]=$false B[27]=$false B[28]=$false B[29]=$false B[30]=$false B[31]=$false S=$procmux$1253_CMP Y[0]=$procmux$1252_Y[0] Y[1]=$procmux$1252_Y[1] Y[2]=$procmux$1252_Y[2] Y[3]=$procmux$1252_Y[3] Y[4]=$procmux$1252_Y[4] Y[5]=$procmux$1252_Y[5] Y[6]=$procmux$1252_Y[6] Y[7]=$procmux$1252_Y[7] Y[8]=$procmux$1252_Y[8] Y[9]=$procmux$1252_Y[9] Y[10]=$procmux$1252_Y[10] Y[11]=$procmux$1252_Y[11] Y[12]=$procmux$1252_Y[12] Y[13]=$procmux$1252_Y[13] Y[14]=$procmux$1252_Y[14] Y[15]=$procmux$1252_Y[15] Y[16]=$procmux$1252_Y[16] Y[17]=$procmux$1252_Y[17] Y[18]=$procmux$1252_Y[18] Y[19]=$procmux$1252_Y[19] Y[20]=$procmux$1252_Y[20] Y[21]=$procmux$1252_Y[21] Y[22]=$procmux$1252_Y[22] Y[23]=$procmux$1252_Y[23] Y[24]=$procmux$1252_Y[24] Y[25]=$procmux$1252_Y[25] Y[26]=$procmux$1252_Y[26] Y[27]=$procmux$1252_Y[27] Y[28]=$procmux$1252_Y[28] Y[29]=$procmux$1252_Y[29] Y[30]=$procmux$1252_Y[30] Y[31]=$procmux$1252_Y[31]
|
||
|
|
.cname $procmux$1252
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:150"
|
||
|
|
.param WIDTH 00000000000000000000000000100000
|
||
|
|
.subckt $pmux A[0]=W0[0] A[1]=W0[1] A[2]=W0[2] A[3]=W0[3] A[4]=W0[4] A[5]=W0[5] A[6]=W0[6] A[7]=W0[7] A[8]=W0[8] A[9]=W0[9] A[10]=W0[10] A[11]=W0[11] A[12]=W0[12] A[13]=W0[13] A[14]=W0[14] A[15]=W0[15] A[16]=W0[16] A[17]=W0[17] A[18]=W0[18] A[19]=W0[19] A[20]=W0[20] A[21]=W0[21] A[22]=W0[22] A[23]=W0[23] A[24]=W0[24] A[25]=W0[25] A[26]=W0[26] A[27]=W0[27] A[28]=W0[28] A[29]=W0[29] A[30]=W0[30] A[31]=W0[31] B[0]=W1[0] B[1]=W1[1] B[2]=W1[2] B[3]=W1[3] B[4]=W1[4] B[5]=W1[5] B[6]=W1[6] B[7]=W1[7] B[8]=W1[8] B[9]=W1[9] B[10]=W1[10] B[11]=W1[11] B[12]=W1[12] B[13]=W1[13] B[14]=W1[14] B[15]=W1[15] B[16]=W1[16] B[17]=W1[17] B[18]=W1[18] B[19]=W1[19] B[20]=W1[20] B[21]=W1[21] B[22]=W1[22] B[23]=W1[23] B[24]=W1[24] B[25]=W1[25] B[26]=W1[26] B[27]=W1[27] B[28]=W1[28] B[29]=W1[29] B[30]=W1[30] B[31]=W1[31] B[32]=W1[0] B[33]=W1[1] B[34]=W1[2] B[35]=W1[3] B[36]=W1[4] B[37]=W1[5] B[38]=W1[6] B[39]=W1[7] B[40]=W1[8] B[41]=W1[9] B[42]=W1[10] B[43]=W1[11] B[44]=W1[12] B[45]=W1[13] B[46]=W1[14] B[47]=W1[15] B[48]=W1[16] B[49]=W1[17] B[50]=W1[18] B[51]=W1[19] B[52]=W1[20] B[53]=W1[21] B[54]=W1[22] B[55]=W1[23] B[56]=W1[24] B[57]=W1[25] B[58]=W1[26] B[59]=W1[27] B[60]=W1[28] B[61]=W1[29] B[62]=W1[30] B[63]=W1[31] B[64]=W1[0] B[65]=W1[1] B[66]=W1[2] B[67]=W1[3] B[68]=W1[4] B[69]=W1[5] B[70]=W1[6] B[71]=W1[7] B[72]=W1[8] B[73]=W1[9] B[74]=W1[10] B[75]=W1[11] B[76]=W1[12] B[77]=W1[13] B[78]=W1[14] B[79]=W1[15] B[80]=W1[16] B[81]=W1[17] B[82]=W1[18] B[83]=W1[19] B[84]=W1[20] B[85]=W1[21] B[86]=W1[22] B[87]=W1[23] B[88]=W1[24] B[89]=W1[25] B[90]=W1[26] B[91]=W1[27] B[92]=W1[28] B[93]=W1[29] B[94]=W1[30] B[95]=W1[31] B[96]=W1[0] B[97]=W1[1] B[98]=W1[2] B[99]=W1[3] B[100]=W1[4] B[101]=W1[5] B[102]=W1[6] B[103]=W1[7] B[104]=W1[8] B[105]=W1[9] B[106]=W1[10] B[107]=W1[11] B[108]=W1[12] B[109]=W1[13] B[110]=W1[14] B[111]=W1[15] B[112]=W1[16] B[113]=W1[17] B[114]=W1[18] B[115]=W1[19] B[116]=W1[20] B[117]=W1[21] B[118]=W1[22] B[119]=W1[23] B[120]=W1[24] B[121]=W1[25] B[122]=W1[26] B[123]=W1[27] B[124]=W1[28] B[125]=W1[29] B[126]=W1[30] B[127]=W1[31] B[128]=W1[0] B[129]=W1[1] B[130]=W1[2] B[131]=W1[3] B[132]=W1[4] B[133]=W1[5] B[134]=W1[6] B[135]=W1[7] B[136]=W1[8] B[137]=W1[9] B[138]=W1[10] B[139]=W1[11] B[140]=W1[12] B[141]=W1[13] B[142]=W1[14] B[143]=W1[15] B[144]=W1[16] B[145]=W1[17] B[146]=W1[18] B[147]=W1[19] B[148]=W1[20] B[149]=W1[21] B[150]=W1[22] B[151]=W1[23] B[152]=W1[24] B[153]=W1[25] B[154]=W1[26] B[155]=W1[27] B[156]=W1[28] B[157]=W1[29] B[158]=W1[30] B[159]=W1[31] B[160]=W1[0] B[161]=W1[1] B[162]=W1[2] B[163]=W1[3] B[164]=W1[4] B[165]=W1[5] B[166]=W1[6] B[167]=W1[7] B[168]=W1[8] B[169]=W1[9] B[170]=W1[10] B[171]=W1[11] B[172]=W1[12] B[173]=W1[13] B[174]=W1[14] B[175]=W1[15] B[176]=W1[16] B[177]=W1[17] B[178]=W1[18] B[179]=W1[19] B[180]=W1[20] B[181]=W1[21] B[182]=W1[22] B[183]=W1[23] B[184]=W1[24] B[185]=W1[25] B[186]=W1[26] B[187]=W1[27] B[188]=W1[28] B[189]=W1[29] B[190]=W1[30] B[191]=W1[31] B[192]=W1[0] B[193]=W1[1] B[194]=W1[2] B[195]=W1[3] B[196]=W1[4] B[197]=W1[5] B[198]=W1[6] B[199]=W1[7] B[200]=W1[8] B[201]=W1[9] B[202]=W1[10] B[203]=W1[11] B[204]=W1[12] B[205]=W1[13] B[206]=W1[14] B[207]=W1[15] B[208]=W1[16] B[209]=W1[17] B[210]=W1[18] B[211]=W1[19] B[212]=W1[20] B[213]=W1[21] B[214]=W1[22] B[215]=W1[23] B[216]=W1[24] B[217]=W1[25] B[218]=W1[26] B[219]=W1[27] B[220]=W1[28] B[221]=W1[29] B[222]=W1[30] B[223]=W1[31] B[224]=W1[0] B[225]=W1[1] B[226]=W1[2] B[227]=W1[3] B[228]=W1[4] B[229]=W1[5] B[230]=W1[6] B[231]=W1[7] B[232]=W1[8] B[233]=W1[9] B[234]=W1[10] B[235]=W1[11] B[236]=W1[12] B[237]=W1[13] B[238]=W1[14] B[239]=W1[15] B[240]=W1[16] B[241]=W1[17] B[242]=W1[18] B[243]=W1[19] B[244]=W1[20] B[245]=W1[21] B[246]=W1[22] B[247]=W1[23] B[248]=W1[24] B[249]=W1[25] B[250]=W1[26] B[251]=W1[27] B[252]=W1[28] B[253]=W1[29] B[254]=W1[30] B[255]=W1[31] B[256]=W1[0] B[257]=W1[1] B[258]=W1[2] B[259]=W1[3] B[260]=W1[4] B[261]=W1[5] B[262]=W1[6] B[263]=W1[7] B[264]=W1[8] B[265]=W1[9] B[266]=W1[10] B[267]=W1[11] B[268]=W1[12] B[269]=W1[13] B[270]=W1[14] B[271]=W1[15] B[272]=W1[16] B[273]=W1[17] B[274]=W1[18] B[275]=W1[19] B[276]=W1[20] B[277]=
|
||
|
|
.cname $procmux$1256
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param S_WIDTH 00000000000000000000000001000001
|
||
|
|
.param WIDTH 00000000000000000000000000100000
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$true B[1]=$true B[2]=$true B[3]=$true B[4]=$false B[5]=$false B[6]=$true Y=$procmux$1257_CMP
|
||
|
|
.cname $procmux$1257_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$false B[1]=$true B[2]=$true B[3]=$true B[4]=$false B[5]=$false B[6]=$true Y=$procmux$1258_CMP
|
||
|
|
.cname $procmux$1258_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$true B[1]=$false B[2]=$true B[3]=$true B[4]=$false B[5]=$false B[6]=$true Y=$procmux$1259_CMP
|
||
|
|
.cname $procmux$1259_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$true B[1]=$true B[2]=$true B[3]=$false B[4]=$false B[5]=$true B[6]=$false Y=$procmux$125_CMP
|
||
|
|
.cname $procmux$125_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$false B[1]=$false B[2]=$true B[3]=$true B[4]=$false B[5]=$false B[6]=$true Y=$procmux$1260_CMP
|
||
|
|
.cname $procmux$1260_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$true B[1]=$true B[2]=$false B[3]=$true B[4]=$false B[5]=$false B[6]=$true Y=$procmux$1261_CMP
|
||
|
|
.cname $procmux$1261_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$false B[1]=$true B[2]=$false B[3]=$true B[4]=$false B[5]=$false B[6]=$true Y=$procmux$1262_CMP
|
||
|
|
.cname $procmux$1262_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$true B[1]=$false B[2]=$false B[3]=$true B[4]=$false B[5]=$false B[6]=$true Y=$procmux$1263_CMP
|
||
|
|
.cname $procmux$1263_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$false B[1]=$false B[2]=$false B[3]=$true B[4]=$false B[5]=$false B[6]=$true Y=$procmux$1264_CMP
|
||
|
|
.cname $procmux$1264_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$true B[1]=$true B[2]=$true B[3]=$false B[4]=$false B[5]=$false B[6]=$true Y=$procmux$1265_CMP
|
||
|
|
.cname $procmux$1265_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$false B[1]=$true B[2]=$true B[3]=$false B[4]=$false B[5]=$false B[6]=$true Y=$procmux$1266_CMP
|
||
|
|
.cname $procmux$1266_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$true B[1]=$false B[2]=$true B[3]=$false B[4]=$false B[5]=$false B[6]=$true Y=$procmux$1267_CMP
|
||
|
|
.cname $procmux$1267_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$false B[1]=$false B[2]=$true B[3]=$false B[4]=$false B[5]=$false B[6]=$true Y=$procmux$1268_CMP
|
||
|
|
.cname $procmux$1268_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$true B[1]=$true B[2]=$false B[3]=$false B[4]=$false B[5]=$false B[6]=$true Y=$procmux$1269_CMP
|
||
|
|
.cname $procmux$1269_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$false B[1]=$true B[2]=$true B[3]=$false B[4]=$false B[5]=$true B[6]=$false Y=$procmux$126_CMP
|
||
|
|
.cname $procmux$126_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$false B[1]=$true B[2]=$false B[3]=$false B[4]=$false B[5]=$false B[6]=$true Y=$procmux$1270_CMP
|
||
|
|
.cname $procmux$1270_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$true B[1]=$false B[2]=$false B[3]=$false B[4]=$false B[5]=$false B[6]=$true Y=$procmux$1271_CMP
|
||
|
|
.cname $procmux$1271_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$false B[1]=$false B[2]=$false B[3]=$false B[4]=$false B[5]=$false B[6]=$true Y=$procmux$1272_CMP
|
||
|
|
.cname $procmux$1272_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$true B[1]=$true B[2]=$true B[3]=$true B[4]=$true B[5]=$true B[6]=$false Y=$procmux$1273_CMP
|
||
|
|
.cname $procmux$1273_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$false B[1]=$true B[2]=$true B[3]=$true B[4]=$true B[5]=$true B[6]=$false Y=$procmux$1274_CMP
|
||
|
|
.cname $procmux$1274_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$true B[1]=$false B[2]=$true B[3]=$true B[4]=$true B[5]=$true B[6]=$false Y=$procmux$1275_CMP
|
||
|
|
.cname $procmux$1275_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$false B[1]=$false B[2]=$true B[3]=$true B[4]=$true B[5]=$true B[6]=$false Y=$procmux$1276_CMP
|
||
|
|
.cname $procmux$1276_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$true B[1]=$true B[2]=$false B[3]=$true B[4]=$true B[5]=$true B[6]=$false Y=$procmux$1277_CMP
|
||
|
|
.cname $procmux$1277_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$false B[1]=$true B[2]=$false B[3]=$true B[4]=$true B[5]=$true B[6]=$false Y=$procmux$1278_CMP
|
||
|
|
.cname $procmux$1278_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$true B[1]=$false B[2]=$false B[3]=$true B[4]=$true B[5]=$true B[6]=$false Y=$procmux$1279_CMP
|
||
|
|
.cname $procmux$1279_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$true B[1]=$false B[2]=$true B[3]=$false B[4]=$false B[5]=$true B[6]=$false Y=$procmux$127_CMP
|
||
|
|
.cname $procmux$127_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$false B[1]=$false B[2]=$false B[3]=$true B[4]=$true B[5]=$true B[6]=$false Y=$procmux$1280_CMP
|
||
|
|
.cname $procmux$1280_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$true B[1]=$true B[2]=$true B[3]=$false B[4]=$true B[5]=$true B[6]=$false Y=$procmux$1281_CMP
|
||
|
|
.cname $procmux$1281_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$false B[1]=$true B[2]=$true B[3]=$false B[4]=$true B[5]=$true B[6]=$false Y=$procmux$1282_CMP
|
||
|
|
.cname $procmux$1282_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$true B[1]=$false B[2]=$true B[3]=$false B[4]=$true B[5]=$true B[6]=$false Y=$procmux$1283_CMP
|
||
|
|
.cname $procmux$1283_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$false B[1]=$false B[2]=$true B[3]=$false B[4]=$true B[5]=$true B[6]=$false Y=$procmux$1284_CMP
|
||
|
|
.cname $procmux$1284_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$true B[1]=$true B[2]=$false B[3]=$false B[4]=$true B[5]=$true B[6]=$false Y=$procmux$1285_CMP
|
||
|
|
.cname $procmux$1285_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$false B[1]=$true B[2]=$false B[3]=$false B[4]=$true B[5]=$true B[6]=$false Y=$procmux$1286_CMP
|
||
|
|
.cname $procmux$1286_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$true B[1]=$false B[2]=$false B[3]=$false B[4]=$true B[5]=$true B[6]=$false Y=$procmux$1287_CMP
|
||
|
|
.cname $procmux$1287_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$false B[1]=$false B[2]=$false B[3]=$false B[4]=$true B[5]=$true B[6]=$false Y=$procmux$1288_CMP
|
||
|
|
.cname $procmux$1288_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$true B[1]=$true B[2]=$true B[3]=$true B[4]=$false B[5]=$true B[6]=$false Y=$procmux$1289_CMP
|
||
|
|
.cname $procmux$1289_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$false B[1]=$false B[2]=$true B[3]=$false B[4]=$false B[5]=$true B[6]=$false Y=$procmux$128_CMP
|
||
|
|
.cname $procmux$128_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$false B[1]=$true B[2]=$true B[3]=$true B[4]=$false B[5]=$true B[6]=$false Y=$procmux$1290_CMP
|
||
|
|
.cname $procmux$1290_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$true B[1]=$false B[2]=$true B[3]=$true B[4]=$false B[5]=$true B[6]=$false Y=$procmux$1291_CMP
|
||
|
|
.cname $procmux$1291_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$false B[1]=$false B[2]=$true B[3]=$true B[4]=$false B[5]=$true B[6]=$false Y=$procmux$1292_CMP
|
||
|
|
.cname $procmux$1292_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$true B[1]=$true B[2]=$false B[3]=$true B[4]=$false B[5]=$true B[6]=$false Y=$procmux$1293_CMP
|
||
|
|
.cname $procmux$1293_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$false B[1]=$true B[2]=$false B[3]=$true B[4]=$false B[5]=$true B[6]=$false Y=$procmux$1294_CMP
|
||
|
|
.cname $procmux$1294_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$true B[1]=$false B[2]=$false B[3]=$true B[4]=$false B[5]=$true B[6]=$false Y=$procmux$1295_CMP
|
||
|
|
.cname $procmux$1295_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$false B[1]=$false B[2]=$false B[3]=$true B[4]=$false B[5]=$true B[6]=$false Y=$procmux$1296_CMP
|
||
|
|
.cname $procmux$1296_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$true B[1]=$true B[2]=$true B[3]=$false B[4]=$false B[5]=$true B[6]=$false Y=$procmux$1297_CMP
|
||
|
|
.cname $procmux$1297_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$false B[1]=$true B[2]=$true B[3]=$false B[4]=$false B[5]=$true B[6]=$false Y=$procmux$1298_CMP
|
||
|
|
.cname $procmux$1298_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$true B[1]=$false B[2]=$true B[3]=$false B[4]=$false B[5]=$true B[6]=$false Y=$procmux$1299_CMP
|
||
|
|
.cname $procmux$1299_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$true B[1]=$true B[2]=$false B[3]=$false B[4]=$false B[5]=$true B[6]=$false Y=$procmux$129_CMP
|
||
|
|
.cname $procmux$129_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$false B[1]=$false B[2]=$true B[3]=$false B[4]=$false B[5]=$true B[6]=$false Y=$procmux$1300_CMP
|
||
|
|
.cname $procmux$1300_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$true B[1]=$true B[2]=$false B[3]=$false B[4]=$false B[5]=$true B[6]=$false Y=$procmux$1301_CMP
|
||
|
|
.cname $procmux$1301_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$false B[1]=$true B[2]=$false B[3]=$false B[4]=$false B[5]=$true B[6]=$false Y=$procmux$1302_CMP
|
||
|
|
.cname $procmux$1302_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$true B[1]=$false B[2]=$false B[3]=$false B[4]=$false B[5]=$true B[6]=$false Y=$procmux$1303_CMP
|
||
|
|
.cname $procmux$1303_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$false B[1]=$false B[2]=$false B[3]=$false B[4]=$false B[5]=$true B[6]=$false Y=$procmux$1304_CMP
|
||
|
|
.cname $procmux$1304_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$true B[1]=$true B[2]=$true B[3]=$true B[4]=$true B[5]=$false B[6]=$false Y=$procmux$1305_CMP
|
||
|
|
.cname $procmux$1305_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$false B[1]=$true B[2]=$true B[3]=$true B[4]=$true B[5]=$false B[6]=$false Y=$procmux$1306_CMP
|
||
|
|
.cname $procmux$1306_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$true B[1]=$false B[2]=$true B[3]=$true B[4]=$true B[5]=$false B[6]=$false Y=$procmux$1307_CMP
|
||
|
|
.cname $procmux$1307_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$false B[1]=$false B[2]=$true B[3]=$true B[4]=$true B[5]=$false B[6]=$false Y=$procmux$1308_CMP
|
||
|
|
.cname $procmux$1308_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$true B[1]=$true B[2]=$false B[3]=$true B[4]=$true B[5]=$false B[6]=$false Y=$procmux$1309_CMP
|
||
|
|
.cname $procmux$1309_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$false B[1]=$true B[2]=$false B[3]=$false B[4]=$false B[5]=$true B[6]=$false Y=$procmux$130_CMP
|
||
|
|
.cname $procmux$130_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$false B[1]=$true B[2]=$false B[3]=$true B[4]=$true B[5]=$false B[6]=$false Y=$procmux$1310_CMP
|
||
|
|
.cname $procmux$1310_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$true B[1]=$false B[2]=$false B[3]=$true B[4]=$true B[5]=$false B[6]=$false Y=$procmux$1311_CMP
|
||
|
|
.cname $procmux$1311_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$false B[1]=$false B[2]=$false B[3]=$true B[4]=$true B[5]=$false B[6]=$false Y=$procmux$1312_CMP
|
||
|
|
.cname $procmux$1312_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$true B[1]=$true B[2]=$true B[3]=$false B[4]=$true B[5]=$false B[6]=$false Y=$procmux$1313_CMP
|
||
|
|
.cname $procmux$1313_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$false B[1]=$true B[2]=$true B[3]=$false B[4]=$true B[5]=$false B[6]=$false Y=$procmux$1314_CMP
|
||
|
|
.cname $procmux$1314_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$true B[1]=$false B[2]=$true B[3]=$false B[4]=$true B[5]=$false B[6]=$false Y=$procmux$1315_CMP
|
||
|
|
.cname $procmux$1315_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$false B[1]=$false B[2]=$true B[3]=$false B[4]=$true B[5]=$false B[6]=$false Y=$procmux$1316_CMP
|
||
|
|
.cname $procmux$1316_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$true B[1]=$true B[2]=$false B[3]=$false B[4]=$true B[5]=$false B[6]=$false Y=$procmux$1317_CMP
|
||
|
|
.cname $procmux$1317_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$false B[1]=$true B[2]=$false B[3]=$false B[4]=$true B[5]=$false B[6]=$false Y=$procmux$1318_CMP
|
||
|
|
.cname $procmux$1318_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$true B[1]=$false B[2]=$false B[3]=$false B[4]=$true B[5]=$false B[6]=$false Y=$procmux$1319_CMP
|
||
|
|
.cname $procmux$1319_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$true B[1]=$false B[2]=$false B[3]=$false B[4]=$false B[5]=$true B[6]=$false Y=$procmux$131_CMP
|
||
|
|
.cname $procmux$131_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$false B[1]=$false B[2]=$false B[3]=$false B[4]=$true B[5]=$false B[6]=$false Y=$procmux$1320_CMP
|
||
|
|
.cname $procmux$1320_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $mux A[0]=W0[0] A[1]=W0[1] A[2]=W0[2] A[3]=W0[3] A[4]=W0[4] A[5]=W0[5] A[6]=W0[6] A[7]=W0[7] A[8]=W0[8] A[9]=W0[9] A[10]=W0[10] A[11]=W0[11] A[12]=W0[12] A[13]=W0[13] A[14]=W0[14] A[15]=W0[15] A[16]=W0[16] A[17]=W0[17] A[18]=W0[18] A[19]=W0[19] A[20]=W0[20] A[21]=W0[21] A[22]=W0[22] A[23]=W0[23] A[24]=W0[24] A[25]=W0[25] A[26]=W0[26] A[27]=W0[27] A[28]=W0[28] A[29]=W0[29] A[30]=W0[30] A[31]=W0[31] B[0]=text_i[0] B[1]=text_i[1] B[2]=text_i[2] B[3]=text_i[3] B[4]=text_i[4] B[5]=text_i[5] B[6]=text_i[6] B[7]=text_i[7] B[8]=text_i[8] B[9]=text_i[9] B[10]=text_i[10] B[11]=text_i[11] B[12]=text_i[12] B[13]=text_i[13] B[14]=text_i[14] B[15]=text_i[15] B[16]=text_i[16] B[17]=text_i[17] B[18]=text_i[18] B[19]=text_i[19] B[20]=text_i[20] B[21]=text_i[21] B[22]=text_i[22] B[23]=text_i[23] B[24]=text_i[24] B[25]=text_i[25] B[26]=text_i[26] B[27]=text_i[27] B[28]=text_i[28] B[29]=text_i[29] B[30]=text_i[30] B[31]=text_i[31] S=$procmux$1323_CMP Y[0]=$procmux$1322_Y[0] Y[1]=$procmux$1322_Y[1] Y[2]=$procmux$1322_Y[2] Y[3]=$procmux$1322_Y[3] Y[4]=$procmux$1322_Y[4] Y[5]=$procmux$1322_Y[5] Y[6]=$procmux$1322_Y[6] Y[7]=$procmux$1322_Y[7] Y[8]=$procmux$1322_Y[8] Y[9]=$procmux$1322_Y[9] Y[10]=$procmux$1322_Y[10] Y[11]=$procmux$1322_Y[11] Y[12]=$procmux$1322_Y[12] Y[13]=$procmux$1322_Y[13] Y[14]=$procmux$1322_Y[14] Y[15]=$procmux$1322_Y[15] Y[16]=$procmux$1322_Y[16] Y[17]=$procmux$1322_Y[17] Y[18]=$procmux$1322_Y[18] Y[19]=$procmux$1322_Y[19] Y[20]=$procmux$1322_Y[20] Y[21]=$procmux$1322_Y[21] Y[22]=$procmux$1322_Y[22] Y[23]=$procmux$1322_Y[23] Y[24]=$procmux$1322_Y[24] Y[25]=$procmux$1322_Y[25] Y[26]=$procmux$1322_Y[26] Y[27]=$procmux$1322_Y[27] Y[28]=$procmux$1322_Y[28] Y[29]=$procmux$1322_Y[29] Y[30]=$procmux$1322_Y[30] Y[31]=$procmux$1322_Y[31]
|
||
|
|
.cname $procmux$1322
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:191"
|
||
|
|
.param WIDTH 00000000000000000000000000100000
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$false B[1]=$false B[2]=$false B[3]=$false B[4]=$false B[5]=$false B[6]=$false Y=$procmux$1324_CMP
|
||
|
|
.cname $procmux$1324_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $mux A[0]=$procmux$1256_Y[0] A[1]=$procmux$1256_Y[1] A[2]=$procmux$1256_Y[2] A[3]=$procmux$1256_Y[3] A[4]=$procmux$1256_Y[4] A[5]=$procmux$1256_Y[5] A[6]=$procmux$1256_Y[6] A[7]=$procmux$1256_Y[7] A[8]=$procmux$1256_Y[8] A[9]=$procmux$1256_Y[9] A[10]=$procmux$1256_Y[10] A[11]=$procmux$1256_Y[11] A[12]=$procmux$1256_Y[12] A[13]=$procmux$1256_Y[13] A[14]=$procmux$1256_Y[14] A[15]=$procmux$1256_Y[15] A[16]=$procmux$1256_Y[16] A[17]=$procmux$1256_Y[17] A[18]=$procmux$1256_Y[18] A[19]=$procmux$1256_Y[19] A[20]=$procmux$1256_Y[20] A[21]=$procmux$1256_Y[21] A[22]=$procmux$1256_Y[22] A[23]=$procmux$1256_Y[23] A[24]=$procmux$1256_Y[24] A[25]=$procmux$1256_Y[25] A[26]=$procmux$1256_Y[26] A[27]=$procmux$1256_Y[27] A[28]=$procmux$1256_Y[28] A[29]=$procmux$1256_Y[29] A[30]=$procmux$1256_Y[30] A[31]=$procmux$1256_Y[31] B[0]=$false B[1]=$false B[2]=$false B[3]=$false B[4]=$false B[5]=$false B[6]=$false B[7]=$false B[8]=$false B[9]=$false B[10]=$false B[11]=$false B[12]=$false B[13]=$false B[14]=$false B[15]=$false B[16]=$false B[17]=$false B[18]=$false B[19]=$false B[20]=$false B[21]=$false B[22]=$false B[23]=$false B[24]=$false B[25]=$false B[26]=$false B[27]=$false B[28]=$false B[29]=$false B[30]=$false B[31]=$false S=$procmux$1327_CMP Y[0]=$procmux$1326_Y[0] Y[1]=$procmux$1326_Y[1] Y[2]=$procmux$1326_Y[2] Y[3]=$procmux$1326_Y[3] Y[4]=$procmux$1326_Y[4] Y[5]=$procmux$1326_Y[5] Y[6]=$procmux$1326_Y[6] Y[7]=$procmux$1326_Y[7] Y[8]=$procmux$1326_Y[8] Y[9]=$procmux$1326_Y[9] Y[10]=$procmux$1326_Y[10] Y[11]=$procmux$1326_Y[11] Y[12]=$procmux$1326_Y[12] Y[13]=$procmux$1326_Y[13] Y[14]=$procmux$1326_Y[14] Y[15]=$procmux$1326_Y[15] Y[16]=$procmux$1326_Y[16] Y[17]=$procmux$1326_Y[17] Y[18]=$procmux$1326_Y[18] Y[19]=$procmux$1326_Y[19] Y[20]=$procmux$1326_Y[20] Y[21]=$procmux$1326_Y[21] Y[22]=$procmux$1326_Y[22] Y[23]=$procmux$1326_Y[23] Y[24]=$procmux$1326_Y[24] Y[25]=$procmux$1326_Y[25] Y[26]=$procmux$1326_Y[26] Y[27]=$procmux$1326_Y[27] Y[28]=$procmux$1326_Y[28] Y[29]=$procmux$1326_Y[29] Y[30]=$procmux$1326_Y[30] Y[31]=$procmux$1326_Y[31]
|
||
|
|
.cname $procmux$1326
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:150"
|
||
|
|
.param WIDTH 00000000000000000000000000100000
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$false B[1]=$false B[2]=$false B[3]=$false B[4]=$false B[5]=$true B[6]=$false Y=$procmux$132_CMP
|
||
|
|
.cname $procmux$132_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$true B[1]=$true B[2]=$true B[3]=$true B[4]=$true B[5]=$false B[6]=$false Y=$procmux$133_CMP
|
||
|
|
.cname $procmux$133_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$false B[1]=$true B[2]=$true B[3]=$true B[4]=$true B[5]=$false B[6]=$false Y=$procmux$134_CMP
|
||
|
|
.cname $procmux$134_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$true B[1]=$false B[2]=$true B[3]=$true B[4]=$true B[5]=$false B[6]=$false Y=$procmux$135_CMP
|
||
|
|
.cname $procmux$135_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$false B[1]=$false B[2]=$true B[3]=$true B[4]=$true B[5]=$false B[6]=$false Y=$procmux$136_CMP
|
||
|
|
.cname $procmux$136_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$true B[1]=$true B[2]=$false B[3]=$true B[4]=$true B[5]=$false B[6]=$false Y=$procmux$137_CMP
|
||
|
|
.cname $procmux$137_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$false B[1]=$true B[2]=$false B[3]=$true B[4]=$true B[5]=$false B[6]=$false Y=$procmux$138_CMP
|
||
|
|
.cname $procmux$138_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$true B[1]=$false B[2]=$false B[3]=$true B[4]=$true B[5]=$false B[6]=$false Y=$procmux$139_CMP
|
||
|
|
.cname $procmux$139_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$false B[1]=$false B[2]=$false B[3]=$true B[4]=$true B[5]=$false B[6]=$false Y=$procmux$140_CMP
|
||
|
|
.cname $procmux$140_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $pmux A[0]=H4[0] A[1]=H4[1] A[2]=H4[2] A[3]=H4[3] A[4]=H4[4] A[5]=H4[5] A[6]=H4[6] A[7]=H4[7] A[8]=H4[8] A[9]=H4[9] A[10]=H4[10] A[11]=H4[11] A[12]=H4[12] A[13]=H4[13] A[14]=H4[14] A[15]=H4[15] A[16]=H4[16] A[17]=H4[17] A[18]=H4[18] A[19]=H4[19] A[20]=H4[20] A[21]=H4[21] A[22]=H4[22] A[23]=H4[23] A[24]=H4[24] A[25]=H4[25] A[26]=H4[26] A[27]=H4[27] A[28]=H4[28] A[29]=H4[29] A[30]=H4[30] A[31]=H4[31] B[0]=E[0] B[1]=E[1] B[2]=E[2] B[3]=E[3] B[4]=E[4] B[5]=E[5] B[6]=E[6] B[7]=E[7] B[8]=E[8] B[9]=E[9] B[10]=E[10] B[11]=E[11] B[12]=E[12] B[13]=E[13] B[14]=E[14] B[15]=E[15] B[16]=E[16] B[17]=E[17] B[18]=E[18] B[19]=E[19] B[20]=E[20] B[21]=E[21] B[22]=E[22] B[23]=E[23] B[24]=E[24] B[25]=E[25] B[26]=E[26] B[27]=E[27] B[28]=E[28] B[29]=E[29] B[30]=E[30] B[31]=E[31] B[32]=$false B[33]=$false B[34]=$false B[35]=$false B[36]=$true B[37]=$true B[38]=$true B[39]=$true B[40]=$true B[41]=$false B[42]=$false B[43]=$false B[44]=$false B[45]=$true B[46]=$true B[47]=$true B[48]=$false B[49]=$true B[50]=$false B[51]=$false B[52]=$true B[53]=$false B[54]=$true B[55]=$true B[56]=$true B[57]=$true B[58]=$false B[59]=$false B[60]=$false B[61]=$false B[62]=$true B[63]=$true S[0]=$procmux$1411_CMP S[1]=$procmux$1412_CMP Y[0]=$procmux$1410_Y[0] Y[1]=$procmux$1410_Y[1] Y[2]=$procmux$1410_Y[2] Y[3]=$procmux$1410_Y[3] Y[4]=$procmux$1410_Y[4] Y[5]=$procmux$1410_Y[5] Y[6]=$procmux$1410_Y[6] Y[7]=$procmux$1410_Y[7] Y[8]=$procmux$1410_Y[8] Y[9]=$procmux$1410_Y[9] Y[10]=$procmux$1410_Y[10] Y[11]=$procmux$1410_Y[11] Y[12]=$procmux$1410_Y[12] Y[13]=$procmux$1410_Y[13] Y[14]=$procmux$1410_Y[14] Y[15]=$procmux$1410_Y[15] Y[16]=$procmux$1410_Y[16] Y[17]=$procmux$1410_Y[17] Y[18]=$procmux$1410_Y[18] Y[19]=$procmux$1410_Y[19] Y[20]=$procmux$1410_Y[20] Y[21]=$procmux$1410_Y[21] Y[22]=$procmux$1410_Y[22] Y[23]=$procmux$1410_Y[23] Y[24]=$procmux$1410_Y[24] Y[25]=$procmux$1410_Y[25] Y[26]=$procmux$1410_Y[26] Y[27]=$procmux$1410_Y[27] Y[28]=$procmux$1410_Y[28] Y[29]=$procmux$1410_Y[29] Y[30]=$procmux$1410_Y[30] Y[31]=$procmux$1410_Y[31]
|
||
|
|
.cname $procmux$1410
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:198"
|
||
|
|
.param S_WIDTH 00000000000000000000000000000010
|
||
|
|
.param WIDTH 00000000000000000000000000100000
|
||
|
|
.subckt $eq A=cmd[2] B=$false Y=$procmux$1412_CMP
|
||
|
|
.cname $procmux$1412_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:198"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000001
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000001
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $mux A[0]=H4[0] A[1]=H4[1] A[2]=H4[2] A[3]=H4[3] A[4]=H4[4] A[5]=H4[5] A[6]=H4[6] A[7]=H4[7] A[8]=H4[8] A[9]=H4[9] A[10]=H4[10] A[11]=H4[11] A[12]=H4[12] A[13]=H4[13] A[14]=H4[14] A[15]=H4[15] A[16]=H4[16] A[17]=H4[17] A[18]=H4[18] A[19]=H4[19] A[20]=H4[20] A[21]=H4[21] A[22]=H4[22] A[23]=H4[23] A[24]=H4[24] A[25]=H4[25] A[26]=H4[26] A[27]=H4[27] A[28]=H4[28] A[29]=H4[29] A[30]=H4[30] A[31]=H4[31] B[0]=$procmux$1410_Y[0] B[1]=$procmux$1410_Y[1] B[2]=$procmux$1410_Y[2] B[3]=$procmux$1410_Y[3] B[4]=$procmux$1410_Y[4] B[5]=$procmux$1410_Y[5] B[6]=$procmux$1410_Y[6] B[7]=$procmux$1410_Y[7] B[8]=$procmux$1410_Y[8] B[9]=$procmux$1410_Y[9] B[10]=$procmux$1410_Y[10] B[11]=$procmux$1410_Y[11] B[12]=$procmux$1410_Y[12] B[13]=$procmux$1410_Y[13] B[14]=$procmux$1410_Y[14] B[15]=$procmux$1410_Y[15] B[16]=$procmux$1410_Y[16] B[17]=$procmux$1410_Y[17] B[18]=$procmux$1410_Y[18] B[19]=$procmux$1410_Y[19] B[20]=$procmux$1410_Y[20] B[21]=$procmux$1410_Y[21] B[22]=$procmux$1410_Y[22] B[23]=$procmux$1410_Y[23] B[24]=$procmux$1410_Y[24] B[25]=$procmux$1410_Y[25] B[26]=$procmux$1410_Y[26] B[27]=$procmux$1410_Y[27] B[28]=$procmux$1410_Y[28] B[29]=$procmux$1410_Y[29] B[30]=$procmux$1410_Y[30] B[31]=$procmux$1410_Y[31] S=$procmux$1414_CMP Y[0]=$procmux$1413_Y[0] Y[1]=$procmux$1413_Y[1] Y[2]=$procmux$1413_Y[2] Y[3]=$procmux$1413_Y[3] Y[4]=$procmux$1413_Y[4] Y[5]=$procmux$1413_Y[5] Y[6]=$procmux$1413_Y[6] Y[7]=$procmux$1413_Y[7] Y[8]=$procmux$1413_Y[8] Y[9]=$procmux$1413_Y[9] Y[10]=$procmux$1413_Y[10] Y[11]=$procmux$1413_Y[11] Y[12]=$procmux$1413_Y[12] Y[13]=$procmux$1413_Y[13] Y[14]=$procmux$1413_Y[14] Y[15]=$procmux$1413_Y[15] Y[16]=$procmux$1413_Y[16] Y[17]=$procmux$1413_Y[17] Y[18]=$procmux$1413_Y[18] Y[19]=$procmux$1413_Y[19] Y[20]=$procmux$1413_Y[20] Y[21]=$procmux$1413_Y[21] Y[22]=$procmux$1413_Y[22] Y[23]=$procmux$1413_Y[23] Y[24]=$procmux$1413_Y[24] Y[25]=$procmux$1413_Y[25] Y[26]=$procmux$1413_Y[26] Y[27]=$procmux$1413_Y[27] Y[28]=$procmux$1413_Y[28] Y[29]=$procmux$1413_Y[29] Y[30]=$procmux$1413_Y[30] Y[31]=$procmux$1413_Y[31]
|
||
|
|
.cname $procmux$1413
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:191"
|
||
|
|
.param WIDTH 00000000000000000000000000100000
|
||
|
|
.subckt $mux A[0]=H4[0] A[1]=H4[1] A[2]=H4[2] A[3]=H4[3] A[4]=H4[4] A[5]=H4[5] A[6]=H4[6] A[7]=H4[7] A[8]=H4[8] A[9]=H4[9] A[10]=H4[10] A[11]=H4[11] A[12]=H4[12] A[13]=H4[13] A[14]=H4[14] A[15]=H4[15] A[16]=H4[16] A[17]=H4[17] A[18]=H4[18] A[19]=H4[19] A[20]=H4[20] A[21]=H4[21] A[22]=H4[22] A[23]=H4[23] A[24]=H4[24] A[25]=H4[25] A[26]=H4[26] A[27]=H4[27] A[28]=H4[28] A[29]=H4[29] A[30]=H4[30] A[31]=H4[31] B[0]=$procmux$1413_Y[0] B[1]=$procmux$1413_Y[1] B[2]=$procmux$1413_Y[2] B[3]=$procmux$1413_Y[3] B[4]=$procmux$1413_Y[4] B[5]=$procmux$1413_Y[5] B[6]=$procmux$1413_Y[6] B[7]=$procmux$1413_Y[7] B[8]=$procmux$1413_Y[8] B[9]=$procmux$1413_Y[9] B[10]=$procmux$1413_Y[10] B[11]=$procmux$1413_Y[11] B[12]=$procmux$1413_Y[12] B[13]=$procmux$1413_Y[13] B[14]=$procmux$1413_Y[14] B[15]=$procmux$1413_Y[15] B[16]=$procmux$1413_Y[16] B[17]=$procmux$1413_Y[17] B[18]=$procmux$1413_Y[18] B[19]=$procmux$1413_Y[19] B[20]=$procmux$1413_Y[20] B[21]=$procmux$1413_Y[21] B[22]=$procmux$1413_Y[22] B[23]=$procmux$1413_Y[23] B[24]=$procmux$1413_Y[24] B[25]=$procmux$1413_Y[25] B[26]=$procmux$1413_Y[26] B[27]=$procmux$1413_Y[27] B[28]=$procmux$1413_Y[28] B[29]=$procmux$1413_Y[29] B[30]=$procmux$1413_Y[30] B[31]=$procmux$1413_Y[31] S=$procmux$1416_CMP Y[0]=$procmux$1415_Y[0] Y[1]=$procmux$1415_Y[1] Y[2]=$procmux$1415_Y[2] Y[3]=$procmux$1415_Y[3] Y[4]=$procmux$1415_Y[4] Y[5]=$procmux$1415_Y[5] Y[6]=$procmux$1415_Y[6] Y[7]=$procmux$1415_Y[7] Y[8]=$procmux$1415_Y[8] Y[9]=$procmux$1415_Y[9] Y[10]=$procmux$1415_Y[10] Y[11]=$procmux$1415_Y[11] Y[12]=$procmux$1415_Y[12] Y[13]=$procmux$1415_Y[13] Y[14]=$procmux$1415_Y[14] Y[15]=$procmux$1415_Y[15] Y[16]=$procmux$1415_Y[16] Y[17]=$procmux$1415_Y[17] Y[18]=$procmux$1415_Y[18] Y[19]=$procmux$1415_Y[19] Y[20]=$procmux$1415_Y[20] Y[21]=$procmux$1415_Y[21] Y[22]=$procmux$1415_Y[22] Y[23]=$procmux$1415_Y[23] Y[24]=$procmux$1415_Y[24] Y[25]=$procmux$1415_Y[25] Y[26]=$procmux$1415_Y[26] Y[27]=$procmux$1415_Y[27] Y[28]=$procmux$1415_Y[28] Y[29]=$procmux$1415_Y[29] Y[30]=$procmux$1415_Y[30] Y[31]=$procmux$1415_Y[31]
|
||
|
|
.cname $procmux$1415
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param WIDTH 00000000000000000000000000100000
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$false B[1]=$false B[2]=$false B[3]=$false B[4]=$false B[5]=$false B[6]=$false Y=$procmux$1416_CMP
|
||
|
|
.cname $procmux$1416_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $mux A[0]=$procmux$1415_Y[0] A[1]=$procmux$1415_Y[1] A[2]=$procmux$1415_Y[2] A[3]=$procmux$1415_Y[3] A[4]=$procmux$1415_Y[4] A[5]=$procmux$1415_Y[5] A[6]=$procmux$1415_Y[6] A[7]=$procmux$1415_Y[7] A[8]=$procmux$1415_Y[8] A[9]=$procmux$1415_Y[9] A[10]=$procmux$1415_Y[10] A[11]=$procmux$1415_Y[11] A[12]=$procmux$1415_Y[12] A[13]=$procmux$1415_Y[13] A[14]=$procmux$1415_Y[14] A[15]=$procmux$1415_Y[15] A[16]=$procmux$1415_Y[16] A[17]=$procmux$1415_Y[17] A[18]=$procmux$1415_Y[18] A[19]=$procmux$1415_Y[19] A[20]=$procmux$1415_Y[20] A[21]=$procmux$1415_Y[21] A[22]=$procmux$1415_Y[22] A[23]=$procmux$1415_Y[23] A[24]=$procmux$1415_Y[24] A[25]=$procmux$1415_Y[25] A[26]=$procmux$1415_Y[26] A[27]=$procmux$1415_Y[27] A[28]=$procmux$1415_Y[28] A[29]=$procmux$1415_Y[29] A[30]=$procmux$1415_Y[30] A[31]=$procmux$1415_Y[31] B[0]=$false B[1]=$false B[2]=$false B[3]=$false B[4]=$false B[5]=$false B[6]=$false B[7]=$false B[8]=$false B[9]=$false B[10]=$false B[11]=$false B[12]=$false B[13]=$false B[14]=$false B[15]=$false B[16]=$false B[17]=$false B[18]=$false B[19]=$false B[20]=$false B[21]=$false B[22]=$false B[23]=$false B[24]=$false B[25]=$false B[26]=$false B[27]=$false B[28]=$false B[29]=$false B[30]=$false B[31]=$false S=$procmux$1419_CMP Y[0]=$procmux$1418_Y[0] Y[1]=$procmux$1418_Y[1] Y[2]=$procmux$1418_Y[2] Y[3]=$procmux$1418_Y[3] Y[4]=$procmux$1418_Y[4] Y[5]=$procmux$1418_Y[5] Y[6]=$procmux$1418_Y[6] Y[7]=$procmux$1418_Y[7] Y[8]=$procmux$1418_Y[8] Y[9]=$procmux$1418_Y[9] Y[10]=$procmux$1418_Y[10] Y[11]=$procmux$1418_Y[11] Y[12]=$procmux$1418_Y[12] Y[13]=$procmux$1418_Y[13] Y[14]=$procmux$1418_Y[14] Y[15]=$procmux$1418_Y[15] Y[16]=$procmux$1418_Y[16] Y[17]=$procmux$1418_Y[17] Y[18]=$procmux$1418_Y[18] Y[19]=$procmux$1418_Y[19] Y[20]=$procmux$1418_Y[20] Y[21]=$procmux$1418_Y[21] Y[22]=$procmux$1418_Y[22] Y[23]=$procmux$1418_Y[23] Y[24]=$procmux$1418_Y[24] Y[25]=$procmux$1418_Y[25] Y[26]=$procmux$1418_Y[26] Y[27]=$procmux$1418_Y[27] Y[28]=$procmux$1418_Y[28] Y[29]=$procmux$1418_Y[29] Y[30]=$procmux$1418_Y[30] Y[31]=$procmux$1418_Y[31]
|
||
|
|
.cname $procmux$1418
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:150"
|
||
|
|
.param WIDTH 00000000000000000000000000100000
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$true B[1]=$true B[2]=$true B[3]=$false B[4]=$true B[5]=$false B[6]=$false Y=$procmux$141_CMP
|
||
|
|
.cname $procmux$141_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$false B[1]=$true B[2]=$true B[3]=$false B[4]=$true B[5]=$false B[6]=$false Y=$procmux$142_CMP
|
||
|
|
.cname $procmux$142_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$true B[1]=$false B[2]=$true B[3]=$false B[4]=$true B[5]=$false B[6]=$false Y=$procmux$143_CMP
|
||
|
|
.cname $procmux$143_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$false B[1]=$false B[2]=$true B[3]=$false B[4]=$true B[5]=$false B[6]=$false Y=$procmux$144_CMP
|
||
|
|
.cname $procmux$144_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$true B[1]=$true B[2]=$false B[3]=$false B[4]=$true B[5]=$false B[6]=$false Y=$procmux$145_CMP
|
||
|
|
.cname $procmux$145_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$false B[1]=$true B[2]=$false B[3]=$false B[4]=$true B[5]=$false B[6]=$false Y=$procmux$146_CMP
|
||
|
|
.cname $procmux$146_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$true B[1]=$false B[2]=$false B[3]=$false B[4]=$true B[5]=$false B[6]=$false Y=$procmux$147_CMP
|
||
|
|
.cname $procmux$147_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$false B[1]=$false B[2]=$false B[3]=$false B[4]=$true B[5]=$false B[6]=$false Y=$procmux$148_CMP
|
||
|
|
.cname $procmux$148_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$true B[1]=$true B[2]=$true B[3]=$true B[4]=$false B[5]=$false B[6]=$false Y=$procmux$149_CMP
|
||
|
|
.cname $procmux$149_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $pmux A[0]=H3[0] A[1]=H3[1] A[2]=H3[2] A[3]=H3[3] A[4]=H3[4] A[5]=H3[5] A[6]=H3[6] A[7]=H3[7] A[8]=H3[8] A[9]=H3[9] A[10]=H3[10] A[11]=H3[11] A[12]=H3[12] A[13]=H3[13] A[14]=H3[14] A[15]=H3[15] A[16]=H3[16] A[17]=H3[17] A[18]=H3[18] A[19]=H3[19] A[20]=H3[20] A[21]=H3[21] A[22]=H3[22] A[23]=H3[23] A[24]=H3[24] A[25]=H3[25] A[26]=H3[26] A[27]=H3[27] A[28]=H3[28] A[29]=H3[29] A[30]=H3[30] A[31]=H3[31] B[0]=D[0] B[1]=D[1] B[2]=D[2] B[3]=D[3] B[4]=D[4] B[5]=D[5] B[6]=D[6] B[7]=D[7] B[8]=D[8] B[9]=D[9] B[10]=D[10] B[11]=D[11] B[12]=D[12] B[13]=D[13] B[14]=D[14] B[15]=D[15] B[16]=D[16] B[17]=D[17] B[18]=D[18] B[19]=D[19] B[20]=D[20] B[21]=D[21] B[22]=D[22] B[23]=D[23] B[24]=D[24] B[25]=D[25] B[26]=D[26] B[27]=D[27] B[28]=D[28] B[29]=D[29] B[30]=D[30] B[31]=D[31] B[32]=$false B[33]=$true B[34]=$true B[35]=$false B[36]=$true B[37]=$true B[38]=$true B[39]=$false B[40]=$false B[41]=$false B[42]=$true B[43]=$false B[44]=$true B[45]=$false B[46]=$true B[47]=$false B[48]=$false B[49]=$true B[50]=$false B[51]=$false B[52]=$true B[53]=$true B[54]=$false B[55]=$false B[56]=$false B[57]=$false B[58]=$false B[59]=$false B[60]=$true B[61]=$false B[62]=$false B[63]=$false S[0]=$procmux$1503_CMP S[1]=$procmux$1504_CMP Y[0]=$procmux$1502_Y[0] Y[1]=$procmux$1502_Y[1] Y[2]=$procmux$1502_Y[2] Y[3]=$procmux$1502_Y[3] Y[4]=$procmux$1502_Y[4] Y[5]=$procmux$1502_Y[5] Y[6]=$procmux$1502_Y[6] Y[7]=$procmux$1502_Y[7] Y[8]=$procmux$1502_Y[8] Y[9]=$procmux$1502_Y[9] Y[10]=$procmux$1502_Y[10] Y[11]=$procmux$1502_Y[11] Y[12]=$procmux$1502_Y[12] Y[13]=$procmux$1502_Y[13] Y[14]=$procmux$1502_Y[14] Y[15]=$procmux$1502_Y[15] Y[16]=$procmux$1502_Y[16] Y[17]=$procmux$1502_Y[17] Y[18]=$procmux$1502_Y[18] Y[19]=$procmux$1502_Y[19] Y[20]=$procmux$1502_Y[20] Y[21]=$procmux$1502_Y[21] Y[22]=$procmux$1502_Y[22] Y[23]=$procmux$1502_Y[23] Y[24]=$procmux$1502_Y[24] Y[25]=$procmux$1502_Y[25] Y[26]=$procmux$1502_Y[26] Y[27]=$procmux$1502_Y[27] Y[28]=$procmux$1502_Y[28] Y[29]=$procmux$1502_Y[29] Y[30]=$procmux$1502_Y[30] Y[31]=$procmux$1502_Y[31]
|
||
|
|
.cname $procmux$1502
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:198"
|
||
|
|
.param S_WIDTH 00000000000000000000000000000010
|
||
|
|
.param WIDTH 00000000000000000000000000100000
|
||
|
|
.subckt $eq A=cmd[2] B=$false Y=$procmux$1504_CMP
|
||
|
|
.cname $procmux$1504_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:198"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000001
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000001
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $mux A[0]=H3[0] A[1]=H3[1] A[2]=H3[2] A[3]=H3[3] A[4]=H3[4] A[5]=H3[5] A[6]=H3[6] A[7]=H3[7] A[8]=H3[8] A[9]=H3[9] A[10]=H3[10] A[11]=H3[11] A[12]=H3[12] A[13]=H3[13] A[14]=H3[14] A[15]=H3[15] A[16]=H3[16] A[17]=H3[17] A[18]=H3[18] A[19]=H3[19] A[20]=H3[20] A[21]=H3[21] A[22]=H3[22] A[23]=H3[23] A[24]=H3[24] A[25]=H3[25] A[26]=H3[26] A[27]=H3[27] A[28]=H3[28] A[29]=H3[29] A[30]=H3[30] A[31]=H3[31] B[0]=$procmux$1502_Y[0] B[1]=$procmux$1502_Y[1] B[2]=$procmux$1502_Y[2] B[3]=$procmux$1502_Y[3] B[4]=$procmux$1502_Y[4] B[5]=$procmux$1502_Y[5] B[6]=$procmux$1502_Y[6] B[7]=$procmux$1502_Y[7] B[8]=$procmux$1502_Y[8] B[9]=$procmux$1502_Y[9] B[10]=$procmux$1502_Y[10] B[11]=$procmux$1502_Y[11] B[12]=$procmux$1502_Y[12] B[13]=$procmux$1502_Y[13] B[14]=$procmux$1502_Y[14] B[15]=$procmux$1502_Y[15] B[16]=$procmux$1502_Y[16] B[17]=$procmux$1502_Y[17] B[18]=$procmux$1502_Y[18] B[19]=$procmux$1502_Y[19] B[20]=$procmux$1502_Y[20] B[21]=$procmux$1502_Y[21] B[22]=$procmux$1502_Y[22] B[23]=$procmux$1502_Y[23] B[24]=$procmux$1502_Y[24] B[25]=$procmux$1502_Y[25] B[26]=$procmux$1502_Y[26] B[27]=$procmux$1502_Y[27] B[28]=$procmux$1502_Y[28] B[29]=$procmux$1502_Y[29] B[30]=$procmux$1502_Y[30] B[31]=$procmux$1502_Y[31] S=$procmux$1506_CMP Y[0]=$procmux$1505_Y[0] Y[1]=$procmux$1505_Y[1] Y[2]=$procmux$1505_Y[2] Y[3]=$procmux$1505_Y[3] Y[4]=$procmux$1505_Y[4] Y[5]=$procmux$1505_Y[5] Y[6]=$procmux$1505_Y[6] Y[7]=$procmux$1505_Y[7] Y[8]=$procmux$1505_Y[8] Y[9]=$procmux$1505_Y[9] Y[10]=$procmux$1505_Y[10] Y[11]=$procmux$1505_Y[11] Y[12]=$procmux$1505_Y[12] Y[13]=$procmux$1505_Y[13] Y[14]=$procmux$1505_Y[14] Y[15]=$procmux$1505_Y[15] Y[16]=$procmux$1505_Y[16] Y[17]=$procmux$1505_Y[17] Y[18]=$procmux$1505_Y[18] Y[19]=$procmux$1505_Y[19] Y[20]=$procmux$1505_Y[20] Y[21]=$procmux$1505_Y[21] Y[22]=$procmux$1505_Y[22] Y[23]=$procmux$1505_Y[23] Y[24]=$procmux$1505_Y[24] Y[25]=$procmux$1505_Y[25] Y[26]=$procmux$1505_Y[26] Y[27]=$procmux$1505_Y[27] Y[28]=$procmux$1505_Y[28] Y[29]=$procmux$1505_Y[29] Y[30]=$procmux$1505_Y[30] Y[31]=$procmux$1505_Y[31]
|
||
|
|
.cname $procmux$1505
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:191"
|
||
|
|
.param WIDTH 00000000000000000000000000100000
|
||
|
|
.subckt $mux A[0]=H3[0] A[1]=H3[1] A[2]=H3[2] A[3]=H3[3] A[4]=H3[4] A[5]=H3[5] A[6]=H3[6] A[7]=H3[7] A[8]=H3[8] A[9]=H3[9] A[10]=H3[10] A[11]=H3[11] A[12]=H3[12] A[13]=H3[13] A[14]=H3[14] A[15]=H3[15] A[16]=H3[16] A[17]=H3[17] A[18]=H3[18] A[19]=H3[19] A[20]=H3[20] A[21]=H3[21] A[22]=H3[22] A[23]=H3[23] A[24]=H3[24] A[25]=H3[25] A[26]=H3[26] A[27]=H3[27] A[28]=H3[28] A[29]=H3[29] A[30]=H3[30] A[31]=H3[31] B[0]=$procmux$1505_Y[0] B[1]=$procmux$1505_Y[1] B[2]=$procmux$1505_Y[2] B[3]=$procmux$1505_Y[3] B[4]=$procmux$1505_Y[4] B[5]=$procmux$1505_Y[5] B[6]=$procmux$1505_Y[6] B[7]=$procmux$1505_Y[7] B[8]=$procmux$1505_Y[8] B[9]=$procmux$1505_Y[9] B[10]=$procmux$1505_Y[10] B[11]=$procmux$1505_Y[11] B[12]=$procmux$1505_Y[12] B[13]=$procmux$1505_Y[13] B[14]=$procmux$1505_Y[14] B[15]=$procmux$1505_Y[15] B[16]=$procmux$1505_Y[16] B[17]=$procmux$1505_Y[17] B[18]=$procmux$1505_Y[18] B[19]=$procmux$1505_Y[19] B[20]=$procmux$1505_Y[20] B[21]=$procmux$1505_Y[21] B[22]=$procmux$1505_Y[22] B[23]=$procmux$1505_Y[23] B[24]=$procmux$1505_Y[24] B[25]=$procmux$1505_Y[25] B[26]=$procmux$1505_Y[26] B[27]=$procmux$1505_Y[27] B[28]=$procmux$1505_Y[28] B[29]=$procmux$1505_Y[29] B[30]=$procmux$1505_Y[30] B[31]=$procmux$1505_Y[31] S=$procmux$1508_CMP Y[0]=$procmux$1507_Y[0] Y[1]=$procmux$1507_Y[1] Y[2]=$procmux$1507_Y[2] Y[3]=$procmux$1507_Y[3] Y[4]=$procmux$1507_Y[4] Y[5]=$procmux$1507_Y[5] Y[6]=$procmux$1507_Y[6] Y[7]=$procmux$1507_Y[7] Y[8]=$procmux$1507_Y[8] Y[9]=$procmux$1507_Y[9] Y[10]=$procmux$1507_Y[10] Y[11]=$procmux$1507_Y[11] Y[12]=$procmux$1507_Y[12] Y[13]=$procmux$1507_Y[13] Y[14]=$procmux$1507_Y[14] Y[15]=$procmux$1507_Y[15] Y[16]=$procmux$1507_Y[16] Y[17]=$procmux$1507_Y[17] Y[18]=$procmux$1507_Y[18] Y[19]=$procmux$1507_Y[19] Y[20]=$procmux$1507_Y[20] Y[21]=$procmux$1507_Y[21] Y[22]=$procmux$1507_Y[22] Y[23]=$procmux$1507_Y[23] Y[24]=$procmux$1507_Y[24] Y[25]=$procmux$1507_Y[25] Y[26]=$procmux$1507_Y[26] Y[27]=$procmux$1507_Y[27] Y[28]=$procmux$1507_Y[28] Y[29]=$procmux$1507_Y[29] Y[30]=$procmux$1507_Y[30] Y[31]=$procmux$1507_Y[31]
|
||
|
|
.cname $procmux$1507
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param WIDTH 00000000000000000000000000100000
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$false B[1]=$false B[2]=$false B[3]=$false B[4]=$false B[5]=$false B[6]=$false Y=$procmux$1508_CMP
|
||
|
|
.cname $procmux$1508_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$false B[1]=$true B[2]=$true B[3]=$true B[4]=$false B[5]=$false B[6]=$false Y=$procmux$150_CMP
|
||
|
|
.cname $procmux$150_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $mux A[0]=$procmux$1507_Y[0] A[1]=$procmux$1507_Y[1] A[2]=$procmux$1507_Y[2] A[3]=$procmux$1507_Y[3] A[4]=$procmux$1507_Y[4] A[5]=$procmux$1507_Y[5] A[6]=$procmux$1507_Y[6] A[7]=$procmux$1507_Y[7] A[8]=$procmux$1507_Y[8] A[9]=$procmux$1507_Y[9] A[10]=$procmux$1507_Y[10] A[11]=$procmux$1507_Y[11] A[12]=$procmux$1507_Y[12] A[13]=$procmux$1507_Y[13] A[14]=$procmux$1507_Y[14] A[15]=$procmux$1507_Y[15] A[16]=$procmux$1507_Y[16] A[17]=$procmux$1507_Y[17] A[18]=$procmux$1507_Y[18] A[19]=$procmux$1507_Y[19] A[20]=$procmux$1507_Y[20] A[21]=$procmux$1507_Y[21] A[22]=$procmux$1507_Y[22] A[23]=$procmux$1507_Y[23] A[24]=$procmux$1507_Y[24] A[25]=$procmux$1507_Y[25] A[26]=$procmux$1507_Y[26] A[27]=$procmux$1507_Y[27] A[28]=$procmux$1507_Y[28] A[29]=$procmux$1507_Y[29] A[30]=$procmux$1507_Y[30] A[31]=$procmux$1507_Y[31] B[0]=$false B[1]=$false B[2]=$false B[3]=$false B[4]=$false B[5]=$false B[6]=$false B[7]=$false B[8]=$false B[9]=$false B[10]=$false B[11]=$false B[12]=$false B[13]=$false B[14]=$false B[15]=$false B[16]=$false B[17]=$false B[18]=$false B[19]=$false B[20]=$false B[21]=$false B[22]=$false B[23]=$false B[24]=$false B[25]=$false B[26]=$false B[27]=$false B[28]=$false B[29]=$false B[30]=$false B[31]=$false S=$procmux$1511_CMP Y[0]=$procmux$1510_Y[0] Y[1]=$procmux$1510_Y[1] Y[2]=$procmux$1510_Y[2] Y[3]=$procmux$1510_Y[3] Y[4]=$procmux$1510_Y[4] Y[5]=$procmux$1510_Y[5] Y[6]=$procmux$1510_Y[6] Y[7]=$procmux$1510_Y[7] Y[8]=$procmux$1510_Y[8] Y[9]=$procmux$1510_Y[9] Y[10]=$procmux$1510_Y[10] Y[11]=$procmux$1510_Y[11] Y[12]=$procmux$1510_Y[12] Y[13]=$procmux$1510_Y[13] Y[14]=$procmux$1510_Y[14] Y[15]=$procmux$1510_Y[15] Y[16]=$procmux$1510_Y[16] Y[17]=$procmux$1510_Y[17] Y[18]=$procmux$1510_Y[18] Y[19]=$procmux$1510_Y[19] Y[20]=$procmux$1510_Y[20] Y[21]=$procmux$1510_Y[21] Y[22]=$procmux$1510_Y[22] Y[23]=$procmux$1510_Y[23] Y[24]=$procmux$1510_Y[24] Y[25]=$procmux$1510_Y[25] Y[26]=$procmux$1510_Y[26] Y[27]=$procmux$1510_Y[27] Y[28]=$procmux$1510_Y[28] Y[29]=$procmux$1510_Y[29] Y[30]=$procmux$1510_Y[30] Y[31]=$procmux$1510_Y[31]
|
||
|
|
.cname $procmux$1510
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:150"
|
||
|
|
.param WIDTH 00000000000000000000000000100000
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$true B[1]=$false B[2]=$true B[3]=$true B[4]=$false B[5]=$false B[6]=$false Y=$procmux$151_CMP
|
||
|
|
.cname $procmux$151_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$false B[1]=$false B[2]=$true B[3]=$true B[4]=$false B[5]=$false B[6]=$false Y=$procmux$152_CMP
|
||
|
|
.cname $procmux$152_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$true B[1]=$true B[2]=$false B[3]=$true B[4]=$false B[5]=$false B[6]=$false Y=$procmux$153_CMP
|
||
|
|
.cname $procmux$153_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$false B[1]=$true B[2]=$false B[3]=$true B[4]=$false B[5]=$false B[6]=$false Y=$procmux$154_CMP
|
||
|
|
.cname $procmux$154_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$true B[1]=$false B[2]=$false B[3]=$true B[4]=$false B[5]=$false B[6]=$false Y=$procmux$155_CMP
|
||
|
|
.cname $procmux$155_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$false B[1]=$false B[2]=$false B[3]=$true B[4]=$false B[5]=$false B[6]=$false Y=$procmux$156_CMP
|
||
|
|
.cname $procmux$156_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$true B[1]=$true B[2]=$true B[3]=$false B[4]=$false B[5]=$false B[6]=$false Y=$procmux$157_CMP
|
||
|
|
.cname $procmux$157_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$false B[1]=$true B[2]=$true B[3]=$false B[4]=$false B[5]=$false B[6]=$false Y=$procmux$158_CMP
|
||
|
|
.cname $procmux$158_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $pmux A[0]=H2[0] A[1]=H2[1] A[2]=H2[2] A[3]=H2[3] A[4]=H2[4] A[5]=H2[5] A[6]=H2[6] A[7]=H2[7] A[8]=H2[8] A[9]=H2[9] A[10]=H2[10] A[11]=H2[11] A[12]=H2[12] A[13]=H2[13] A[14]=H2[14] A[15]=H2[15] A[16]=H2[16] A[17]=H2[17] A[18]=H2[18] A[19]=H2[19] A[20]=H2[20] A[21]=H2[21] A[22]=H2[22] A[23]=H2[23] A[24]=H2[24] A[25]=H2[25] A[26]=H2[26] A[27]=H2[27] A[28]=H2[28] A[29]=H2[29] A[30]=H2[30] A[31]=H2[31] B[0]=C[0] B[1]=C[1] B[2]=C[2] B[3]=C[3] B[4]=C[4] B[5]=C[5] B[6]=C[6] B[7]=C[7] B[8]=C[8] B[9]=C[9] B[10]=C[10] B[11]=C[11] B[12]=C[12] B[13]=C[13] B[14]=C[14] B[15]=C[15] B[16]=C[16] B[17]=C[17] B[18]=C[18] B[19]=C[19] B[20]=C[20] B[21]=C[21] B[22]=C[22] B[23]=C[23] B[24]=C[24] B[25]=C[25] B[26]=C[26] B[27]=C[27] B[28]=C[28] B[29]=C[29] B[30]=C[30] B[31]=C[31] B[32]=$false B[33]=$true B[34]=$true B[35]=$true B[36]=$true B[37]=$true B[38]=$true B[39]=$true B[40]=$false B[41]=$false B[42]=$true B[43]=$true B[44]=$true B[45]=$false B[46]=$true B[47]=$true B[48]=$false B[49]=$true B[50]=$false B[51]=$true B[52]=$true B[53]=$true B[54]=$false B[55]=$true B[56]=$false B[57]=$false B[58]=$false B[59]=$true B[60]=$true B[61]=$false B[62]=$false B[63]=$true S[0]=$procmux$1595_CMP S[1]=$procmux$1596_CMP Y[0]=$procmux$1594_Y[0] Y[1]=$procmux$1594_Y[1] Y[2]=$procmux$1594_Y[2] Y[3]=$procmux$1594_Y[3] Y[4]=$procmux$1594_Y[4] Y[5]=$procmux$1594_Y[5] Y[6]=$procmux$1594_Y[6] Y[7]=$procmux$1594_Y[7] Y[8]=$procmux$1594_Y[8] Y[9]=$procmux$1594_Y[9] Y[10]=$procmux$1594_Y[10] Y[11]=$procmux$1594_Y[11] Y[12]=$procmux$1594_Y[12] Y[13]=$procmux$1594_Y[13] Y[14]=$procmux$1594_Y[14] Y[15]=$procmux$1594_Y[15] Y[16]=$procmux$1594_Y[16] Y[17]=$procmux$1594_Y[17] Y[18]=$procmux$1594_Y[18] Y[19]=$procmux$1594_Y[19] Y[20]=$procmux$1594_Y[20] Y[21]=$procmux$1594_Y[21] Y[22]=$procmux$1594_Y[22] Y[23]=$procmux$1594_Y[23] Y[24]=$procmux$1594_Y[24] Y[25]=$procmux$1594_Y[25] Y[26]=$procmux$1594_Y[26] Y[27]=$procmux$1594_Y[27] Y[28]=$procmux$1594_Y[28] Y[29]=$procmux$1594_Y[29] Y[30]=$procmux$1594_Y[30] Y[31]=$procmux$1594_Y[31]
|
||
|
|
.cname $procmux$1594
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:198"
|
||
|
|
.param S_WIDTH 00000000000000000000000000000010
|
||
|
|
.param WIDTH 00000000000000000000000000100000
|
||
|
|
.subckt $eq A=cmd[2] B=$false Y=$procmux$1596_CMP
|
||
|
|
.cname $procmux$1596_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:198"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000001
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000001
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $mux A[0]=H2[0] A[1]=H2[1] A[2]=H2[2] A[3]=H2[3] A[4]=H2[4] A[5]=H2[5] A[6]=H2[6] A[7]=H2[7] A[8]=H2[8] A[9]=H2[9] A[10]=H2[10] A[11]=H2[11] A[12]=H2[12] A[13]=H2[13] A[14]=H2[14] A[15]=H2[15] A[16]=H2[16] A[17]=H2[17] A[18]=H2[18] A[19]=H2[19] A[20]=H2[20] A[21]=H2[21] A[22]=H2[22] A[23]=H2[23] A[24]=H2[24] A[25]=H2[25] A[26]=H2[26] A[27]=H2[27] A[28]=H2[28] A[29]=H2[29] A[30]=H2[30] A[31]=H2[31] B[0]=$procmux$1594_Y[0] B[1]=$procmux$1594_Y[1] B[2]=$procmux$1594_Y[2] B[3]=$procmux$1594_Y[3] B[4]=$procmux$1594_Y[4] B[5]=$procmux$1594_Y[5] B[6]=$procmux$1594_Y[6] B[7]=$procmux$1594_Y[7] B[8]=$procmux$1594_Y[8] B[9]=$procmux$1594_Y[9] B[10]=$procmux$1594_Y[10] B[11]=$procmux$1594_Y[11] B[12]=$procmux$1594_Y[12] B[13]=$procmux$1594_Y[13] B[14]=$procmux$1594_Y[14] B[15]=$procmux$1594_Y[15] B[16]=$procmux$1594_Y[16] B[17]=$procmux$1594_Y[17] B[18]=$procmux$1594_Y[18] B[19]=$procmux$1594_Y[19] B[20]=$procmux$1594_Y[20] B[21]=$procmux$1594_Y[21] B[22]=$procmux$1594_Y[22] B[23]=$procmux$1594_Y[23] B[24]=$procmux$1594_Y[24] B[25]=$procmux$1594_Y[25] B[26]=$procmux$1594_Y[26] B[27]=$procmux$1594_Y[27] B[28]=$procmux$1594_Y[28] B[29]=$procmux$1594_Y[29] B[30]=$procmux$1594_Y[30] B[31]=$procmux$1594_Y[31] S=$procmux$1598_CMP Y[0]=$procmux$1597_Y[0] Y[1]=$procmux$1597_Y[1] Y[2]=$procmux$1597_Y[2] Y[3]=$procmux$1597_Y[3] Y[4]=$procmux$1597_Y[4] Y[5]=$procmux$1597_Y[5] Y[6]=$procmux$1597_Y[6] Y[7]=$procmux$1597_Y[7] Y[8]=$procmux$1597_Y[8] Y[9]=$procmux$1597_Y[9] Y[10]=$procmux$1597_Y[10] Y[11]=$procmux$1597_Y[11] Y[12]=$procmux$1597_Y[12] Y[13]=$procmux$1597_Y[13] Y[14]=$procmux$1597_Y[14] Y[15]=$procmux$1597_Y[15] Y[16]=$procmux$1597_Y[16] Y[17]=$procmux$1597_Y[17] Y[18]=$procmux$1597_Y[18] Y[19]=$procmux$1597_Y[19] Y[20]=$procmux$1597_Y[20] Y[21]=$procmux$1597_Y[21] Y[22]=$procmux$1597_Y[22] Y[23]=$procmux$1597_Y[23] Y[24]=$procmux$1597_Y[24] Y[25]=$procmux$1597_Y[25] Y[26]=$procmux$1597_Y[26] Y[27]=$procmux$1597_Y[27] Y[28]=$procmux$1597_Y[28] Y[29]=$procmux$1597_Y[29] Y[30]=$procmux$1597_Y[30] Y[31]=$procmux$1597_Y[31]
|
||
|
|
.cname $procmux$1597
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:191"
|
||
|
|
.param WIDTH 00000000000000000000000000100000
|
||
|
|
.subckt $mux A[0]=H2[0] A[1]=H2[1] A[2]=H2[2] A[3]=H2[3] A[4]=H2[4] A[5]=H2[5] A[6]=H2[6] A[7]=H2[7] A[8]=H2[8] A[9]=H2[9] A[10]=H2[10] A[11]=H2[11] A[12]=H2[12] A[13]=H2[13] A[14]=H2[14] A[15]=H2[15] A[16]=H2[16] A[17]=H2[17] A[18]=H2[18] A[19]=H2[19] A[20]=H2[20] A[21]=H2[21] A[22]=H2[22] A[23]=H2[23] A[24]=H2[24] A[25]=H2[25] A[26]=H2[26] A[27]=H2[27] A[28]=H2[28] A[29]=H2[29] A[30]=H2[30] A[31]=H2[31] B[0]=$procmux$1597_Y[0] B[1]=$procmux$1597_Y[1] B[2]=$procmux$1597_Y[2] B[3]=$procmux$1597_Y[3] B[4]=$procmux$1597_Y[4] B[5]=$procmux$1597_Y[5] B[6]=$procmux$1597_Y[6] B[7]=$procmux$1597_Y[7] B[8]=$procmux$1597_Y[8] B[9]=$procmux$1597_Y[9] B[10]=$procmux$1597_Y[10] B[11]=$procmux$1597_Y[11] B[12]=$procmux$1597_Y[12] B[13]=$procmux$1597_Y[13] B[14]=$procmux$1597_Y[14] B[15]=$procmux$1597_Y[15] B[16]=$procmux$1597_Y[16] B[17]=$procmux$1597_Y[17] B[18]=$procmux$1597_Y[18] B[19]=$procmux$1597_Y[19] B[20]=$procmux$1597_Y[20] B[21]=$procmux$1597_Y[21] B[22]=$procmux$1597_Y[22] B[23]=$procmux$1597_Y[23] B[24]=$procmux$1597_Y[24] B[25]=$procmux$1597_Y[25] B[26]=$procmux$1597_Y[26] B[27]=$procmux$1597_Y[27] B[28]=$procmux$1597_Y[28] B[29]=$procmux$1597_Y[29] B[30]=$procmux$1597_Y[30] B[31]=$procmux$1597_Y[31] S=$procmux$1600_CMP Y[0]=$procmux$1599_Y[0] Y[1]=$procmux$1599_Y[1] Y[2]=$procmux$1599_Y[2] Y[3]=$procmux$1599_Y[3] Y[4]=$procmux$1599_Y[4] Y[5]=$procmux$1599_Y[5] Y[6]=$procmux$1599_Y[6] Y[7]=$procmux$1599_Y[7] Y[8]=$procmux$1599_Y[8] Y[9]=$procmux$1599_Y[9] Y[10]=$procmux$1599_Y[10] Y[11]=$procmux$1599_Y[11] Y[12]=$procmux$1599_Y[12] Y[13]=$procmux$1599_Y[13] Y[14]=$procmux$1599_Y[14] Y[15]=$procmux$1599_Y[15] Y[16]=$procmux$1599_Y[16] Y[17]=$procmux$1599_Y[17] Y[18]=$procmux$1599_Y[18] Y[19]=$procmux$1599_Y[19] Y[20]=$procmux$1599_Y[20] Y[21]=$procmux$1599_Y[21] Y[22]=$procmux$1599_Y[22] Y[23]=$procmux$1599_Y[23] Y[24]=$procmux$1599_Y[24] Y[25]=$procmux$1599_Y[25] Y[26]=$procmux$1599_Y[26] Y[27]=$procmux$1599_Y[27] Y[28]=$procmux$1599_Y[28] Y[29]=$procmux$1599_Y[29] Y[30]=$procmux$1599_Y[30] Y[31]=$procmux$1599_Y[31]
|
||
|
|
.cname $procmux$1599
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param WIDTH 00000000000000000000000000100000
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$true B[1]=$false B[2]=$true B[3]=$false B[4]=$false B[5]=$false B[6]=$false Y=$procmux$159_CMP
|
||
|
|
.cname $procmux$159_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$false B[1]=$false B[2]=$false B[3]=$false B[4]=$false B[5]=$false B[6]=$false Y=$procmux$1600_CMP
|
||
|
|
.cname $procmux$1600_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $mux A[0]=$procmux$1599_Y[0] A[1]=$procmux$1599_Y[1] A[2]=$procmux$1599_Y[2] A[3]=$procmux$1599_Y[3] A[4]=$procmux$1599_Y[4] A[5]=$procmux$1599_Y[5] A[6]=$procmux$1599_Y[6] A[7]=$procmux$1599_Y[7] A[8]=$procmux$1599_Y[8] A[9]=$procmux$1599_Y[9] A[10]=$procmux$1599_Y[10] A[11]=$procmux$1599_Y[11] A[12]=$procmux$1599_Y[12] A[13]=$procmux$1599_Y[13] A[14]=$procmux$1599_Y[14] A[15]=$procmux$1599_Y[15] A[16]=$procmux$1599_Y[16] A[17]=$procmux$1599_Y[17] A[18]=$procmux$1599_Y[18] A[19]=$procmux$1599_Y[19] A[20]=$procmux$1599_Y[20] A[21]=$procmux$1599_Y[21] A[22]=$procmux$1599_Y[22] A[23]=$procmux$1599_Y[23] A[24]=$procmux$1599_Y[24] A[25]=$procmux$1599_Y[25] A[26]=$procmux$1599_Y[26] A[27]=$procmux$1599_Y[27] A[28]=$procmux$1599_Y[28] A[29]=$procmux$1599_Y[29] A[30]=$procmux$1599_Y[30] A[31]=$procmux$1599_Y[31] B[0]=$false B[1]=$false B[2]=$false B[3]=$false B[4]=$false B[5]=$false B[6]=$false B[7]=$false B[8]=$false B[9]=$false B[10]=$false B[11]=$false B[12]=$false B[13]=$false B[14]=$false B[15]=$false B[16]=$false B[17]=$false B[18]=$false B[19]=$false B[20]=$false B[21]=$false B[22]=$false B[23]=$false B[24]=$false B[25]=$false B[26]=$false B[27]=$false B[28]=$false B[29]=$false B[30]=$false B[31]=$false S=$procmux$1603_CMP Y[0]=$procmux$1602_Y[0] Y[1]=$procmux$1602_Y[1] Y[2]=$procmux$1602_Y[2] Y[3]=$procmux$1602_Y[3] Y[4]=$procmux$1602_Y[4] Y[5]=$procmux$1602_Y[5] Y[6]=$procmux$1602_Y[6] Y[7]=$procmux$1602_Y[7] Y[8]=$procmux$1602_Y[8] Y[9]=$procmux$1602_Y[9] Y[10]=$procmux$1602_Y[10] Y[11]=$procmux$1602_Y[11] Y[12]=$procmux$1602_Y[12] Y[13]=$procmux$1602_Y[13] Y[14]=$procmux$1602_Y[14] Y[15]=$procmux$1602_Y[15] Y[16]=$procmux$1602_Y[16] Y[17]=$procmux$1602_Y[17] Y[18]=$procmux$1602_Y[18] Y[19]=$procmux$1602_Y[19] Y[20]=$procmux$1602_Y[20] Y[21]=$procmux$1602_Y[21] Y[22]=$procmux$1602_Y[22] Y[23]=$procmux$1602_Y[23] Y[24]=$procmux$1602_Y[24] Y[25]=$procmux$1602_Y[25] Y[26]=$procmux$1602_Y[26] Y[27]=$procmux$1602_Y[27] Y[28]=$procmux$1602_Y[28] Y[29]=$procmux$1602_Y[29] Y[30]=$procmux$1602_Y[30] Y[31]=$procmux$1602_Y[31]
|
||
|
|
.cname $procmux$1602
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:150"
|
||
|
|
.param WIDTH 00000000000000000000000000100000
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$false B[1]=$false B[2]=$true B[3]=$false B[4]=$false B[5]=$false B[6]=$false Y=$procmux$160_CMP
|
||
|
|
.cname $procmux$160_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$true B[1]=$true B[2]=$false B[3]=$false B[4]=$false B[5]=$false B[6]=$false Y=$procmux$161_CMP
|
||
|
|
.cname $procmux$161_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$false B[1]=$true B[2]=$false B[3]=$false B[4]=$false B[5]=$false B[6]=$false Y=$procmux$162_CMP
|
||
|
|
.cname $procmux$162_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$true B[1]=$false B[2]=$false B[3]=$false B[4]=$false B[5]=$false B[6]=$false Y=$procmux$163_CMP
|
||
|
|
.cname $procmux$163_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $mux A=busy B=$true S=$procmux$166_CMP Y=$procmux$165_Y
|
||
|
|
.cname $procmux$165
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:191"
|
||
|
|
.param WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$false B[1]=$false B[2]=$false B[3]=$false B[4]=$false B[5]=$false B[6]=$false Y=$procmux$167_CMP
|
||
|
|
.cname $procmux$167_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $pmux A[0]=H1[0] A[1]=H1[1] A[2]=H1[2] A[3]=H1[3] A[4]=H1[4] A[5]=H1[5] A[6]=H1[6] A[7]=H1[7] A[8]=H1[8] A[9]=H1[9] A[10]=H1[10] A[11]=H1[11] A[12]=H1[12] A[13]=H1[13] A[14]=H1[14] A[15]=H1[15] A[16]=H1[16] A[17]=H1[17] A[18]=H1[18] A[19]=H1[19] A[20]=H1[20] A[21]=H1[21] A[22]=H1[22] A[23]=H1[23] A[24]=H1[24] A[25]=H1[25] A[26]=H1[26] A[27]=H1[27] A[28]=H1[28] A[29]=H1[29] A[30]=H1[30] A[31]=H1[31] B[0]=B[0] B[1]=B[1] B[2]=B[2] B[3]=B[3] B[4]=B[4] B[5]=B[5] B[6]=B[6] B[7]=B[7] B[8]=B[8] B[9]=B[9] B[10]=B[10] B[11]=B[11] B[12]=B[12] B[13]=B[13] B[14]=B[14] B[15]=B[15] B[16]=B[16] B[17]=B[17] B[18]=B[18] B[19]=B[19] B[20]=B[20] B[21]=B[21] B[22]=B[22] B[23]=B[23] B[24]=B[24] B[25]=B[25] B[26]=B[26] B[27]=B[27] B[28]=B[28] B[29]=B[29] B[30]=B[30] B[31]=B[31] B[32]=$true B[33]=$false B[34]=$false B[35]=$true B[36]=$false B[37]=$false B[38]=$false B[39]=$true B[40]=$true B[41]=$true B[42]=$false B[43]=$true B[44]=$false B[45]=$true B[46]=$false B[47]=$true B[48]=$true B[49]=$false B[50]=$true B[51]=$true B[52]=$false B[53]=$false B[54]=$true B[55]=$true B[56]=$true B[57]=$true B[58]=$true B[59]=$true B[60]=$false B[61]=$true B[62]=$true B[63]=$true S[0]=$procmux$1687_CMP S[1]=$procmux$1688_CMP Y[0]=$procmux$1686_Y[0] Y[1]=$procmux$1686_Y[1] Y[2]=$procmux$1686_Y[2] Y[3]=$procmux$1686_Y[3] Y[4]=$procmux$1686_Y[4] Y[5]=$procmux$1686_Y[5] Y[6]=$procmux$1686_Y[6] Y[7]=$procmux$1686_Y[7] Y[8]=$procmux$1686_Y[8] Y[9]=$procmux$1686_Y[9] Y[10]=$procmux$1686_Y[10] Y[11]=$procmux$1686_Y[11] Y[12]=$procmux$1686_Y[12] Y[13]=$procmux$1686_Y[13] Y[14]=$procmux$1686_Y[14] Y[15]=$procmux$1686_Y[15] Y[16]=$procmux$1686_Y[16] Y[17]=$procmux$1686_Y[17] Y[18]=$procmux$1686_Y[18] Y[19]=$procmux$1686_Y[19] Y[20]=$procmux$1686_Y[20] Y[21]=$procmux$1686_Y[21] Y[22]=$procmux$1686_Y[22] Y[23]=$procmux$1686_Y[23] Y[24]=$procmux$1686_Y[24] Y[25]=$procmux$1686_Y[25] Y[26]=$procmux$1686_Y[26] Y[27]=$procmux$1686_Y[27] Y[28]=$procmux$1686_Y[28] Y[29]=$procmux$1686_Y[29] Y[30]=$procmux$1686_Y[30] Y[31]=$procmux$1686_Y[31]
|
||
|
|
.cname $procmux$1686
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:198"
|
||
|
|
.param S_WIDTH 00000000000000000000000000000010
|
||
|
|
.param WIDTH 00000000000000000000000000100000
|
||
|
|
.subckt $eq A=cmd[2] B=$false Y=$procmux$1688_CMP
|
||
|
|
.cname $procmux$1688_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:198"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000001
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000001
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $mux A[0]=H1[0] A[1]=H1[1] A[2]=H1[2] A[3]=H1[3] A[4]=H1[4] A[5]=H1[5] A[6]=H1[6] A[7]=H1[7] A[8]=H1[8] A[9]=H1[9] A[10]=H1[10] A[11]=H1[11] A[12]=H1[12] A[13]=H1[13] A[14]=H1[14] A[15]=H1[15] A[16]=H1[16] A[17]=H1[17] A[18]=H1[18] A[19]=H1[19] A[20]=H1[20] A[21]=H1[21] A[22]=H1[22] A[23]=H1[23] A[24]=H1[24] A[25]=H1[25] A[26]=H1[26] A[27]=H1[27] A[28]=H1[28] A[29]=H1[29] A[30]=H1[30] A[31]=H1[31] B[0]=$procmux$1686_Y[0] B[1]=$procmux$1686_Y[1] B[2]=$procmux$1686_Y[2] B[3]=$procmux$1686_Y[3] B[4]=$procmux$1686_Y[4] B[5]=$procmux$1686_Y[5] B[6]=$procmux$1686_Y[6] B[7]=$procmux$1686_Y[7] B[8]=$procmux$1686_Y[8] B[9]=$procmux$1686_Y[9] B[10]=$procmux$1686_Y[10] B[11]=$procmux$1686_Y[11] B[12]=$procmux$1686_Y[12] B[13]=$procmux$1686_Y[13] B[14]=$procmux$1686_Y[14] B[15]=$procmux$1686_Y[15] B[16]=$procmux$1686_Y[16] B[17]=$procmux$1686_Y[17] B[18]=$procmux$1686_Y[18] B[19]=$procmux$1686_Y[19] B[20]=$procmux$1686_Y[20] B[21]=$procmux$1686_Y[21] B[22]=$procmux$1686_Y[22] B[23]=$procmux$1686_Y[23] B[24]=$procmux$1686_Y[24] B[25]=$procmux$1686_Y[25] B[26]=$procmux$1686_Y[26] B[27]=$procmux$1686_Y[27] B[28]=$procmux$1686_Y[28] B[29]=$procmux$1686_Y[29] B[30]=$procmux$1686_Y[30] B[31]=$procmux$1686_Y[31] S=$procmux$1690_CMP Y[0]=$procmux$1689_Y[0] Y[1]=$procmux$1689_Y[1] Y[2]=$procmux$1689_Y[2] Y[3]=$procmux$1689_Y[3] Y[4]=$procmux$1689_Y[4] Y[5]=$procmux$1689_Y[5] Y[6]=$procmux$1689_Y[6] Y[7]=$procmux$1689_Y[7] Y[8]=$procmux$1689_Y[8] Y[9]=$procmux$1689_Y[9] Y[10]=$procmux$1689_Y[10] Y[11]=$procmux$1689_Y[11] Y[12]=$procmux$1689_Y[12] Y[13]=$procmux$1689_Y[13] Y[14]=$procmux$1689_Y[14] Y[15]=$procmux$1689_Y[15] Y[16]=$procmux$1689_Y[16] Y[17]=$procmux$1689_Y[17] Y[18]=$procmux$1689_Y[18] Y[19]=$procmux$1689_Y[19] Y[20]=$procmux$1689_Y[20] Y[21]=$procmux$1689_Y[21] Y[22]=$procmux$1689_Y[22] Y[23]=$procmux$1689_Y[23] Y[24]=$procmux$1689_Y[24] Y[25]=$procmux$1689_Y[25] Y[26]=$procmux$1689_Y[26] Y[27]=$procmux$1689_Y[27] Y[28]=$procmux$1689_Y[28] Y[29]=$procmux$1689_Y[29] Y[30]=$procmux$1689_Y[30] Y[31]=$procmux$1689_Y[31]
|
||
|
|
.cname $procmux$1689
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:191"
|
||
|
|
.param WIDTH 00000000000000000000000000100000
|
||
|
|
.subckt $mux A=$procmux$84_Y B=$false S=$procmux$170_CMP Y=$procmux$169_Y
|
||
|
|
.cname $procmux$169
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:150"
|
||
|
|
.param WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $mux A[0]=H1[0] A[1]=H1[1] A[2]=H1[2] A[3]=H1[3] A[4]=H1[4] A[5]=H1[5] A[6]=H1[6] A[7]=H1[7] A[8]=H1[8] A[9]=H1[9] A[10]=H1[10] A[11]=H1[11] A[12]=H1[12] A[13]=H1[13] A[14]=H1[14] A[15]=H1[15] A[16]=H1[16] A[17]=H1[17] A[18]=H1[18] A[19]=H1[19] A[20]=H1[20] A[21]=H1[21] A[22]=H1[22] A[23]=H1[23] A[24]=H1[24] A[25]=H1[25] A[26]=H1[26] A[27]=H1[27] A[28]=H1[28] A[29]=H1[29] A[30]=H1[30] A[31]=H1[31] B[0]=$procmux$1689_Y[0] B[1]=$procmux$1689_Y[1] B[2]=$procmux$1689_Y[2] B[3]=$procmux$1689_Y[3] B[4]=$procmux$1689_Y[4] B[5]=$procmux$1689_Y[5] B[6]=$procmux$1689_Y[6] B[7]=$procmux$1689_Y[7] B[8]=$procmux$1689_Y[8] B[9]=$procmux$1689_Y[9] B[10]=$procmux$1689_Y[10] B[11]=$procmux$1689_Y[11] B[12]=$procmux$1689_Y[12] B[13]=$procmux$1689_Y[13] B[14]=$procmux$1689_Y[14] B[15]=$procmux$1689_Y[15] B[16]=$procmux$1689_Y[16] B[17]=$procmux$1689_Y[17] B[18]=$procmux$1689_Y[18] B[19]=$procmux$1689_Y[19] B[20]=$procmux$1689_Y[20] B[21]=$procmux$1689_Y[21] B[22]=$procmux$1689_Y[22] B[23]=$procmux$1689_Y[23] B[24]=$procmux$1689_Y[24] B[25]=$procmux$1689_Y[25] B[26]=$procmux$1689_Y[26] B[27]=$procmux$1689_Y[27] B[28]=$procmux$1689_Y[28] B[29]=$procmux$1689_Y[29] B[30]=$procmux$1689_Y[30] B[31]=$procmux$1689_Y[31] S=$procmux$1692_CMP Y[0]=$procmux$1691_Y[0] Y[1]=$procmux$1691_Y[1] Y[2]=$procmux$1691_Y[2] Y[3]=$procmux$1691_Y[3] Y[4]=$procmux$1691_Y[4] Y[5]=$procmux$1691_Y[5] Y[6]=$procmux$1691_Y[6] Y[7]=$procmux$1691_Y[7] Y[8]=$procmux$1691_Y[8] Y[9]=$procmux$1691_Y[9] Y[10]=$procmux$1691_Y[10] Y[11]=$procmux$1691_Y[11] Y[12]=$procmux$1691_Y[12] Y[13]=$procmux$1691_Y[13] Y[14]=$procmux$1691_Y[14] Y[15]=$procmux$1691_Y[15] Y[16]=$procmux$1691_Y[16] Y[17]=$procmux$1691_Y[17] Y[18]=$procmux$1691_Y[18] Y[19]=$procmux$1691_Y[19] Y[20]=$procmux$1691_Y[20] Y[21]=$procmux$1691_Y[21] Y[22]=$procmux$1691_Y[22] Y[23]=$procmux$1691_Y[23] Y[24]=$procmux$1691_Y[24] Y[25]=$procmux$1691_Y[25] Y[26]=$procmux$1691_Y[26] Y[27]=$procmux$1691_Y[27] Y[28]=$procmux$1691_Y[28] Y[29]=$procmux$1691_Y[29] Y[30]=$procmux$1691_Y[30] Y[31]=$procmux$1691_Y[31]
|
||
|
|
.cname $procmux$1691
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param WIDTH 00000000000000000000000000100000
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$false B[1]=$false B[2]=$false B[3]=$false B[4]=$false B[5]=$false B[6]=$false Y=$procmux$1692_CMP
|
||
|
|
.cname $procmux$1692_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $mux A[0]=$procmux$1691_Y[0] A[1]=$procmux$1691_Y[1] A[2]=$procmux$1691_Y[2] A[3]=$procmux$1691_Y[3] A[4]=$procmux$1691_Y[4] A[5]=$procmux$1691_Y[5] A[6]=$procmux$1691_Y[6] A[7]=$procmux$1691_Y[7] A[8]=$procmux$1691_Y[8] A[9]=$procmux$1691_Y[9] A[10]=$procmux$1691_Y[10] A[11]=$procmux$1691_Y[11] A[12]=$procmux$1691_Y[12] A[13]=$procmux$1691_Y[13] A[14]=$procmux$1691_Y[14] A[15]=$procmux$1691_Y[15] A[16]=$procmux$1691_Y[16] A[17]=$procmux$1691_Y[17] A[18]=$procmux$1691_Y[18] A[19]=$procmux$1691_Y[19] A[20]=$procmux$1691_Y[20] A[21]=$procmux$1691_Y[21] A[22]=$procmux$1691_Y[22] A[23]=$procmux$1691_Y[23] A[24]=$procmux$1691_Y[24] A[25]=$procmux$1691_Y[25] A[26]=$procmux$1691_Y[26] A[27]=$procmux$1691_Y[27] A[28]=$procmux$1691_Y[28] A[29]=$procmux$1691_Y[29] A[30]=$procmux$1691_Y[30] A[31]=$procmux$1691_Y[31] B[0]=$false B[1]=$false B[2]=$false B[3]=$false B[4]=$false B[5]=$false B[6]=$false B[7]=$false B[8]=$false B[9]=$false B[10]=$false B[11]=$false B[12]=$false B[13]=$false B[14]=$false B[15]=$false B[16]=$false B[17]=$false B[18]=$false B[19]=$false B[20]=$false B[21]=$false B[22]=$false B[23]=$false B[24]=$false B[25]=$false B[26]=$false B[27]=$false B[28]=$false B[29]=$false B[30]=$false B[31]=$false S=$procmux$1695_CMP Y[0]=$procmux$1694_Y[0] Y[1]=$procmux$1694_Y[1] Y[2]=$procmux$1694_Y[2] Y[3]=$procmux$1694_Y[3] Y[4]=$procmux$1694_Y[4] Y[5]=$procmux$1694_Y[5] Y[6]=$procmux$1694_Y[6] Y[7]=$procmux$1694_Y[7] Y[8]=$procmux$1694_Y[8] Y[9]=$procmux$1694_Y[9] Y[10]=$procmux$1694_Y[10] Y[11]=$procmux$1694_Y[11] Y[12]=$procmux$1694_Y[12] Y[13]=$procmux$1694_Y[13] Y[14]=$procmux$1694_Y[14] Y[15]=$procmux$1694_Y[15] Y[16]=$procmux$1694_Y[16] Y[17]=$procmux$1694_Y[17] Y[18]=$procmux$1694_Y[18] Y[19]=$procmux$1694_Y[19] Y[20]=$procmux$1694_Y[20] Y[21]=$procmux$1694_Y[21] Y[22]=$procmux$1694_Y[22] Y[23]=$procmux$1694_Y[23] Y[24]=$procmux$1694_Y[24] Y[25]=$procmux$1694_Y[25] Y[26]=$procmux$1694_Y[26] Y[27]=$procmux$1694_Y[27] Y[28]=$procmux$1694_Y[28] Y[29]=$procmux$1694_Y[29] Y[30]=$procmux$1694_Y[30] Y[31]=$procmux$1694_Y[31]
|
||
|
|
.cname $procmux$1694
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:150"
|
||
|
|
.param WIDTH 00000000000000000000000000100000
|
||
|
|
.subckt $pmux A[0]=Wt[0] A[1]=Wt[1] A[2]=Wt[2] A[3]=Wt[3] A[4]=Wt[4] A[5]=Wt[5] A[6]=Wt[6] A[7]=Wt[7] A[8]=Wt[8] A[9]=Wt[9] A[10]=Wt[10] A[11]=Wt[11] A[12]=Wt[12] A[13]=Wt[13] A[14]=Wt[14] A[15]=Wt[15] A[16]=Wt[16] A[17]=Wt[17] A[18]=Wt[18] A[19]=Wt[19] A[20]=Wt[20] A[21]=Wt[21] A[22]=Wt[22] A[23]=Wt[23] A[24]=Wt[24] A[25]=Wt[25] A[26]=Wt[26] A[27]=Wt[27] A[28]=Wt[28] A[29]=Wt[29] A[30]=Wt[30] A[31]=Wt[31] B[0]=next_Wt[0] B[1]=next_Wt[1] B[2]=next_Wt[2] B[3]=next_Wt[3] B[4]=next_Wt[4] B[5]=next_Wt[5] B[6]=next_Wt[6] B[7]=next_Wt[7] B[8]=next_Wt[8] B[9]=next_Wt[9] B[10]=next_Wt[10] B[11]=next_Wt[11] B[12]=next_Wt[12] B[13]=next_Wt[13] B[14]=next_Wt[14] B[15]=next_Wt[15] B[16]=next_Wt[16] B[17]=next_Wt[17] B[18]=next_Wt[18] B[19]=next_Wt[19] B[20]=next_Wt[20] B[21]=next_Wt[21] B[22]=next_Wt[22] B[23]=next_Wt[23] B[24]=next_Wt[24] B[25]=next_Wt[25] B[26]=next_Wt[26] B[27]=next_Wt[27] B[28]=next_Wt[28] B[29]=next_Wt[29] B[30]=next_Wt[30] B[31]=next_Wt[31] B[32]=next_Wt[0] B[33]=next_Wt[1] B[34]=next_Wt[2] B[35]=next_Wt[3] B[36]=next_Wt[4] B[37]=next_Wt[5] B[38]=next_Wt[6] B[39]=next_Wt[7] B[40]=next_Wt[8] B[41]=next_Wt[9] B[42]=next_Wt[10] B[43]=next_Wt[11] B[44]=next_Wt[12] B[45]=next_Wt[13] B[46]=next_Wt[14] B[47]=next_Wt[15] B[48]=next_Wt[16] B[49]=next_Wt[17] B[50]=next_Wt[18] B[51]=next_Wt[19] B[52]=next_Wt[20] B[53]=next_Wt[21] B[54]=next_Wt[22] B[55]=next_Wt[23] B[56]=next_Wt[24] B[57]=next_Wt[25] B[58]=next_Wt[26] B[59]=next_Wt[27] B[60]=next_Wt[28] B[61]=next_Wt[29] B[62]=next_Wt[30] B[63]=next_Wt[31] B[64]=next_Wt[0] B[65]=next_Wt[1] B[66]=next_Wt[2] B[67]=next_Wt[3] B[68]=next_Wt[4] B[69]=next_Wt[5] B[70]=next_Wt[6] B[71]=next_Wt[7] B[72]=next_Wt[8] B[73]=next_Wt[9] B[74]=next_Wt[10] B[75]=next_Wt[11] B[76]=next_Wt[12] B[77]=next_Wt[13] B[78]=next_Wt[14] B[79]=next_Wt[15] B[80]=next_Wt[16] B[81]=next_Wt[17] B[82]=next_Wt[18] B[83]=next_Wt[19] B[84]=next_Wt[20] B[85]=next_Wt[21] B[86]=next_Wt[22] B[87]=next_Wt[23] B[88]=next_Wt[24] B[89]=next_Wt[25] B[90]=next_Wt[26] B[91]=next_Wt[27] B[92]=next_Wt[28] B[93]=next_Wt[29] B[94]=next_Wt[30] B[95]=next_Wt[31] B[96]=next_Wt[0] B[97]=next_Wt[1] B[98]=next_Wt[2] B[99]=next_Wt[3] B[100]=next_Wt[4] B[101]=next_Wt[5] B[102]=next_Wt[6] B[103]=next_Wt[7] B[104]=next_Wt[8] B[105]=next_Wt[9] B[106]=next_Wt[10] B[107]=next_Wt[11] B[108]=next_Wt[12] B[109]=next_Wt[13] B[110]=next_Wt[14] B[111]=next_Wt[15] B[112]=next_Wt[16] B[113]=next_Wt[17] B[114]=next_Wt[18] B[115]=next_Wt[19] B[116]=next_Wt[20] B[117]=next_Wt[21] B[118]=next_Wt[22] B[119]=next_Wt[23] B[120]=next_Wt[24] B[121]=next_Wt[25] B[122]=next_Wt[26] B[123]=next_Wt[27] B[124]=next_Wt[28] B[125]=next_Wt[29] B[126]=next_Wt[30] B[127]=next_Wt[31] B[128]=next_Wt[0] B[129]=next_Wt[1] B[130]=next_Wt[2] B[131]=next_Wt[3] B[132]=next_Wt[4] B[133]=next_Wt[5] B[134]=next_Wt[6] B[135]=next_Wt[7] B[136]=next_Wt[8] B[137]=next_Wt[9] B[138]=next_Wt[10] B[139]=next_Wt[11] B[140]=next_Wt[12] B[141]=next_Wt[13] B[142]=next_Wt[14] B[143]=next_Wt[15] B[144]=next_Wt[16] B[145]=next_Wt[17] B[146]=next_Wt[18] B[147]=next_Wt[19] B[148]=next_Wt[20] B[149]=next_Wt[21] B[150]=next_Wt[22] B[151]=next_Wt[23] B[152]=next_Wt[24] B[153]=next_Wt[25] B[154]=next_Wt[26] B[155]=next_Wt[27] B[156]=next_Wt[28] B[157]=next_Wt[29] B[158]=next_Wt[30] B[159]=next_Wt[31] B[160]=next_Wt[0] B[161]=next_Wt[1] B[162]=next_Wt[2] B[163]=next_Wt[3] B[164]=next_Wt[4] B[165]=next_Wt[5] B[166]=next_Wt[6] B[167]=next_Wt[7] B[168]=next_Wt[8] B[169]=next_Wt[9] B[170]=next_Wt[10] B[171]=next_Wt[11] B[172]=next_Wt[12] B[173]=next_Wt[13] B[174]=next_Wt[14] B[175]=next_Wt[15] B[176]=next_Wt[16] B[177]=next_Wt[17] B[178]=next_Wt[18] B[179]=next_Wt[19] B[180]=next_Wt[20] B[181]=next_Wt[21] B[182]=next_Wt[22] B[183]=next_Wt[23] B[184]=next_Wt[24] B[185]=next_Wt[25] B[186]=next_Wt[26] B[187]=next_Wt[27] B[188]=next_Wt[28] B[189]=next_Wt[29] B[190]=next_Wt[30] B[191]=next_Wt[31] B[192]=next_Wt[0] B[193]=next_Wt[1] B[194]=next_Wt[2] B[195]=next_Wt[3] B[196]=next_Wt[4] B[197]=next_Wt[5] B[198]=next_Wt[6] B[199]=next_Wt[7] B[200]=next_Wt[8] B[201]=next_Wt[9] B[202]=next_Wt[10] B[203]=n
|
||
|
|
.cname $procmux$173
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param S_WIDTH 00000000000000000000000001010000
|
||
|
|
.param WIDTH 00000000000000000000000000100000
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$true B[1]=$true B[2]=$true B[3]=$true B[4]=$false B[5]=$false B[6]=$true Y=$procmux$174_CMP
|
||
|
|
.cname $procmux$174_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$false B[1]=$true B[2]=$true B[3]=$true B[4]=$false B[5]=$false B[6]=$true Y=$procmux$175_CMP
|
||
|
|
.cname $procmux$175_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$true B[1]=$false B[2]=$true B[3]=$true B[4]=$false B[5]=$false B[6]=$true Y=$procmux$176_CMP
|
||
|
|
.cname $procmux$176_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $pmux A[0]=H0[0] A[1]=H0[1] A[2]=H0[2] A[3]=H0[3] A[4]=H0[4] A[5]=H0[5] A[6]=H0[6] A[7]=H0[7] A[8]=H0[8] A[9]=H0[9] A[10]=H0[10] A[11]=H0[11] A[12]=H0[12] A[13]=H0[13] A[14]=H0[14] A[15]=H0[15] A[16]=H0[16] A[17]=H0[17] A[18]=H0[18] A[19]=H0[19] A[20]=H0[20] A[21]=H0[21] A[22]=H0[22] A[23]=H0[23] A[24]=H0[24] A[25]=H0[25] A[26]=H0[26] A[27]=H0[27] A[28]=H0[28] A[29]=H0[29] A[30]=H0[30] A[31]=H0[31] B[0]=A[0] B[1]=A[1] B[2]=A[2] B[3]=A[3] B[4]=A[4] B[5]=A[5] B[6]=A[6] B[7]=A[7] B[8]=A[8] B[9]=A[9] B[10]=A[10] B[11]=A[11] B[12]=A[12] B[13]=A[13] B[14]=A[14] B[15]=A[15] B[16]=A[16] B[17]=A[17] B[18]=A[18] B[19]=A[19] B[20]=A[20] B[21]=A[21] B[22]=A[22] B[23]=A[23] B[24]=A[24] B[25]=A[25] B[26]=A[26] B[27]=A[27] B[28]=A[28] B[29]=A[29] B[30]=A[30] B[31]=A[31] B[32]=$true B[33]=$false B[34]=$false B[35]=$false B[36]=$false B[37]=$false B[38]=$false B[39]=$false B[40]=$true B[41]=$true B[42]=$false B[43]=$false B[44]=$false B[45]=$true B[46]=$false B[47]=$false B[48]=$true B[49]=$false B[50]=$true B[51]=$false B[52]=$false B[53]=$false B[54]=$true B[55]=$false B[56]=$true B[57]=$true B[58]=$true B[59]=$false B[60]=$false B[61]=$true B[62]=$true B[63]=$false S[0]=$procmux$1779_CMP S[1]=$procmux$1780_CMP Y[0]=$procmux$1778_Y[0] Y[1]=$procmux$1778_Y[1] Y[2]=$procmux$1778_Y[2] Y[3]=$procmux$1778_Y[3] Y[4]=$procmux$1778_Y[4] Y[5]=$procmux$1778_Y[5] Y[6]=$procmux$1778_Y[6] Y[7]=$procmux$1778_Y[7] Y[8]=$procmux$1778_Y[8] Y[9]=$procmux$1778_Y[9] Y[10]=$procmux$1778_Y[10] Y[11]=$procmux$1778_Y[11] Y[12]=$procmux$1778_Y[12] Y[13]=$procmux$1778_Y[13] Y[14]=$procmux$1778_Y[14] Y[15]=$procmux$1778_Y[15] Y[16]=$procmux$1778_Y[16] Y[17]=$procmux$1778_Y[17] Y[18]=$procmux$1778_Y[18] Y[19]=$procmux$1778_Y[19] Y[20]=$procmux$1778_Y[20] Y[21]=$procmux$1778_Y[21] Y[22]=$procmux$1778_Y[22] Y[23]=$procmux$1778_Y[23] Y[24]=$procmux$1778_Y[24] Y[25]=$procmux$1778_Y[25] Y[26]=$procmux$1778_Y[26] Y[27]=$procmux$1778_Y[27] Y[28]=$procmux$1778_Y[28] Y[29]=$procmux$1778_Y[29] Y[30]=$procmux$1778_Y[30] Y[31]=$procmux$1778_Y[31]
|
||
|
|
.cname $procmux$1778
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:198"
|
||
|
|
.param S_WIDTH 00000000000000000000000000000010
|
||
|
|
.param WIDTH 00000000000000000000000000100000
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$false B[1]=$false B[2]=$true B[3]=$true B[4]=$false B[5]=$false B[6]=$true Y=$procmux$177_CMP
|
||
|
|
.cname $procmux$177_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A=cmd[2] B=$false Y=$procmux$1780_CMP
|
||
|
|
.cname $procmux$1780_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:198"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000001
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000001
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $mux A[0]=H0[0] A[1]=H0[1] A[2]=H0[2] A[3]=H0[3] A[4]=H0[4] A[5]=H0[5] A[6]=H0[6] A[7]=H0[7] A[8]=H0[8] A[9]=H0[9] A[10]=H0[10] A[11]=H0[11] A[12]=H0[12] A[13]=H0[13] A[14]=H0[14] A[15]=H0[15] A[16]=H0[16] A[17]=H0[17] A[18]=H0[18] A[19]=H0[19] A[20]=H0[20] A[21]=H0[21] A[22]=H0[22] A[23]=H0[23] A[24]=H0[24] A[25]=H0[25] A[26]=H0[26] A[27]=H0[27] A[28]=H0[28] A[29]=H0[29] A[30]=H0[30] A[31]=H0[31] B[0]=$procmux$1778_Y[0] B[1]=$procmux$1778_Y[1] B[2]=$procmux$1778_Y[2] B[3]=$procmux$1778_Y[3] B[4]=$procmux$1778_Y[4] B[5]=$procmux$1778_Y[5] B[6]=$procmux$1778_Y[6] B[7]=$procmux$1778_Y[7] B[8]=$procmux$1778_Y[8] B[9]=$procmux$1778_Y[9] B[10]=$procmux$1778_Y[10] B[11]=$procmux$1778_Y[11] B[12]=$procmux$1778_Y[12] B[13]=$procmux$1778_Y[13] B[14]=$procmux$1778_Y[14] B[15]=$procmux$1778_Y[15] B[16]=$procmux$1778_Y[16] B[17]=$procmux$1778_Y[17] B[18]=$procmux$1778_Y[18] B[19]=$procmux$1778_Y[19] B[20]=$procmux$1778_Y[20] B[21]=$procmux$1778_Y[21] B[22]=$procmux$1778_Y[22] B[23]=$procmux$1778_Y[23] B[24]=$procmux$1778_Y[24] B[25]=$procmux$1778_Y[25] B[26]=$procmux$1778_Y[26] B[27]=$procmux$1778_Y[27] B[28]=$procmux$1778_Y[28] B[29]=$procmux$1778_Y[29] B[30]=$procmux$1778_Y[30] B[31]=$procmux$1778_Y[31] S=$procmux$1782_CMP Y[0]=$procmux$1781_Y[0] Y[1]=$procmux$1781_Y[1] Y[2]=$procmux$1781_Y[2] Y[3]=$procmux$1781_Y[3] Y[4]=$procmux$1781_Y[4] Y[5]=$procmux$1781_Y[5] Y[6]=$procmux$1781_Y[6] Y[7]=$procmux$1781_Y[7] Y[8]=$procmux$1781_Y[8] Y[9]=$procmux$1781_Y[9] Y[10]=$procmux$1781_Y[10] Y[11]=$procmux$1781_Y[11] Y[12]=$procmux$1781_Y[12] Y[13]=$procmux$1781_Y[13] Y[14]=$procmux$1781_Y[14] Y[15]=$procmux$1781_Y[15] Y[16]=$procmux$1781_Y[16] Y[17]=$procmux$1781_Y[17] Y[18]=$procmux$1781_Y[18] Y[19]=$procmux$1781_Y[19] Y[20]=$procmux$1781_Y[20] Y[21]=$procmux$1781_Y[21] Y[22]=$procmux$1781_Y[22] Y[23]=$procmux$1781_Y[23] Y[24]=$procmux$1781_Y[24] Y[25]=$procmux$1781_Y[25] Y[26]=$procmux$1781_Y[26] Y[27]=$procmux$1781_Y[27] Y[28]=$procmux$1781_Y[28] Y[29]=$procmux$1781_Y[29] Y[30]=$procmux$1781_Y[30] Y[31]=$procmux$1781_Y[31]
|
||
|
|
.cname $procmux$1781
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:191"
|
||
|
|
.param WIDTH 00000000000000000000000000100000
|
||
|
|
.subckt $mux A[0]=H0[0] A[1]=H0[1] A[2]=H0[2] A[3]=H0[3] A[4]=H0[4] A[5]=H0[5] A[6]=H0[6] A[7]=H0[7] A[8]=H0[8] A[9]=H0[9] A[10]=H0[10] A[11]=H0[11] A[12]=H0[12] A[13]=H0[13] A[14]=H0[14] A[15]=H0[15] A[16]=H0[16] A[17]=H0[17] A[18]=H0[18] A[19]=H0[19] A[20]=H0[20] A[21]=H0[21] A[22]=H0[22] A[23]=H0[23] A[24]=H0[24] A[25]=H0[25] A[26]=H0[26] A[27]=H0[27] A[28]=H0[28] A[29]=H0[29] A[30]=H0[30] A[31]=H0[31] B[0]=$procmux$1781_Y[0] B[1]=$procmux$1781_Y[1] B[2]=$procmux$1781_Y[2] B[3]=$procmux$1781_Y[3] B[4]=$procmux$1781_Y[4] B[5]=$procmux$1781_Y[5] B[6]=$procmux$1781_Y[6] B[7]=$procmux$1781_Y[7] B[8]=$procmux$1781_Y[8] B[9]=$procmux$1781_Y[9] B[10]=$procmux$1781_Y[10] B[11]=$procmux$1781_Y[11] B[12]=$procmux$1781_Y[12] B[13]=$procmux$1781_Y[13] B[14]=$procmux$1781_Y[14] B[15]=$procmux$1781_Y[15] B[16]=$procmux$1781_Y[16] B[17]=$procmux$1781_Y[17] B[18]=$procmux$1781_Y[18] B[19]=$procmux$1781_Y[19] B[20]=$procmux$1781_Y[20] B[21]=$procmux$1781_Y[21] B[22]=$procmux$1781_Y[22] B[23]=$procmux$1781_Y[23] B[24]=$procmux$1781_Y[24] B[25]=$procmux$1781_Y[25] B[26]=$procmux$1781_Y[26] B[27]=$procmux$1781_Y[27] B[28]=$procmux$1781_Y[28] B[29]=$procmux$1781_Y[29] B[30]=$procmux$1781_Y[30] B[31]=$procmux$1781_Y[31] S=$procmux$1784_CMP Y[0]=$procmux$1783_Y[0] Y[1]=$procmux$1783_Y[1] Y[2]=$procmux$1783_Y[2] Y[3]=$procmux$1783_Y[3] Y[4]=$procmux$1783_Y[4] Y[5]=$procmux$1783_Y[5] Y[6]=$procmux$1783_Y[6] Y[7]=$procmux$1783_Y[7] Y[8]=$procmux$1783_Y[8] Y[9]=$procmux$1783_Y[9] Y[10]=$procmux$1783_Y[10] Y[11]=$procmux$1783_Y[11] Y[12]=$procmux$1783_Y[12] Y[13]=$procmux$1783_Y[13] Y[14]=$procmux$1783_Y[14] Y[15]=$procmux$1783_Y[15] Y[16]=$procmux$1783_Y[16] Y[17]=$procmux$1783_Y[17] Y[18]=$procmux$1783_Y[18] Y[19]=$procmux$1783_Y[19] Y[20]=$procmux$1783_Y[20] Y[21]=$procmux$1783_Y[21] Y[22]=$procmux$1783_Y[22] Y[23]=$procmux$1783_Y[23] Y[24]=$procmux$1783_Y[24] Y[25]=$procmux$1783_Y[25] Y[26]=$procmux$1783_Y[26] Y[27]=$procmux$1783_Y[27] Y[28]=$procmux$1783_Y[28] Y[29]=$procmux$1783_Y[29] Y[30]=$procmux$1783_Y[30] Y[31]=$procmux$1783_Y[31]
|
||
|
|
.cname $procmux$1783
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param WIDTH 00000000000000000000000000100000
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$false B[1]=$false B[2]=$false B[3]=$false B[4]=$false B[5]=$false B[6]=$false Y=$procmux$1784_CMP
|
||
|
|
.cname $procmux$1784_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $mux A[0]=$procmux$1783_Y[0] A[1]=$procmux$1783_Y[1] A[2]=$procmux$1783_Y[2] A[3]=$procmux$1783_Y[3] A[4]=$procmux$1783_Y[4] A[5]=$procmux$1783_Y[5] A[6]=$procmux$1783_Y[6] A[7]=$procmux$1783_Y[7] A[8]=$procmux$1783_Y[8] A[9]=$procmux$1783_Y[9] A[10]=$procmux$1783_Y[10] A[11]=$procmux$1783_Y[11] A[12]=$procmux$1783_Y[12] A[13]=$procmux$1783_Y[13] A[14]=$procmux$1783_Y[14] A[15]=$procmux$1783_Y[15] A[16]=$procmux$1783_Y[16] A[17]=$procmux$1783_Y[17] A[18]=$procmux$1783_Y[18] A[19]=$procmux$1783_Y[19] A[20]=$procmux$1783_Y[20] A[21]=$procmux$1783_Y[21] A[22]=$procmux$1783_Y[22] A[23]=$procmux$1783_Y[23] A[24]=$procmux$1783_Y[24] A[25]=$procmux$1783_Y[25] A[26]=$procmux$1783_Y[26] A[27]=$procmux$1783_Y[27] A[28]=$procmux$1783_Y[28] A[29]=$procmux$1783_Y[29] A[30]=$procmux$1783_Y[30] A[31]=$procmux$1783_Y[31] B[0]=$false B[1]=$false B[2]=$false B[3]=$false B[4]=$false B[5]=$false B[6]=$false B[7]=$false B[8]=$false B[9]=$false B[10]=$false B[11]=$false B[12]=$false B[13]=$false B[14]=$false B[15]=$false B[16]=$false B[17]=$false B[18]=$false B[19]=$false B[20]=$false B[21]=$false B[22]=$false B[23]=$false B[24]=$false B[25]=$false B[26]=$false B[27]=$false B[28]=$false B[29]=$false B[30]=$false B[31]=$false S=$procmux$1787_CMP Y[0]=$procmux$1786_Y[0] Y[1]=$procmux$1786_Y[1] Y[2]=$procmux$1786_Y[2] Y[3]=$procmux$1786_Y[3] Y[4]=$procmux$1786_Y[4] Y[5]=$procmux$1786_Y[5] Y[6]=$procmux$1786_Y[6] Y[7]=$procmux$1786_Y[7] Y[8]=$procmux$1786_Y[8] Y[9]=$procmux$1786_Y[9] Y[10]=$procmux$1786_Y[10] Y[11]=$procmux$1786_Y[11] Y[12]=$procmux$1786_Y[12] Y[13]=$procmux$1786_Y[13] Y[14]=$procmux$1786_Y[14] Y[15]=$procmux$1786_Y[15] Y[16]=$procmux$1786_Y[16] Y[17]=$procmux$1786_Y[17] Y[18]=$procmux$1786_Y[18] Y[19]=$procmux$1786_Y[19] Y[20]=$procmux$1786_Y[20] Y[21]=$procmux$1786_Y[21] Y[22]=$procmux$1786_Y[22] Y[23]=$procmux$1786_Y[23] Y[24]=$procmux$1786_Y[24] Y[25]=$procmux$1786_Y[25] Y[26]=$procmux$1786_Y[26] Y[27]=$procmux$1786_Y[27] Y[28]=$procmux$1786_Y[28] Y[29]=$procmux$1786_Y[29] Y[30]=$procmux$1786_Y[30] Y[31]=$procmux$1786_Y[31]
|
||
|
|
.cname $procmux$1786
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:150"
|
||
|
|
.param WIDTH 00000000000000000000000000100000
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$true B[1]=$true B[2]=$false B[3]=$true B[4]=$false B[5]=$false B[6]=$true Y=$procmux$178_CMP
|
||
|
|
.cname $procmux$178_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $pmux A[0]=$false A[1]=$false A[2]=$false A[3]=$false A[4]=$false A[5]=$false A[6]=$false B[0]=round_plus_1[0] B[1]=round_plus_1[1] B[2]=round_plus_1[2] B[3]=round_plus_1[3] B[4]=round_plus_1[4] B[5]=round_plus_1[5] B[6]=round_plus_1[6] B[7]=round_plus_1[0] B[8]=round_plus_1[1] B[9]=round_plus_1[2] B[10]=round_plus_1[3] B[11]=round_plus_1[4] B[12]=round_plus_1[5] B[13]=round_plus_1[6] B[14]=round_plus_1[0] B[15]=round_plus_1[1] B[16]=round_plus_1[2] B[17]=round_plus_1[3] B[18]=round_plus_1[4] B[19]=round_plus_1[5] B[20]=round_plus_1[6] B[21]=round_plus_1[0] B[22]=round_plus_1[1] B[23]=round_plus_1[2] B[24]=round_plus_1[3] B[25]=round_plus_1[4] B[26]=round_plus_1[5] B[27]=round_plus_1[6] B[28]=round_plus_1[0] B[29]=round_plus_1[1] B[30]=round_plus_1[2] B[31]=round_plus_1[3] B[32]=round_plus_1[4] B[33]=round_plus_1[5] B[34]=round_plus_1[6] B[35]=round_plus_1[0] B[36]=round_plus_1[1] B[37]=round_plus_1[2] B[38]=round_plus_1[3] B[39]=round_plus_1[4] B[40]=round_plus_1[5] B[41]=round_plus_1[6] B[42]=round_plus_1[0] B[43]=round_plus_1[1] B[44]=round_plus_1[2] B[45]=round_plus_1[3] B[46]=round_plus_1[4] B[47]=round_plus_1[5] B[48]=round_plus_1[6] B[49]=round_plus_1[0] B[50]=round_plus_1[1] B[51]=round_plus_1[2] B[52]=round_plus_1[3] B[53]=round_plus_1[4] B[54]=round_plus_1[5] B[55]=round_plus_1[6] B[56]=round_plus_1[0] B[57]=round_plus_1[1] B[58]=round_plus_1[2] B[59]=round_plus_1[3] B[60]=round_plus_1[4] B[61]=round_plus_1[5] B[62]=round_plus_1[6] B[63]=round_plus_1[0] B[64]=round_plus_1[1] B[65]=round_plus_1[2] B[66]=round_plus_1[3] B[67]=round_plus_1[4] B[68]=round_plus_1[5] B[69]=round_plus_1[6] B[70]=round_plus_1[0] B[71]=round_plus_1[1] B[72]=round_plus_1[2] B[73]=round_plus_1[3] B[74]=round_plus_1[4] B[75]=round_plus_1[5] B[76]=round_plus_1[6] B[77]=round_plus_1[0] B[78]=round_plus_1[1] B[79]=round_plus_1[2] B[80]=round_plus_1[3] B[81]=round_plus_1[4] B[82]=round_plus_1[5] B[83]=round_plus_1[6] B[84]=round_plus_1[0] B[85]=round_plus_1[1] B[86]=round_plus_1[2] B[87]=round_plus_1[3] B[88]=round_plus_1[4] B[89]=round_plus_1[5] B[90]=round_plus_1[6] B[91]=round_plus_1[0] B[92]=round_plus_1[1] B[93]=round_plus_1[2] B[94]=round_plus_1[3] B[95]=round_plus_1[4] B[96]=round_plus_1[5] B[97]=round_plus_1[6] B[98]=round_plus_1[0] B[99]=round_plus_1[1] B[100]=round_plus_1[2] B[101]=round_plus_1[3] B[102]=round_plus_1[4] B[103]=round_plus_1[5] B[104]=round_plus_1[6] B[105]=round_plus_1[0] B[106]=round_plus_1[1] B[107]=round_plus_1[2] B[108]=round_plus_1[3] B[109]=round_plus_1[4] B[110]=round_plus_1[5] B[111]=round_plus_1[6] B[112]=round_plus_1[0] B[113]=round_plus_1[1] B[114]=round_plus_1[2] B[115]=round_plus_1[3] B[116]=round_plus_1[4] B[117]=round_plus_1[5] B[118]=round_plus_1[6] B[119]=round_plus_1[0] B[120]=round_plus_1[1] B[121]=round_plus_1[2] B[122]=round_plus_1[3] B[123]=round_plus_1[4] B[124]=round_plus_1[5] B[125]=round_plus_1[6] B[126]=round_plus_1[0] B[127]=round_plus_1[1] B[128]=round_plus_1[2] B[129]=round_plus_1[3] B[130]=round_plus_1[4] B[131]=round_plus_1[5] B[132]=round_plus_1[6] B[133]=round_plus_1[0] B[134]=round_plus_1[1] B[135]=round_plus_1[2] B[136]=round_plus_1[3] B[137]=round_plus_1[4] B[138]=round_plus_1[5] B[139]=round_plus_1[6] B[140]=round_plus_1[0] B[141]=round_plus_1[1] B[142]=round_plus_1[2] B[143]=round_plus_1[3] B[144]=round_plus_1[4] B[145]=round_plus_1[5] B[146]=round_plus_1[6] B[147]=round_plus_1[0] B[148]=round_plus_1[1] B[149]=round_plus_1[2] B[150]=round_plus_1[3] B[151]=round_plus_1[4] B[152]=round_plus_1[5] B[153]=round_plus_1[6] B[154]=round_plus_1[0] B[155]=round_plus_1[1] B[156]=round_plus_1[2] B[157]=round_plus_1[3] B[158]=round_plus_1[4] B[159]=round_plus_1[5] B[160]=round_plus_1[6] B[161]=round_plus_1[0] B[162]=round_plus_1[1] B[163]=round_plus_1[2] B[164]=round_plus_1[3] B[165]=round_plus_1[4] B[166]=round_plus_1[5] B[167]=round_plus_1[6] B[168]=round_plus_1[0] B[169]=round_plus_1[1] B[170]=round_plus_1[2] B[171]=round_plus_1[3] B[172]=round_plus_1[4] B[173]=round_plus_1[5] B[174]=round_plus_1[6] B[175]=round_plus_1[0] B[176]=round_plus_1[1] B[177]=round_plus_1[2] B[178]=round_
|
||
|
|
.cname $procmux$1790
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param S_WIDTH 00000000000000000000000001010000
|
||
|
|
.param WIDTH 00000000000000000000000000000111
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$true B[1]=$true B[2]=$true B[3]=$true B[4]=$false B[5]=$false B[6]=$true Y=$procmux$1791_CMP
|
||
|
|
.cname $procmux$1791_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$false B[1]=$true B[2]=$true B[3]=$true B[4]=$false B[5]=$false B[6]=$true Y=$procmux$1792_CMP
|
||
|
|
.cname $procmux$1792_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$true B[1]=$false B[2]=$true B[3]=$true B[4]=$false B[5]=$false B[6]=$true Y=$procmux$1793_CMP
|
||
|
|
.cname $procmux$1793_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$false B[1]=$false B[2]=$true B[3]=$true B[4]=$false B[5]=$false B[6]=$true Y=$procmux$1794_CMP
|
||
|
|
.cname $procmux$1794_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$true B[1]=$true B[2]=$false B[3]=$true B[4]=$false B[5]=$false B[6]=$true Y=$procmux$1795_CMP
|
||
|
|
.cname $procmux$1795_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$false B[1]=$true B[2]=$false B[3]=$true B[4]=$false B[5]=$false B[6]=$true Y=$procmux$1796_CMP
|
||
|
|
.cname $procmux$1796_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$true B[1]=$false B[2]=$false B[3]=$true B[4]=$false B[5]=$false B[6]=$true Y=$procmux$1797_CMP
|
||
|
|
.cname $procmux$1797_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$false B[1]=$false B[2]=$false B[3]=$true B[4]=$false B[5]=$false B[6]=$true Y=$procmux$1798_CMP
|
||
|
|
.cname $procmux$1798_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$true B[1]=$true B[2]=$true B[3]=$false B[4]=$false B[5]=$false B[6]=$true Y=$procmux$1799_CMP
|
||
|
|
.cname $procmux$1799_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$false B[1]=$true B[2]=$false B[3]=$true B[4]=$false B[5]=$false B[6]=$true Y=$procmux$179_CMP
|
||
|
|
.cname $procmux$179_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$false B[1]=$true B[2]=$true B[3]=$false B[4]=$false B[5]=$false B[6]=$true Y=$procmux$1800_CMP
|
||
|
|
.cname $procmux$1800_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$true B[1]=$false B[2]=$true B[3]=$false B[4]=$false B[5]=$false B[6]=$true Y=$procmux$1801_CMP
|
||
|
|
.cname $procmux$1801_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$false B[1]=$false B[2]=$true B[3]=$false B[4]=$false B[5]=$false B[6]=$true Y=$procmux$1802_CMP
|
||
|
|
.cname $procmux$1802_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$true B[1]=$true B[2]=$false B[3]=$false B[4]=$false B[5]=$false B[6]=$true Y=$procmux$1803_CMP
|
||
|
|
.cname $procmux$1803_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$false B[1]=$true B[2]=$false B[3]=$false B[4]=$false B[5]=$false B[6]=$true Y=$procmux$1804_CMP
|
||
|
|
.cname $procmux$1804_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$true B[1]=$false B[2]=$false B[3]=$false B[4]=$false B[5]=$false B[6]=$true Y=$procmux$1805_CMP
|
||
|
|
.cname $procmux$1805_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$false B[1]=$false B[2]=$false B[3]=$false B[4]=$false B[5]=$false B[6]=$true Y=$procmux$1806_CMP
|
||
|
|
.cname $procmux$1806_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$true B[1]=$true B[2]=$true B[3]=$true B[4]=$true B[5]=$true B[6]=$false Y=$procmux$1807_CMP
|
||
|
|
.cname $procmux$1807_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$false B[1]=$true B[2]=$true B[3]=$true B[4]=$true B[5]=$true B[6]=$false Y=$procmux$1808_CMP
|
||
|
|
.cname $procmux$1808_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$true B[1]=$false B[2]=$true B[3]=$true B[4]=$true B[5]=$true B[6]=$false Y=$procmux$1809_CMP
|
||
|
|
.cname $procmux$1809_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$true B[1]=$false B[2]=$false B[3]=$true B[4]=$false B[5]=$false B[6]=$true Y=$procmux$180_CMP
|
||
|
|
.cname $procmux$180_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$false B[1]=$false B[2]=$true B[3]=$true B[4]=$true B[5]=$true B[6]=$false Y=$procmux$1810_CMP
|
||
|
|
.cname $procmux$1810_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$true B[1]=$true B[2]=$false B[3]=$true B[4]=$true B[5]=$true B[6]=$false Y=$procmux$1811_CMP
|
||
|
|
.cname $procmux$1811_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$false B[1]=$true B[2]=$false B[3]=$true B[4]=$true B[5]=$true B[6]=$false Y=$procmux$1812_CMP
|
||
|
|
.cname $procmux$1812_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$true B[1]=$false B[2]=$false B[3]=$true B[4]=$true B[5]=$true B[6]=$false Y=$procmux$1813_CMP
|
||
|
|
.cname $procmux$1813_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$false B[1]=$false B[2]=$false B[3]=$true B[4]=$true B[5]=$true B[6]=$false Y=$procmux$1814_CMP
|
||
|
|
.cname $procmux$1814_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$true B[1]=$true B[2]=$true B[3]=$false B[4]=$true B[5]=$true B[6]=$false Y=$procmux$1815_CMP
|
||
|
|
.cname $procmux$1815_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$false B[1]=$true B[2]=$true B[3]=$false B[4]=$true B[5]=$true B[6]=$false Y=$procmux$1816_CMP
|
||
|
|
.cname $procmux$1816_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$true B[1]=$false B[2]=$true B[3]=$false B[4]=$true B[5]=$true B[6]=$false Y=$procmux$1817_CMP
|
||
|
|
.cname $procmux$1817_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$false B[1]=$false B[2]=$true B[3]=$false B[4]=$true B[5]=$true B[6]=$false Y=$procmux$1818_CMP
|
||
|
|
.cname $procmux$1818_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$true B[1]=$true B[2]=$false B[3]=$false B[4]=$true B[5]=$true B[6]=$false Y=$procmux$1819_CMP
|
||
|
|
.cname $procmux$1819_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$false B[1]=$false B[2]=$false B[3]=$true B[4]=$false B[5]=$false B[6]=$true Y=$procmux$181_CMP
|
||
|
|
.cname $procmux$181_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$false B[1]=$true B[2]=$false B[3]=$false B[4]=$true B[5]=$true B[6]=$false Y=$procmux$1820_CMP
|
||
|
|
.cname $procmux$1820_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$true B[1]=$false B[2]=$false B[3]=$false B[4]=$true B[5]=$true B[6]=$false Y=$procmux$1821_CMP
|
||
|
|
.cname $procmux$1821_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$false B[1]=$false B[2]=$false B[3]=$false B[4]=$true B[5]=$true B[6]=$false Y=$procmux$1822_CMP
|
||
|
|
.cname $procmux$1822_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$true B[1]=$true B[2]=$true B[3]=$true B[4]=$false B[5]=$true B[6]=$false Y=$procmux$1823_CMP
|
||
|
|
.cname $procmux$1823_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$false B[1]=$true B[2]=$true B[3]=$true B[4]=$false B[5]=$true B[6]=$false Y=$procmux$1824_CMP
|
||
|
|
.cname $procmux$1824_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$true B[1]=$false B[2]=$true B[3]=$true B[4]=$false B[5]=$true B[6]=$false Y=$procmux$1825_CMP
|
||
|
|
.cname $procmux$1825_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$false B[1]=$false B[2]=$true B[3]=$true B[4]=$false B[5]=$true B[6]=$false Y=$procmux$1826_CMP
|
||
|
|
.cname $procmux$1826_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$true B[1]=$true B[2]=$false B[3]=$true B[4]=$false B[5]=$true B[6]=$false Y=$procmux$1827_CMP
|
||
|
|
.cname $procmux$1827_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$false B[1]=$true B[2]=$false B[3]=$true B[4]=$false B[5]=$true B[6]=$false Y=$procmux$1828_CMP
|
||
|
|
.cname $procmux$1828_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$true B[1]=$false B[2]=$false B[3]=$true B[4]=$false B[5]=$true B[6]=$false Y=$procmux$1829_CMP
|
||
|
|
.cname $procmux$1829_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$true B[1]=$true B[2]=$true B[3]=$false B[4]=$false B[5]=$false B[6]=$true Y=$procmux$182_CMP
|
||
|
|
.cname $procmux$182_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$false B[1]=$false B[2]=$false B[3]=$true B[4]=$false B[5]=$true B[6]=$false Y=$procmux$1830_CMP
|
||
|
|
.cname $procmux$1830_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$true B[1]=$true B[2]=$true B[3]=$false B[4]=$false B[5]=$true B[6]=$false Y=$procmux$1831_CMP
|
||
|
|
.cname $procmux$1831_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$false B[1]=$true B[2]=$true B[3]=$false B[4]=$false B[5]=$true B[6]=$false Y=$procmux$1832_CMP
|
||
|
|
.cname $procmux$1832_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$true B[1]=$false B[2]=$true B[3]=$false B[4]=$false B[5]=$true B[6]=$false Y=$procmux$1833_CMP
|
||
|
|
.cname $procmux$1833_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$false B[1]=$false B[2]=$true B[3]=$false B[4]=$false B[5]=$true B[6]=$false Y=$procmux$1834_CMP
|
||
|
|
.cname $procmux$1834_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$true B[1]=$true B[2]=$false B[3]=$false B[4]=$false B[5]=$true B[6]=$false Y=$procmux$1835_CMP
|
||
|
|
.cname $procmux$1835_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$false B[1]=$true B[2]=$false B[3]=$false B[4]=$false B[5]=$true B[6]=$false Y=$procmux$1836_CMP
|
||
|
|
.cname $procmux$1836_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$true B[1]=$false B[2]=$false B[3]=$false B[4]=$false B[5]=$true B[6]=$false Y=$procmux$1837_CMP
|
||
|
|
.cname $procmux$1837_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$false B[1]=$false B[2]=$false B[3]=$false B[4]=$false B[5]=$true B[6]=$false Y=$procmux$1838_CMP
|
||
|
|
.cname $procmux$1838_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$true B[1]=$true B[2]=$true B[3]=$true B[4]=$true B[5]=$false B[6]=$false Y=$procmux$1839_CMP
|
||
|
|
.cname $procmux$1839_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$false B[1]=$true B[2]=$true B[3]=$false B[4]=$false B[5]=$false B[6]=$true Y=$procmux$183_CMP
|
||
|
|
.cname $procmux$183_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$false B[1]=$true B[2]=$true B[3]=$true B[4]=$true B[5]=$false B[6]=$false Y=$procmux$1840_CMP
|
||
|
|
.cname $procmux$1840_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$true B[1]=$false B[2]=$true B[3]=$true B[4]=$true B[5]=$false B[6]=$false Y=$procmux$1841_CMP
|
||
|
|
.cname $procmux$1841_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$false B[1]=$false B[2]=$true B[3]=$true B[4]=$true B[5]=$false B[6]=$false Y=$procmux$1842_CMP
|
||
|
|
.cname $procmux$1842_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$true B[1]=$true B[2]=$false B[3]=$true B[4]=$true B[5]=$false B[6]=$false Y=$procmux$1843_CMP
|
||
|
|
.cname $procmux$1843_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$false B[1]=$true B[2]=$false B[3]=$true B[4]=$true B[5]=$false B[6]=$false Y=$procmux$1844_CMP
|
||
|
|
.cname $procmux$1844_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$true B[1]=$false B[2]=$false B[3]=$true B[4]=$true B[5]=$false B[6]=$false Y=$procmux$1845_CMP
|
||
|
|
.cname $procmux$1845_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$false B[1]=$false B[2]=$false B[3]=$true B[4]=$true B[5]=$false B[6]=$false Y=$procmux$1846_CMP
|
||
|
|
.cname $procmux$1846_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$true B[1]=$true B[2]=$true B[3]=$false B[4]=$true B[5]=$false B[6]=$false Y=$procmux$1847_CMP
|
||
|
|
.cname $procmux$1847_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$false B[1]=$true B[2]=$true B[3]=$false B[4]=$true B[5]=$false B[6]=$false Y=$procmux$1848_CMP
|
||
|
|
.cname $procmux$1848_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$true B[1]=$false B[2]=$true B[3]=$false B[4]=$true B[5]=$false B[6]=$false Y=$procmux$1849_CMP
|
||
|
|
.cname $procmux$1849_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$true B[1]=$false B[2]=$true B[3]=$false B[4]=$false B[5]=$false B[6]=$true Y=$procmux$184_CMP
|
||
|
|
.cname $procmux$184_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$false B[1]=$false B[2]=$true B[3]=$false B[4]=$true B[5]=$false B[6]=$false Y=$procmux$1850_CMP
|
||
|
|
.cname $procmux$1850_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$true B[1]=$true B[2]=$false B[3]=$false B[4]=$true B[5]=$false B[6]=$false Y=$procmux$1851_CMP
|
||
|
|
.cname $procmux$1851_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$false B[1]=$true B[2]=$false B[3]=$false B[4]=$true B[5]=$false B[6]=$false Y=$procmux$1852_CMP
|
||
|
|
.cname $procmux$1852_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$true B[1]=$false B[2]=$false B[3]=$false B[4]=$true B[5]=$false B[6]=$false Y=$procmux$1853_CMP
|
||
|
|
.cname $procmux$1853_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$false B[1]=$false B[2]=$false B[3]=$false B[4]=$true B[5]=$false B[6]=$false Y=$procmux$1854_CMP
|
||
|
|
.cname $procmux$1854_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$true B[1]=$true B[2]=$true B[3]=$true B[4]=$false B[5]=$false B[6]=$false Y=$procmux$1855_CMP
|
||
|
|
.cname $procmux$1855_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$false B[1]=$true B[2]=$true B[3]=$true B[4]=$false B[5]=$false B[6]=$false Y=$procmux$1856_CMP
|
||
|
|
.cname $procmux$1856_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$true B[1]=$false B[2]=$true B[3]=$true B[4]=$false B[5]=$false B[6]=$false Y=$procmux$1857_CMP
|
||
|
|
.cname $procmux$1857_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$false B[1]=$false B[2]=$true B[3]=$true B[4]=$false B[5]=$false B[6]=$false Y=$procmux$1858_CMP
|
||
|
|
.cname $procmux$1858_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$true B[1]=$true B[2]=$false B[3]=$true B[4]=$false B[5]=$false B[6]=$false Y=$procmux$1859_CMP
|
||
|
|
.cname $procmux$1859_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$false B[1]=$false B[2]=$true B[3]=$false B[4]=$false B[5]=$false B[6]=$true Y=$procmux$185_CMP
|
||
|
|
.cname $procmux$185_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$false B[1]=$true B[2]=$false B[3]=$true B[4]=$false B[5]=$false B[6]=$false Y=$procmux$1860_CMP
|
||
|
|
.cname $procmux$1860_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$true B[1]=$false B[2]=$false B[3]=$true B[4]=$false B[5]=$false B[6]=$false Y=$procmux$1861_CMP
|
||
|
|
.cname $procmux$1861_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$false B[1]=$false B[2]=$false B[3]=$true B[4]=$false B[5]=$false B[6]=$false Y=$procmux$1862_CMP
|
||
|
|
.cname $procmux$1862_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$true B[1]=$true B[2]=$true B[3]=$false B[4]=$false B[5]=$false B[6]=$false Y=$procmux$1863_CMP
|
||
|
|
.cname $procmux$1863_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$false B[1]=$true B[2]=$true B[3]=$false B[4]=$false B[5]=$false B[6]=$false Y=$procmux$1864_CMP
|
||
|
|
.cname $procmux$1864_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$true B[1]=$false B[2]=$true B[3]=$false B[4]=$false B[5]=$false B[6]=$false Y=$procmux$1865_CMP
|
||
|
|
.cname $procmux$1865_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$false B[1]=$false B[2]=$true B[3]=$false B[4]=$false B[5]=$false B[6]=$false Y=$procmux$1866_CMP
|
||
|
|
.cname $procmux$1866_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$true B[1]=$true B[2]=$false B[3]=$false B[4]=$false B[5]=$false B[6]=$false Y=$procmux$1867_CMP
|
||
|
|
.cname $procmux$1867_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$false B[1]=$true B[2]=$false B[3]=$false B[4]=$false B[5]=$false B[6]=$false Y=$procmux$1868_CMP
|
||
|
|
.cname $procmux$1868_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$true B[1]=$false B[2]=$false B[3]=$false B[4]=$false B[5]=$false B[6]=$false Y=$procmux$1869_CMP
|
||
|
|
.cname $procmux$1869_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$true B[1]=$true B[2]=$false B[3]=$false B[4]=$false B[5]=$false B[6]=$true Y=$procmux$186_CMP
|
||
|
|
.cname $procmux$186_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $mux A[0]=$false A[1]=$false A[2]=$false A[3]=$false A[4]=$false A[5]=$false A[6]=$false B[0]=round_plus_1[0] B[1]=round_plus_1[1] B[2]=round_plus_1[2] B[3]=round_plus_1[3] B[4]=round_plus_1[4] B[5]=round_plus_1[5] B[6]=round_plus_1[6] S=$procmux$1872_CMP Y[0]=$procmux$1871_Y[0] Y[1]=$procmux$1871_Y[1] Y[2]=$procmux$1871_Y[2] Y[3]=$procmux$1871_Y[3] Y[4]=$procmux$1871_Y[4] Y[5]=$procmux$1871_Y[5] Y[6]=$procmux$1871_Y[6]
|
||
|
|
.cname $procmux$1871
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:191"
|
||
|
|
.param WIDTH 00000000000000000000000000000111
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$false B[1]=$false B[2]=$false B[3]=$false B[4]=$false B[5]=$false B[6]=$false Y=$procmux$1873_CMP
|
||
|
|
.cname $procmux$1873_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $mux A[0]=$procmux$1790_Y[0] A[1]=$procmux$1790_Y[1] A[2]=$procmux$1790_Y[2] A[3]=$procmux$1790_Y[3] A[4]=$procmux$1790_Y[4] A[5]=$procmux$1790_Y[5] A[6]=$procmux$1790_Y[6] B[0]=$false B[1]=$false B[2]=$false B[3]=$false B[4]=$false B[5]=$false B[6]=$false S=$procmux$1876_CMP Y[0]=$procmux$1875_Y[0] Y[1]=$procmux$1875_Y[1] Y[2]=$procmux$1875_Y[2] Y[3]=$procmux$1875_Y[3] Y[4]=$procmux$1875_Y[4] Y[5]=$procmux$1875_Y[5] Y[6]=$procmux$1875_Y[6]
|
||
|
|
.cname $procmux$1875
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:150"
|
||
|
|
.param WIDTH 00000000000000000000000000000111
|
||
|
|
.subckt $pmux A[0]=E[0] A[1]=E[1] A[2]=E[2] A[3]=E[3] A[4]=E[4] A[5]=E[5] A[6]=E[6] A[7]=E[7] A[8]=E[8] A[9]=E[9] A[10]=E[10] A[11]=E[11] A[12]=E[12] A[13]=E[13] A[14]=E[14] A[15]=E[15] A[16]=E[16] A[17]=E[17] A[18]=E[18] A[19]=E[19] A[20]=E[20] A[21]=E[21] A[22]=E[22] A[23]=E[23] A[24]=E[24] A[25]=E[25] A[26]=E[26] A[27]=E[27] A[28]=E[28] A[29]=E[29] A[30]=E[30] A[31]=E[31] B[0]=$add$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:2093$33_Y[0] B[1]=$add$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:2093$33_Y[1] B[2]=$add$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:2093$33_Y[2] B[3]=$add$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:2093$33_Y[3] B[4]=$add$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:2093$33_Y[4] B[5]=$add$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:2093$33_Y[5] B[6]=$add$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:2093$33_Y[6] B[7]=$add$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:2093$33_Y[7] B[8]=$add$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:2093$33_Y[8] B[9]=$add$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:2093$33_Y[9] B[10]=$add$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:2093$33_Y[10] B[11]=$add$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:2093$33_Y[11] B[12]=$add$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:2093$33_Y[12] B[13]=$add$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:2093$33_Y[13] B[14]=$add$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:2093$33_Y[14] B[15]=$add$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:2093$33_Y[15] B[16]=$add$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:2093$33_Y[16] B[17]=$add$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:2093$33_Y[17] B[18]=$add$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:2093$33_Y[18] B[19]=$add$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:2093$33_Y[19] B[20]=$add$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:2093$33_Y[20] B[21]=$add$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:2093$33_Y[21] B[22]=$add$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:2093$33_Y[22] B[23]=$add$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:2093$33_Y[23] B[24]=$add$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:2093$33_Y[24] B[25]=$add$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:2093$33_Y[25] B[26]=$add$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:2093$33_Y[26] B[27]=$add$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:2093$33_Y[27] B[28]=$add$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:2093$33_Y[28] B[29]=$add$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:2093$33_Y[29] B[30]=$add$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:2093$33_Y[30] B[31]=$add$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:2093$33_Y[31] B[32]=D[0] B[33]=D[1] B[34]=D[2] B[35]=D[3] B[36]=D[4] B[37]=D[5] B[38]=D[6] B[39]=D[7] B[40]=D[8] B[41]=D[9] B[42]=D[10] B[43]=D[11] B[44]=D[12] B[45]=D[13] B[46]=D[14] B[47]=D[15] B[48]=D[16] B[49]=D[17] B[50]=D[18] B[51]=D[19] B[52]=D[20] B[53]=D[21] B[54]=D[22] B[55]=D[23] B[56]=D[24] B[57]=D[25] B[58]=D[26] B[59]=D[27] B[60]=D[28] B[61]=D[29] B[62]=D[30] B[63]=D[31] B[64]=D[0] B[65]=D[1] B[66]=D[2] B[67]=D[3] B[68]=D[4] B[69]=D[5] B[70]=D[6] B[71]=D[7] B[72]=D[8] B[73]=D[9] B[74]=D[10] B[75]=D[11] B[76]=D[12] B[77]=D[13] B[78]=D[14] B[79]=D[15] B[80]=D[16] B[81]=D[17] B[82]=D[18] B[83]=D[19] B[84]=D[20] B[85]=D[21] B[86]=D[22] B[87]=D[23] B[88]=D[24] B[89]=D[25] B[90]=D[26] B[91]=D[27] B[92]=D[28] B[93]=D[29] B[94]=D[30] B[95]=D[31] B[96]=D[0] B[97]=D[1] B[98]=D[2] B[99]=D[3] B[100]=D[4] B[101]=D[5] B[102]=D[6] B[103]=D[7] B[104]=D[8] B[105]=D[9] B[106]=D[10] B[107]=D[11] B[108]=D[12] B[109]=D[13] B[110]=D[14] B[111]=D[15] B[112]=D[16] B[113]=D[17] B[114]=D[18] B[115]=D[19] B[116]=D[20] B[117]=D[21] B[118]=D[22] B[119]=D[23] B[120]=D[24] B[121]=D[25] B[122]=D[26] B[123]=D[27] B[124]=D[28] B[125]=D[29] B[126]=D[30] B[127]=D[31] B[128]=D[0] B[129]=D[1] B[130]=D[2] B[131]=D[3] B[132]=D[4] B[133]=D[5] B[134]=D[6] B[135]=
|
||
|
|
.cname $procmux$1878
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param S_WIDTH 00000000000000000000000001010001
|
||
|
|
.param WIDTH 00000000000000000000000000100000
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$false B[1]=$false B[2]=$false B[3]=$false B[4]=$true B[5]=$false B[6]=$true Y=$procmux$1879_CMP
|
||
|
|
.cname $procmux$1879_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$false B[1]=$true B[2]=$false B[3]=$false B[4]=$false B[5]=$false B[6]=$true Y=$procmux$187_CMP
|
||
|
|
.cname $procmux$187_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$true B[1]=$true B[2]=$true B[3]=$true B[4]=$false B[5]=$false B[6]=$true Y=$procmux$1880_CMP
|
||
|
|
.cname $procmux$1880_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$false B[1]=$true B[2]=$true B[3]=$true B[4]=$false B[5]=$false B[6]=$true Y=$procmux$1881_CMP
|
||
|
|
.cname $procmux$1881_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$true B[1]=$false B[2]=$true B[3]=$true B[4]=$false B[5]=$false B[6]=$true Y=$procmux$1882_CMP
|
||
|
|
.cname $procmux$1882_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$false B[1]=$false B[2]=$true B[3]=$true B[4]=$false B[5]=$false B[6]=$true Y=$procmux$1883_CMP
|
||
|
|
.cname $procmux$1883_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$true B[1]=$true B[2]=$false B[3]=$true B[4]=$false B[5]=$false B[6]=$true Y=$procmux$1884_CMP
|
||
|
|
.cname $procmux$1884_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$false B[1]=$true B[2]=$false B[3]=$true B[4]=$false B[5]=$false B[6]=$true Y=$procmux$1885_CMP
|
||
|
|
.cname $procmux$1885_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$true B[1]=$false B[2]=$false B[3]=$true B[4]=$false B[5]=$false B[6]=$true Y=$procmux$1886_CMP
|
||
|
|
.cname $procmux$1886_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$false B[1]=$false B[2]=$false B[3]=$true B[4]=$false B[5]=$false B[6]=$true Y=$procmux$1887_CMP
|
||
|
|
.cname $procmux$1887_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$true B[1]=$true B[2]=$true B[3]=$false B[4]=$false B[5]=$false B[6]=$true Y=$procmux$1888_CMP
|
||
|
|
.cname $procmux$1888_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$false B[1]=$true B[2]=$true B[3]=$false B[4]=$false B[5]=$false B[6]=$true Y=$procmux$1889_CMP
|
||
|
|
.cname $procmux$1889_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$true B[1]=$false B[2]=$false B[3]=$false B[4]=$false B[5]=$false B[6]=$true Y=$procmux$188_CMP
|
||
|
|
.cname $procmux$188_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$true B[1]=$false B[2]=$true B[3]=$false B[4]=$false B[5]=$false B[6]=$true Y=$procmux$1890_CMP
|
||
|
|
.cname $procmux$1890_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$false B[1]=$false B[2]=$true B[3]=$false B[4]=$false B[5]=$false B[6]=$true Y=$procmux$1891_CMP
|
||
|
|
.cname $procmux$1891_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$true B[1]=$true B[2]=$false B[3]=$false B[4]=$false B[5]=$false B[6]=$true Y=$procmux$1892_CMP
|
||
|
|
.cname $procmux$1892_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$false B[1]=$true B[2]=$false B[3]=$false B[4]=$false B[5]=$false B[6]=$true Y=$procmux$1893_CMP
|
||
|
|
.cname $procmux$1893_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$true B[1]=$false B[2]=$false B[3]=$false B[4]=$false B[5]=$false B[6]=$true Y=$procmux$1894_CMP
|
||
|
|
.cname $procmux$1894_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$false B[1]=$false B[2]=$false B[3]=$false B[4]=$false B[5]=$false B[6]=$true Y=$procmux$1895_CMP
|
||
|
|
.cname $procmux$1895_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$true B[1]=$true B[2]=$true B[3]=$true B[4]=$true B[5]=$true B[6]=$false Y=$procmux$1896_CMP
|
||
|
|
.cname $procmux$1896_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$false B[1]=$true B[2]=$true B[3]=$true B[4]=$true B[5]=$true B[6]=$false Y=$procmux$1897_CMP
|
||
|
|
.cname $procmux$1897_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$true B[1]=$false B[2]=$true B[3]=$true B[4]=$true B[5]=$true B[6]=$false Y=$procmux$1898_CMP
|
||
|
|
.cname $procmux$1898_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$false B[1]=$false B[2]=$true B[3]=$true B[4]=$true B[5]=$true B[6]=$false Y=$procmux$1899_CMP
|
||
|
|
.cname $procmux$1899_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$false B[1]=$false B[2]=$false B[3]=$false B[4]=$false B[5]=$false B[6]=$true Y=$procmux$189_CMP
|
||
|
|
.cname $procmux$189_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$true B[1]=$true B[2]=$false B[3]=$true B[4]=$true B[5]=$true B[6]=$false Y=$procmux$1900_CMP
|
||
|
|
.cname $procmux$1900_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$false B[1]=$true B[2]=$false B[3]=$true B[4]=$true B[5]=$true B[6]=$false Y=$procmux$1901_CMP
|
||
|
|
.cname $procmux$1901_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$true B[1]=$false B[2]=$false B[3]=$true B[4]=$true B[5]=$true B[6]=$false Y=$procmux$1902_CMP
|
||
|
|
.cname $procmux$1902_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$false B[1]=$false B[2]=$false B[3]=$true B[4]=$true B[5]=$true B[6]=$false Y=$procmux$1903_CMP
|
||
|
|
.cname $procmux$1903_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$true B[1]=$true B[2]=$true B[3]=$false B[4]=$true B[5]=$true B[6]=$false Y=$procmux$1904_CMP
|
||
|
|
.cname $procmux$1904_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$false B[1]=$true B[2]=$true B[3]=$false B[4]=$true B[5]=$true B[6]=$false Y=$procmux$1905_CMP
|
||
|
|
.cname $procmux$1905_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$true B[1]=$false B[2]=$true B[3]=$false B[4]=$true B[5]=$true B[6]=$false Y=$procmux$1906_CMP
|
||
|
|
.cname $procmux$1906_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$false B[1]=$false B[2]=$true B[3]=$false B[4]=$true B[5]=$true B[6]=$false Y=$procmux$1907_CMP
|
||
|
|
.cname $procmux$1907_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$true B[1]=$true B[2]=$false B[3]=$false B[4]=$true B[5]=$true B[6]=$false Y=$procmux$1908_CMP
|
||
|
|
.cname $procmux$1908_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$false B[1]=$true B[2]=$false B[3]=$false B[4]=$true B[5]=$true B[6]=$false Y=$procmux$1909_CMP
|
||
|
|
.cname $procmux$1909_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$true B[1]=$true B[2]=$true B[3]=$true B[4]=$true B[5]=$true B[6]=$false Y=$procmux$190_CMP
|
||
|
|
.cname $procmux$190_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$true B[1]=$false B[2]=$false B[3]=$false B[4]=$true B[5]=$true B[6]=$false Y=$procmux$1910_CMP
|
||
|
|
.cname $procmux$1910_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$false B[1]=$false B[2]=$false B[3]=$false B[4]=$true B[5]=$true B[6]=$false Y=$procmux$1911_CMP
|
||
|
|
.cname $procmux$1911_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$true B[1]=$true B[2]=$true B[3]=$true B[4]=$false B[5]=$true B[6]=$false Y=$procmux$1912_CMP
|
||
|
|
.cname $procmux$1912_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$false B[1]=$true B[2]=$true B[3]=$true B[4]=$false B[5]=$true B[6]=$false Y=$procmux$1913_CMP
|
||
|
|
.cname $procmux$1913_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$true B[1]=$false B[2]=$true B[3]=$true B[4]=$false B[5]=$true B[6]=$false Y=$procmux$1914_CMP
|
||
|
|
.cname $procmux$1914_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$false B[1]=$false B[2]=$true B[3]=$true B[4]=$false B[5]=$true B[6]=$false Y=$procmux$1915_CMP
|
||
|
|
.cname $procmux$1915_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$true B[1]=$true B[2]=$false B[3]=$true B[4]=$false B[5]=$true B[6]=$false Y=$procmux$1916_CMP
|
||
|
|
.cname $procmux$1916_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$false B[1]=$true B[2]=$false B[3]=$true B[4]=$false B[5]=$true B[6]=$false Y=$procmux$1917_CMP
|
||
|
|
.cname $procmux$1917_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$true B[1]=$false B[2]=$false B[3]=$true B[4]=$false B[5]=$true B[6]=$false Y=$procmux$1918_CMP
|
||
|
|
.cname $procmux$1918_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$false B[1]=$false B[2]=$false B[3]=$true B[4]=$false B[5]=$true B[6]=$false Y=$procmux$1919_CMP
|
||
|
|
.cname $procmux$1919_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$false B[1]=$true B[2]=$true B[3]=$true B[4]=$true B[5]=$true B[6]=$false Y=$procmux$191_CMP
|
||
|
|
.cname $procmux$191_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$true B[1]=$true B[2]=$true B[3]=$false B[4]=$false B[5]=$true B[6]=$false Y=$procmux$1920_CMP
|
||
|
|
.cname $procmux$1920_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$false B[1]=$true B[2]=$true B[3]=$false B[4]=$false B[5]=$true B[6]=$false Y=$procmux$1921_CMP
|
||
|
|
.cname $procmux$1921_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$true B[1]=$false B[2]=$true B[3]=$false B[4]=$false B[5]=$true B[6]=$false Y=$procmux$1922_CMP
|
||
|
|
.cname $procmux$1922_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$false B[1]=$false B[2]=$true B[3]=$false B[4]=$false B[5]=$true B[6]=$false Y=$procmux$1923_CMP
|
||
|
|
.cname $procmux$1923_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$true B[1]=$true B[2]=$false B[3]=$false B[4]=$false B[5]=$true B[6]=$false Y=$procmux$1924_CMP
|
||
|
|
.cname $procmux$1924_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$false B[1]=$true B[2]=$false B[3]=$false B[4]=$false B[5]=$true B[6]=$false Y=$procmux$1925_CMP
|
||
|
|
.cname $procmux$1925_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$true B[1]=$false B[2]=$false B[3]=$false B[4]=$false B[5]=$true B[6]=$false Y=$procmux$1926_CMP
|
||
|
|
.cname $procmux$1926_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$false B[1]=$false B[2]=$false B[3]=$false B[4]=$false B[5]=$true B[6]=$false Y=$procmux$1927_CMP
|
||
|
|
.cname $procmux$1927_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$true B[1]=$true B[2]=$true B[3]=$true B[4]=$true B[5]=$false B[6]=$false Y=$procmux$1928_CMP
|
||
|
|
.cname $procmux$1928_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$false B[1]=$true B[2]=$true B[3]=$true B[4]=$true B[5]=$false B[6]=$false Y=$procmux$1929_CMP
|
||
|
|
.cname $procmux$1929_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$true B[1]=$false B[2]=$true B[3]=$true B[4]=$true B[5]=$true B[6]=$false Y=$procmux$192_CMP
|
||
|
|
.cname $procmux$192_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$true B[1]=$false B[2]=$true B[3]=$true B[4]=$true B[5]=$false B[6]=$false Y=$procmux$1930_CMP
|
||
|
|
.cname $procmux$1930_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$false B[1]=$false B[2]=$true B[3]=$true B[4]=$true B[5]=$false B[6]=$false Y=$procmux$1931_CMP
|
||
|
|
.cname $procmux$1931_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$true B[1]=$true B[2]=$false B[3]=$true B[4]=$true B[5]=$false B[6]=$false Y=$procmux$1932_CMP
|
||
|
|
.cname $procmux$1932_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$false B[1]=$true B[2]=$false B[3]=$true B[4]=$true B[5]=$false B[6]=$false Y=$procmux$1933_CMP
|
||
|
|
.cname $procmux$1933_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$true B[1]=$false B[2]=$false B[3]=$true B[4]=$true B[5]=$false B[6]=$false Y=$procmux$1934_CMP
|
||
|
|
.cname $procmux$1934_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$false B[1]=$false B[2]=$false B[3]=$true B[4]=$true B[5]=$false B[6]=$false Y=$procmux$1935_CMP
|
||
|
|
.cname $procmux$1935_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$true B[1]=$true B[2]=$true B[3]=$false B[4]=$true B[5]=$false B[6]=$false Y=$procmux$1936_CMP
|
||
|
|
.cname $procmux$1936_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$false B[1]=$true B[2]=$true B[3]=$false B[4]=$true B[5]=$false B[6]=$false Y=$procmux$1937_CMP
|
||
|
|
.cname $procmux$1937_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$true B[1]=$false B[2]=$true B[3]=$false B[4]=$true B[5]=$false B[6]=$false Y=$procmux$1938_CMP
|
||
|
|
.cname $procmux$1938_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$false B[1]=$false B[2]=$true B[3]=$false B[4]=$true B[5]=$false B[6]=$false Y=$procmux$1939_CMP
|
||
|
|
.cname $procmux$1939_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$false B[1]=$false B[2]=$true B[3]=$true B[4]=$true B[5]=$true B[6]=$false Y=$procmux$193_CMP
|
||
|
|
.cname $procmux$193_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$true B[1]=$true B[2]=$false B[3]=$false B[4]=$true B[5]=$false B[6]=$false Y=$procmux$1940_CMP
|
||
|
|
.cname $procmux$1940_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$false B[1]=$true B[2]=$false B[3]=$false B[4]=$true B[5]=$false B[6]=$false Y=$procmux$1941_CMP
|
||
|
|
.cname $procmux$1941_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$true B[1]=$false B[2]=$false B[3]=$false B[4]=$true B[5]=$false B[6]=$false Y=$procmux$1942_CMP
|
||
|
|
.cname $procmux$1942_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$false B[1]=$false B[2]=$false B[3]=$false B[4]=$true B[5]=$false B[6]=$false Y=$procmux$1943_CMP
|
||
|
|
.cname $procmux$1943_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$true B[1]=$true B[2]=$true B[3]=$true B[4]=$false B[5]=$false B[6]=$false Y=$procmux$1944_CMP
|
||
|
|
.cname $procmux$1944_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$false B[1]=$true B[2]=$true B[3]=$true B[4]=$false B[5]=$false B[6]=$false Y=$procmux$1945_CMP
|
||
|
|
.cname $procmux$1945_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$true B[1]=$false B[2]=$true B[3]=$true B[4]=$false B[5]=$false B[6]=$false Y=$procmux$1946_CMP
|
||
|
|
.cname $procmux$1946_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$false B[1]=$false B[2]=$true B[3]=$true B[4]=$false B[5]=$false B[6]=$false Y=$procmux$1947_CMP
|
||
|
|
.cname $procmux$1947_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$true B[1]=$true B[2]=$false B[3]=$true B[4]=$false B[5]=$false B[6]=$false Y=$procmux$1948_CMP
|
||
|
|
.cname $procmux$1948_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$false B[1]=$true B[2]=$false B[3]=$true B[4]=$false B[5]=$false B[6]=$false Y=$procmux$1949_CMP
|
||
|
|
.cname $procmux$1949_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$true B[1]=$true B[2]=$false B[3]=$true B[4]=$true B[5]=$true B[6]=$false Y=$procmux$194_CMP
|
||
|
|
.cname $procmux$194_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$true B[1]=$false B[2]=$false B[3]=$true B[4]=$false B[5]=$false B[6]=$false Y=$procmux$1950_CMP
|
||
|
|
.cname $procmux$1950_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$false B[1]=$false B[2]=$false B[3]=$true B[4]=$false B[5]=$false B[6]=$false Y=$procmux$1951_CMP
|
||
|
|
.cname $procmux$1951_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$true B[1]=$true B[2]=$true B[3]=$false B[4]=$false B[5]=$false B[6]=$false Y=$procmux$1952_CMP
|
||
|
|
.cname $procmux$1952_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$false B[1]=$true B[2]=$true B[3]=$false B[4]=$false B[5]=$false B[6]=$false Y=$procmux$1953_CMP
|
||
|
|
.cname $procmux$1953_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$true B[1]=$false B[2]=$true B[3]=$false B[4]=$false B[5]=$false B[6]=$false Y=$procmux$1954_CMP
|
||
|
|
.cname $procmux$1954_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$false B[1]=$false B[2]=$true B[3]=$false B[4]=$false B[5]=$false B[6]=$false Y=$procmux$1955_CMP
|
||
|
|
.cname $procmux$1955_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$true B[1]=$true B[2]=$false B[3]=$false B[4]=$false B[5]=$false B[6]=$false Y=$procmux$1956_CMP
|
||
|
|
.cname $procmux$1956_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$false B[1]=$true B[2]=$false B[3]=$false B[4]=$false B[5]=$false B[6]=$false Y=$procmux$1957_CMP
|
||
|
|
.cname $procmux$1957_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$true B[1]=$false B[2]=$false B[3]=$false B[4]=$false B[5]=$false B[6]=$false Y=$procmux$1958_CMP
|
||
|
|
.cname $procmux$1958_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$false B[1]=$true B[2]=$false B[3]=$true B[4]=$true B[5]=$true B[6]=$false Y=$procmux$195_CMP
|
||
|
|
.cname $procmux$195_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $mux A[0]=E[0] A[1]=E[1] A[2]=E[2] A[3]=E[3] A[4]=E[4] A[5]=E[5] A[6]=E[6] A[7]=E[7] A[8]=E[8] A[9]=E[9] A[10]=E[10] A[11]=E[11] A[12]=E[12] A[13]=E[13] A[14]=E[14] A[15]=E[15] A[16]=E[16] A[17]=E[17] A[18]=E[18] A[19]=E[19] A[20]=E[20] A[21]=E[21] A[22]=E[22] A[23]=E[23] A[24]=E[24] A[25]=E[25] A[26]=E[26] A[27]=E[27] A[28]=E[28] A[29]=E[29] A[30]=E[30] A[31]=E[31] B[0]=$false B[1]=$false B[2]=$false B[3]=$false B[4]=$true B[5]=$true B[6]=$true B[7]=$true B[8]=$true B[9]=$false B[10]=$false B[11]=$false B[12]=$false B[13]=$true B[14]=$true B[15]=$true B[16]=$false B[17]=$true B[18]=$false B[19]=$false B[20]=$true B[21]=$false B[22]=$true B[23]=$true B[24]=$true B[25]=$true B[26]=$false B[27]=$false B[28]=$false B[29]=$false B[30]=$true B[31]=$true S=$procmux$1962_CMP Y[0]=$procmux$1961_Y[0] Y[1]=$procmux$1961_Y[1] Y[2]=$procmux$1961_Y[2] Y[3]=$procmux$1961_Y[3] Y[4]=$procmux$1961_Y[4] Y[5]=$procmux$1961_Y[5] Y[6]=$procmux$1961_Y[6] Y[7]=$procmux$1961_Y[7] Y[8]=$procmux$1961_Y[8] Y[9]=$procmux$1961_Y[9] Y[10]=$procmux$1961_Y[10] Y[11]=$procmux$1961_Y[11] Y[12]=$procmux$1961_Y[12] Y[13]=$procmux$1961_Y[13] Y[14]=$procmux$1961_Y[14] Y[15]=$procmux$1961_Y[15] Y[16]=$procmux$1961_Y[16] Y[17]=$procmux$1961_Y[17] Y[18]=$procmux$1961_Y[18] Y[19]=$procmux$1961_Y[19] Y[20]=$procmux$1961_Y[20] Y[21]=$procmux$1961_Y[21] Y[22]=$procmux$1961_Y[22] Y[23]=$procmux$1961_Y[23] Y[24]=$procmux$1961_Y[24] Y[25]=$procmux$1961_Y[25] Y[26]=$procmux$1961_Y[26] Y[27]=$procmux$1961_Y[27] Y[28]=$procmux$1961_Y[28] Y[29]=$procmux$1961_Y[29] Y[30]=$procmux$1961_Y[30] Y[31]=$procmux$1961_Y[31]
|
||
|
|
.cname $procmux$1961
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:198"
|
||
|
|
.param WIDTH 00000000000000000000000000100000
|
||
|
|
.subckt $eq A=cmd[2] B=$false Y=$procmux$1962_CMP
|
||
|
|
.cname $procmux$1962_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:198"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000001
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000001
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $mux A[0]=E[0] A[1]=E[1] A[2]=E[2] A[3]=E[3] A[4]=E[4] A[5]=E[5] A[6]=E[6] A[7]=E[7] A[8]=E[8] A[9]=E[9] A[10]=E[10] A[11]=E[11] A[12]=E[12] A[13]=E[13] A[14]=E[14] A[15]=E[15] A[16]=E[16] A[17]=E[17] A[18]=E[18] A[19]=E[19] A[20]=E[20] A[21]=E[21] A[22]=E[22] A[23]=E[23] A[24]=E[24] A[25]=E[25] A[26]=E[26] A[27]=E[27] A[28]=E[28] A[29]=E[29] A[30]=E[30] A[31]=E[31] B[0]=$procmux$1961_Y[0] B[1]=$procmux$1961_Y[1] B[2]=$procmux$1961_Y[2] B[3]=$procmux$1961_Y[3] B[4]=$procmux$1961_Y[4] B[5]=$procmux$1961_Y[5] B[6]=$procmux$1961_Y[6] B[7]=$procmux$1961_Y[7] B[8]=$procmux$1961_Y[8] B[9]=$procmux$1961_Y[9] B[10]=$procmux$1961_Y[10] B[11]=$procmux$1961_Y[11] B[12]=$procmux$1961_Y[12] B[13]=$procmux$1961_Y[13] B[14]=$procmux$1961_Y[14] B[15]=$procmux$1961_Y[15] B[16]=$procmux$1961_Y[16] B[17]=$procmux$1961_Y[17] B[18]=$procmux$1961_Y[18] B[19]=$procmux$1961_Y[19] B[20]=$procmux$1961_Y[20] B[21]=$procmux$1961_Y[21] B[22]=$procmux$1961_Y[22] B[23]=$procmux$1961_Y[23] B[24]=$procmux$1961_Y[24] B[25]=$procmux$1961_Y[25] B[26]=$procmux$1961_Y[26] B[27]=$procmux$1961_Y[27] B[28]=$procmux$1961_Y[28] B[29]=$procmux$1961_Y[29] B[30]=$procmux$1961_Y[30] B[31]=$procmux$1961_Y[31] S=$procmux$1964_CMP Y[0]=$procmux$1963_Y[0] Y[1]=$procmux$1963_Y[1] Y[2]=$procmux$1963_Y[2] Y[3]=$procmux$1963_Y[3] Y[4]=$procmux$1963_Y[4] Y[5]=$procmux$1963_Y[5] Y[6]=$procmux$1963_Y[6] Y[7]=$procmux$1963_Y[7] Y[8]=$procmux$1963_Y[8] Y[9]=$procmux$1963_Y[9] Y[10]=$procmux$1963_Y[10] Y[11]=$procmux$1963_Y[11] Y[12]=$procmux$1963_Y[12] Y[13]=$procmux$1963_Y[13] Y[14]=$procmux$1963_Y[14] Y[15]=$procmux$1963_Y[15] Y[16]=$procmux$1963_Y[16] Y[17]=$procmux$1963_Y[17] Y[18]=$procmux$1963_Y[18] Y[19]=$procmux$1963_Y[19] Y[20]=$procmux$1963_Y[20] Y[21]=$procmux$1963_Y[21] Y[22]=$procmux$1963_Y[22] Y[23]=$procmux$1963_Y[23] Y[24]=$procmux$1963_Y[24] Y[25]=$procmux$1963_Y[25] Y[26]=$procmux$1963_Y[26] Y[27]=$procmux$1963_Y[27] Y[28]=$procmux$1963_Y[28] Y[29]=$procmux$1963_Y[29] Y[30]=$procmux$1963_Y[30] Y[31]=$procmux$1963_Y[31]
|
||
|
|
.cname $procmux$1963
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:191"
|
||
|
|
.param WIDTH 00000000000000000000000000100000
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$false B[1]=$false B[2]=$false B[3]=$false B[4]=$false B[5]=$false B[6]=$false Y=$procmux$1965_CMP
|
||
|
|
.cname $procmux$1965_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $mux A[0]=$procmux$1878_Y[0] A[1]=$procmux$1878_Y[1] A[2]=$procmux$1878_Y[2] A[3]=$procmux$1878_Y[3] A[4]=$procmux$1878_Y[4] A[5]=$procmux$1878_Y[5] A[6]=$procmux$1878_Y[6] A[7]=$procmux$1878_Y[7] A[8]=$procmux$1878_Y[8] A[9]=$procmux$1878_Y[9] A[10]=$procmux$1878_Y[10] A[11]=$procmux$1878_Y[11] A[12]=$procmux$1878_Y[12] A[13]=$procmux$1878_Y[13] A[14]=$procmux$1878_Y[14] A[15]=$procmux$1878_Y[15] A[16]=$procmux$1878_Y[16] A[17]=$procmux$1878_Y[17] A[18]=$procmux$1878_Y[18] A[19]=$procmux$1878_Y[19] A[20]=$procmux$1878_Y[20] A[21]=$procmux$1878_Y[21] A[22]=$procmux$1878_Y[22] A[23]=$procmux$1878_Y[23] A[24]=$procmux$1878_Y[24] A[25]=$procmux$1878_Y[25] A[26]=$procmux$1878_Y[26] A[27]=$procmux$1878_Y[27] A[28]=$procmux$1878_Y[28] A[29]=$procmux$1878_Y[29] A[30]=$procmux$1878_Y[30] A[31]=$procmux$1878_Y[31] B[0]=$false B[1]=$false B[2]=$false B[3]=$false B[4]=$false B[5]=$false B[6]=$false B[7]=$false B[8]=$false B[9]=$false B[10]=$false B[11]=$false B[12]=$false B[13]=$false B[14]=$false B[15]=$false B[16]=$false B[17]=$false B[18]=$false B[19]=$false B[20]=$false B[21]=$false B[22]=$false B[23]=$false B[24]=$false B[25]=$false B[26]=$false B[27]=$false B[28]=$false B[29]=$false B[30]=$false B[31]=$false S=$procmux$1968_CMP Y[0]=$procmux$1967_Y[0] Y[1]=$procmux$1967_Y[1] Y[2]=$procmux$1967_Y[2] Y[3]=$procmux$1967_Y[3] Y[4]=$procmux$1967_Y[4] Y[5]=$procmux$1967_Y[5] Y[6]=$procmux$1967_Y[6] Y[7]=$procmux$1967_Y[7] Y[8]=$procmux$1967_Y[8] Y[9]=$procmux$1967_Y[9] Y[10]=$procmux$1967_Y[10] Y[11]=$procmux$1967_Y[11] Y[12]=$procmux$1967_Y[12] Y[13]=$procmux$1967_Y[13] Y[14]=$procmux$1967_Y[14] Y[15]=$procmux$1967_Y[15] Y[16]=$procmux$1967_Y[16] Y[17]=$procmux$1967_Y[17] Y[18]=$procmux$1967_Y[18] Y[19]=$procmux$1967_Y[19] Y[20]=$procmux$1967_Y[20] Y[21]=$procmux$1967_Y[21] Y[22]=$procmux$1967_Y[22] Y[23]=$procmux$1967_Y[23] Y[24]=$procmux$1967_Y[24] Y[25]=$procmux$1967_Y[25] Y[26]=$procmux$1967_Y[26] Y[27]=$procmux$1967_Y[27] Y[28]=$procmux$1967_Y[28] Y[29]=$procmux$1967_Y[29] Y[30]=$procmux$1967_Y[30] Y[31]=$procmux$1967_Y[31]
|
||
|
|
.cname $procmux$1967
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:150"
|
||
|
|
.param WIDTH 00000000000000000000000000100000
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$true B[1]=$false B[2]=$false B[3]=$true B[4]=$true B[5]=$true B[6]=$false Y=$procmux$196_CMP
|
||
|
|
.cname $procmux$196_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $pmux A[0]=D[0] A[1]=D[1] A[2]=D[2] A[3]=D[3] A[4]=D[4] A[5]=D[5] A[6]=D[6] A[7]=D[7] A[8]=D[8] A[9]=D[9] A[10]=D[10] A[11]=D[11] A[12]=D[12] A[13]=D[13] A[14]=D[14] A[15]=D[15] A[16]=D[16] A[17]=D[17] A[18]=D[18] A[19]=D[19] A[20]=D[20] A[21]=D[21] A[22]=D[22] A[23]=D[23] A[24]=D[24] A[25]=D[25] A[26]=D[26] A[27]=D[27] A[28]=D[28] A[29]=D[29] A[30]=D[30] A[31]=D[31] B[0]=$add$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:2092$32_Y[0] B[1]=$add$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:2092$32_Y[1] B[2]=$add$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:2092$32_Y[2] B[3]=$add$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:2092$32_Y[3] B[4]=$add$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:2092$32_Y[4] B[5]=$add$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:2092$32_Y[5] B[6]=$add$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:2092$32_Y[6] B[7]=$add$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:2092$32_Y[7] B[8]=$add$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:2092$32_Y[8] B[9]=$add$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:2092$32_Y[9] B[10]=$add$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:2092$32_Y[10] B[11]=$add$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:2092$32_Y[11] B[12]=$add$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:2092$32_Y[12] B[13]=$add$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:2092$32_Y[13] B[14]=$add$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:2092$32_Y[14] B[15]=$add$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:2092$32_Y[15] B[16]=$add$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:2092$32_Y[16] B[17]=$add$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:2092$32_Y[17] B[18]=$add$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:2092$32_Y[18] B[19]=$add$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:2092$32_Y[19] B[20]=$add$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:2092$32_Y[20] B[21]=$add$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:2092$32_Y[21] B[22]=$add$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:2092$32_Y[22] B[23]=$add$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:2092$32_Y[23] B[24]=$add$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:2092$32_Y[24] B[25]=$add$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:2092$32_Y[25] B[26]=$add$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:2092$32_Y[26] B[27]=$add$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:2092$32_Y[27] B[28]=$add$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:2092$32_Y[28] B[29]=$add$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:2092$32_Y[29] B[30]=$add$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:2092$32_Y[30] B[31]=$add$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:2092$32_Y[31] B[32]=C[0] B[33]=C[1] B[34]=C[2] B[35]=C[3] B[36]=C[4] B[37]=C[5] B[38]=C[6] B[39]=C[7] B[40]=C[8] B[41]=C[9] B[42]=C[10] B[43]=C[11] B[44]=C[12] B[45]=C[13] B[46]=C[14] B[47]=C[15] B[48]=C[16] B[49]=C[17] B[50]=C[18] B[51]=C[19] B[52]=C[20] B[53]=C[21] B[54]=C[22] B[55]=C[23] B[56]=C[24] B[57]=C[25] B[58]=C[26] B[59]=C[27] B[60]=C[28] B[61]=C[29] B[62]=C[30] B[63]=C[31] B[64]=C[0] B[65]=C[1] B[66]=C[2] B[67]=C[3] B[68]=C[4] B[69]=C[5] B[70]=C[6] B[71]=C[7] B[72]=C[8] B[73]=C[9] B[74]=C[10] B[75]=C[11] B[76]=C[12] B[77]=C[13] B[78]=C[14] B[79]=C[15] B[80]=C[16] B[81]=C[17] B[82]=C[18] B[83]=C[19] B[84]=C[20] B[85]=C[21] B[86]=C[22] B[87]=C[23] B[88]=C[24] B[89]=C[25] B[90]=C[26] B[91]=C[27] B[92]=C[28] B[93]=C[29] B[94]=C[30] B[95]=C[31] B[96]=C[0] B[97]=C[1] B[98]=C[2] B[99]=C[3] B[100]=C[4] B[101]=C[5] B[102]=C[6] B[103]=C[7] B[104]=C[8] B[105]=C[9] B[106]=C[10] B[107]=C[11] B[108]=C[12] B[109]=C[13] B[110]=C[14] B[111]=C[15] B[112]=C[16] B[113]=C[17] B[114]=C[18] B[115]=C[19] B[116]=C[20] B[117]=C[21] B[118]=C[22] B[119]=C[23] B[120]=C[24] B[121]=C[25] B[122]=C[26] B[123]=C[27] B[124]=C[28] B[125]=C[29] B[126]=C[30] B[127]=C[31] B[128]=C[0] B[129]=C[1] B[130]=C[2] B[131]=C[3] B[132]=C[4] B[133]=C[5] B[134]=C[6] B[135]=
|
||
|
|
.cname $procmux$1970
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param S_WIDTH 00000000000000000000000001010001
|
||
|
|
.param WIDTH 00000000000000000000000000100000
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$false B[1]=$false B[2]=$false B[3]=$false B[4]=$true B[5]=$false B[6]=$true Y=$procmux$1971_CMP
|
||
|
|
.cname $procmux$1971_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$true B[1]=$true B[2]=$true B[3]=$true B[4]=$false B[5]=$false B[6]=$true Y=$procmux$1972_CMP
|
||
|
|
.cname $procmux$1972_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$false B[1]=$true B[2]=$true B[3]=$true B[4]=$false B[5]=$false B[6]=$true Y=$procmux$1973_CMP
|
||
|
|
.cname $procmux$1973_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$true B[1]=$false B[2]=$true B[3]=$true B[4]=$false B[5]=$false B[6]=$true Y=$procmux$1974_CMP
|
||
|
|
.cname $procmux$1974_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$false B[1]=$false B[2]=$true B[3]=$true B[4]=$false B[5]=$false B[6]=$true Y=$procmux$1975_CMP
|
||
|
|
.cname $procmux$1975_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$true B[1]=$true B[2]=$false B[3]=$true B[4]=$false B[5]=$false B[6]=$true Y=$procmux$1976_CMP
|
||
|
|
.cname $procmux$1976_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$false B[1]=$true B[2]=$false B[3]=$true B[4]=$false B[5]=$false B[6]=$true Y=$procmux$1977_CMP
|
||
|
|
.cname $procmux$1977_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$true B[1]=$false B[2]=$false B[3]=$true B[4]=$false B[5]=$false B[6]=$true Y=$procmux$1978_CMP
|
||
|
|
.cname $procmux$1978_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$false B[1]=$false B[2]=$false B[3]=$true B[4]=$false B[5]=$false B[6]=$true Y=$procmux$1979_CMP
|
||
|
|
.cname $procmux$1979_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$false B[1]=$false B[2]=$false B[3]=$true B[4]=$true B[5]=$true B[6]=$false Y=$procmux$197_CMP
|
||
|
|
.cname $procmux$197_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$true B[1]=$true B[2]=$true B[3]=$false B[4]=$false B[5]=$false B[6]=$true Y=$procmux$1980_CMP
|
||
|
|
.cname $procmux$1980_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$false B[1]=$true B[2]=$true B[3]=$false B[4]=$false B[5]=$false B[6]=$true Y=$procmux$1981_CMP
|
||
|
|
.cname $procmux$1981_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$true B[1]=$false B[2]=$true B[3]=$false B[4]=$false B[5]=$false B[6]=$true Y=$procmux$1982_CMP
|
||
|
|
.cname $procmux$1982_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$false B[1]=$false B[2]=$true B[3]=$false B[4]=$false B[5]=$false B[6]=$true Y=$procmux$1983_CMP
|
||
|
|
.cname $procmux$1983_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$true B[1]=$true B[2]=$false B[3]=$false B[4]=$false B[5]=$false B[6]=$true Y=$procmux$1984_CMP
|
||
|
|
.cname $procmux$1984_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$false B[1]=$true B[2]=$false B[3]=$false B[4]=$false B[5]=$false B[6]=$true Y=$procmux$1985_CMP
|
||
|
|
.cname $procmux$1985_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$true B[1]=$false B[2]=$false B[3]=$false B[4]=$false B[5]=$false B[6]=$true Y=$procmux$1986_CMP
|
||
|
|
.cname $procmux$1986_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$false B[1]=$false B[2]=$false B[3]=$false B[4]=$false B[5]=$false B[6]=$true Y=$procmux$1987_CMP
|
||
|
|
.cname $procmux$1987_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$true B[1]=$true B[2]=$true B[3]=$true B[4]=$true B[5]=$true B[6]=$false Y=$procmux$1988_CMP
|
||
|
|
.cname $procmux$1988_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$false B[1]=$true B[2]=$true B[3]=$true B[4]=$true B[5]=$true B[6]=$false Y=$procmux$1989_CMP
|
||
|
|
.cname $procmux$1989_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$true B[1]=$true B[2]=$true B[3]=$false B[4]=$true B[5]=$true B[6]=$false Y=$procmux$198_CMP
|
||
|
|
.cname $procmux$198_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$true B[1]=$false B[2]=$true B[3]=$true B[4]=$true B[5]=$true B[6]=$false Y=$procmux$1990_CMP
|
||
|
|
.cname $procmux$1990_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$false B[1]=$false B[2]=$true B[3]=$true B[4]=$true B[5]=$true B[6]=$false Y=$procmux$1991_CMP
|
||
|
|
.cname $procmux$1991_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$true B[1]=$true B[2]=$false B[3]=$true B[4]=$true B[5]=$true B[6]=$false Y=$procmux$1992_CMP
|
||
|
|
.cname $procmux$1992_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$false B[1]=$true B[2]=$false B[3]=$true B[4]=$true B[5]=$true B[6]=$false Y=$procmux$1993_CMP
|
||
|
|
.cname $procmux$1993_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$true B[1]=$false B[2]=$false B[3]=$true B[4]=$true B[5]=$true B[6]=$false Y=$procmux$1994_CMP
|
||
|
|
.cname $procmux$1994_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$false B[1]=$false B[2]=$false B[3]=$true B[4]=$true B[5]=$true B[6]=$false Y=$procmux$1995_CMP
|
||
|
|
.cname $procmux$1995_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$true B[1]=$true B[2]=$true B[3]=$false B[4]=$true B[5]=$true B[6]=$false Y=$procmux$1996_CMP
|
||
|
|
.cname $procmux$1996_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$false B[1]=$true B[2]=$true B[3]=$false B[4]=$true B[5]=$true B[6]=$false Y=$procmux$1997_CMP
|
||
|
|
.cname $procmux$1997_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$true B[1]=$false B[2]=$true B[3]=$false B[4]=$true B[5]=$true B[6]=$false Y=$procmux$1998_CMP
|
||
|
|
.cname $procmux$1998_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$false B[1]=$false B[2]=$true B[3]=$false B[4]=$true B[5]=$true B[6]=$false Y=$procmux$1999_CMP
|
||
|
|
.cname $procmux$1999_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$false B[1]=$true B[2]=$true B[3]=$false B[4]=$true B[5]=$true B[6]=$false Y=$procmux$199_CMP
|
||
|
|
.cname $procmux$199_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$true B[1]=$true B[2]=$false B[3]=$false B[4]=$true B[5]=$true B[6]=$false Y=$procmux$2000_CMP
|
||
|
|
.cname $procmux$2000_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$false B[1]=$true B[2]=$false B[3]=$false B[4]=$true B[5]=$true B[6]=$false Y=$procmux$2001_CMP
|
||
|
|
.cname $procmux$2001_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$true B[1]=$false B[2]=$false B[3]=$false B[4]=$true B[5]=$true B[6]=$false Y=$procmux$2002_CMP
|
||
|
|
.cname $procmux$2002_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$false B[1]=$false B[2]=$false B[3]=$false B[4]=$true B[5]=$true B[6]=$false Y=$procmux$2003_CMP
|
||
|
|
.cname $procmux$2003_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$true B[1]=$true B[2]=$true B[3]=$true B[4]=$false B[5]=$true B[6]=$false Y=$procmux$2004_CMP
|
||
|
|
.cname $procmux$2004_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$false B[1]=$true B[2]=$true B[3]=$true B[4]=$false B[5]=$true B[6]=$false Y=$procmux$2005_CMP
|
||
|
|
.cname $procmux$2005_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$true B[1]=$false B[2]=$true B[3]=$true B[4]=$false B[5]=$true B[6]=$false Y=$procmux$2006_CMP
|
||
|
|
.cname $procmux$2006_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$false B[1]=$false B[2]=$true B[3]=$true B[4]=$false B[5]=$true B[6]=$false Y=$procmux$2007_CMP
|
||
|
|
.cname $procmux$2007_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$true B[1]=$true B[2]=$false B[3]=$true B[4]=$false B[5]=$true B[6]=$false Y=$procmux$2008_CMP
|
||
|
|
.cname $procmux$2008_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$false B[1]=$true B[2]=$false B[3]=$true B[4]=$false B[5]=$true B[6]=$false Y=$procmux$2009_CMP
|
||
|
|
.cname $procmux$2009_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$true B[1]=$false B[2]=$true B[3]=$false B[4]=$true B[5]=$true B[6]=$false Y=$procmux$200_CMP
|
||
|
|
.cname $procmux$200_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$true B[1]=$false B[2]=$false B[3]=$true B[4]=$false B[5]=$true B[6]=$false Y=$procmux$2010_CMP
|
||
|
|
.cname $procmux$2010_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$false B[1]=$false B[2]=$false B[3]=$true B[4]=$false B[5]=$true B[6]=$false Y=$procmux$2011_CMP
|
||
|
|
.cname $procmux$2011_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$true B[1]=$true B[2]=$true B[3]=$false B[4]=$false B[5]=$true B[6]=$false Y=$procmux$2012_CMP
|
||
|
|
.cname $procmux$2012_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$false B[1]=$true B[2]=$true B[3]=$false B[4]=$false B[5]=$true B[6]=$false Y=$procmux$2013_CMP
|
||
|
|
.cname $procmux$2013_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$true B[1]=$false B[2]=$true B[3]=$false B[4]=$false B[5]=$true B[6]=$false Y=$procmux$2014_CMP
|
||
|
|
.cname $procmux$2014_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$false B[1]=$false B[2]=$true B[3]=$false B[4]=$false B[5]=$true B[6]=$false Y=$procmux$2015_CMP
|
||
|
|
.cname $procmux$2015_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$true B[1]=$true B[2]=$false B[3]=$false B[4]=$false B[5]=$true B[6]=$false Y=$procmux$2016_CMP
|
||
|
|
.cname $procmux$2016_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$false B[1]=$true B[2]=$false B[3]=$false B[4]=$false B[5]=$true B[6]=$false Y=$procmux$2017_CMP
|
||
|
|
.cname $procmux$2017_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$true B[1]=$false B[2]=$false B[3]=$false B[4]=$false B[5]=$true B[6]=$false Y=$procmux$2018_CMP
|
||
|
|
.cname $procmux$2018_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$false B[1]=$false B[2]=$false B[3]=$false B[4]=$false B[5]=$true B[6]=$false Y=$procmux$2019_CMP
|
||
|
|
.cname $procmux$2019_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$false B[1]=$false B[2]=$true B[3]=$false B[4]=$true B[5]=$true B[6]=$false Y=$procmux$201_CMP
|
||
|
|
.cname $procmux$201_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$true B[1]=$true B[2]=$true B[3]=$true B[4]=$true B[5]=$false B[6]=$false Y=$procmux$2020_CMP
|
||
|
|
.cname $procmux$2020_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$false B[1]=$true B[2]=$true B[3]=$true B[4]=$true B[5]=$false B[6]=$false Y=$procmux$2021_CMP
|
||
|
|
.cname $procmux$2021_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$true B[1]=$false B[2]=$true B[3]=$true B[4]=$true B[5]=$false B[6]=$false Y=$procmux$2022_CMP
|
||
|
|
.cname $procmux$2022_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$false B[1]=$false B[2]=$true B[3]=$true B[4]=$true B[5]=$false B[6]=$false Y=$procmux$2023_CMP
|
||
|
|
.cname $procmux$2023_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$true B[1]=$true B[2]=$false B[3]=$true B[4]=$true B[5]=$false B[6]=$false Y=$procmux$2024_CMP
|
||
|
|
.cname $procmux$2024_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$false B[1]=$true B[2]=$false B[3]=$true B[4]=$true B[5]=$false B[6]=$false Y=$procmux$2025_CMP
|
||
|
|
.cname $procmux$2025_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$true B[1]=$false B[2]=$false B[3]=$true B[4]=$true B[5]=$false B[6]=$false Y=$procmux$2026_CMP
|
||
|
|
.cname $procmux$2026_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$false B[1]=$false B[2]=$false B[3]=$true B[4]=$true B[5]=$false B[6]=$false Y=$procmux$2027_CMP
|
||
|
|
.cname $procmux$2027_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$true B[1]=$true B[2]=$true B[3]=$false B[4]=$true B[5]=$false B[6]=$false Y=$procmux$2028_CMP
|
||
|
|
.cname $procmux$2028_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$false B[1]=$true B[2]=$true B[3]=$false B[4]=$true B[5]=$false B[6]=$false Y=$procmux$2029_CMP
|
||
|
|
.cname $procmux$2029_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$true B[1]=$true B[2]=$false B[3]=$false B[4]=$true B[5]=$true B[6]=$false Y=$procmux$202_CMP
|
||
|
|
.cname $procmux$202_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$true B[1]=$false B[2]=$true B[3]=$false B[4]=$true B[5]=$false B[6]=$false Y=$procmux$2030_CMP
|
||
|
|
.cname $procmux$2030_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$false B[1]=$false B[2]=$true B[3]=$false B[4]=$true B[5]=$false B[6]=$false Y=$procmux$2031_CMP
|
||
|
|
.cname $procmux$2031_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$true B[1]=$true B[2]=$false B[3]=$false B[4]=$true B[5]=$false B[6]=$false Y=$procmux$2032_CMP
|
||
|
|
.cname $procmux$2032_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$false B[1]=$true B[2]=$false B[3]=$false B[4]=$true B[5]=$false B[6]=$false Y=$procmux$2033_CMP
|
||
|
|
.cname $procmux$2033_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$true B[1]=$false B[2]=$false B[3]=$false B[4]=$true B[5]=$false B[6]=$false Y=$procmux$2034_CMP
|
||
|
|
.cname $procmux$2034_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$false B[1]=$false B[2]=$false B[3]=$false B[4]=$true B[5]=$false B[6]=$false Y=$procmux$2035_CMP
|
||
|
|
.cname $procmux$2035_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$true B[1]=$true B[2]=$true B[3]=$true B[4]=$false B[5]=$false B[6]=$false Y=$procmux$2036_CMP
|
||
|
|
.cname $procmux$2036_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$false B[1]=$true B[2]=$true B[3]=$true B[4]=$false B[5]=$false B[6]=$false Y=$procmux$2037_CMP
|
||
|
|
.cname $procmux$2037_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$true B[1]=$false B[2]=$true B[3]=$true B[4]=$false B[5]=$false B[6]=$false Y=$procmux$2038_CMP
|
||
|
|
.cname $procmux$2038_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$false B[1]=$false B[2]=$true B[3]=$true B[4]=$false B[5]=$false B[6]=$false Y=$procmux$2039_CMP
|
||
|
|
.cname $procmux$2039_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$false B[1]=$true B[2]=$false B[3]=$false B[4]=$true B[5]=$true B[6]=$false Y=$procmux$203_CMP
|
||
|
|
.cname $procmux$203_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$true B[1]=$true B[2]=$false B[3]=$true B[4]=$false B[5]=$false B[6]=$false Y=$procmux$2040_CMP
|
||
|
|
.cname $procmux$2040_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$false B[1]=$true B[2]=$false B[3]=$true B[4]=$false B[5]=$false B[6]=$false Y=$procmux$2041_CMP
|
||
|
|
.cname $procmux$2041_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$true B[1]=$false B[2]=$false B[3]=$true B[4]=$false B[5]=$false B[6]=$false Y=$procmux$2042_CMP
|
||
|
|
.cname $procmux$2042_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$false B[1]=$false B[2]=$false B[3]=$true B[4]=$false B[5]=$false B[6]=$false Y=$procmux$2043_CMP
|
||
|
|
.cname $procmux$2043_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$true B[1]=$true B[2]=$true B[3]=$false B[4]=$false B[5]=$false B[6]=$false Y=$procmux$2044_CMP
|
||
|
|
.cname $procmux$2044_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$false B[1]=$true B[2]=$true B[3]=$false B[4]=$false B[5]=$false B[6]=$false Y=$procmux$2045_CMP
|
||
|
|
.cname $procmux$2045_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$true B[1]=$false B[2]=$true B[3]=$false B[4]=$false B[5]=$false B[6]=$false Y=$procmux$2046_CMP
|
||
|
|
.cname $procmux$2046_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$false B[1]=$false B[2]=$true B[3]=$false B[4]=$false B[5]=$false B[6]=$false Y=$procmux$2047_CMP
|
||
|
|
.cname $procmux$2047_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$true B[1]=$true B[2]=$false B[3]=$false B[4]=$false B[5]=$false B[6]=$false Y=$procmux$2048_CMP
|
||
|
|
.cname $procmux$2048_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$false B[1]=$true B[2]=$false B[3]=$false B[4]=$false B[5]=$false B[6]=$false Y=$procmux$2049_CMP
|
||
|
|
.cname $procmux$2049_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$true B[1]=$false B[2]=$false B[3]=$false B[4]=$true B[5]=$true B[6]=$false Y=$procmux$204_CMP
|
||
|
|
.cname $procmux$204_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$true B[1]=$false B[2]=$false B[3]=$false B[4]=$false B[5]=$false B[6]=$false Y=$procmux$2050_CMP
|
||
|
|
.cname $procmux$2050_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $mux A[0]=D[0] A[1]=D[1] A[2]=D[2] A[3]=D[3] A[4]=D[4] A[5]=D[5] A[6]=D[6] A[7]=D[7] A[8]=D[8] A[9]=D[9] A[10]=D[10] A[11]=D[11] A[12]=D[12] A[13]=D[13] A[14]=D[14] A[15]=D[15] A[16]=D[16] A[17]=D[17] A[18]=D[18] A[19]=D[19] A[20]=D[20] A[21]=D[21] A[22]=D[22] A[23]=D[23] A[24]=D[24] A[25]=D[25] A[26]=D[26] A[27]=D[27] A[28]=D[28] A[29]=D[29] A[30]=D[30] A[31]=D[31] B[0]=$false B[1]=$true B[2]=$true B[3]=$false B[4]=$true B[5]=$true B[6]=$true B[7]=$false B[8]=$false B[9]=$false B[10]=$true B[11]=$false B[12]=$true B[13]=$false B[14]=$true B[15]=$false B[16]=$false B[17]=$true B[18]=$false B[19]=$false B[20]=$true B[21]=$true B[22]=$false B[23]=$false B[24]=$false B[25]=$false B[26]=$false B[27]=$false B[28]=$true B[29]=$false B[30]=$false B[31]=$false S=$procmux$2054_CMP Y[0]=$procmux$2053_Y[0] Y[1]=$procmux$2053_Y[1] Y[2]=$procmux$2053_Y[2] Y[3]=$procmux$2053_Y[3] Y[4]=$procmux$2053_Y[4] Y[5]=$procmux$2053_Y[5] Y[6]=$procmux$2053_Y[6] Y[7]=$procmux$2053_Y[7] Y[8]=$procmux$2053_Y[8] Y[9]=$procmux$2053_Y[9] Y[10]=$procmux$2053_Y[10] Y[11]=$procmux$2053_Y[11] Y[12]=$procmux$2053_Y[12] Y[13]=$procmux$2053_Y[13] Y[14]=$procmux$2053_Y[14] Y[15]=$procmux$2053_Y[15] Y[16]=$procmux$2053_Y[16] Y[17]=$procmux$2053_Y[17] Y[18]=$procmux$2053_Y[18] Y[19]=$procmux$2053_Y[19] Y[20]=$procmux$2053_Y[20] Y[21]=$procmux$2053_Y[21] Y[22]=$procmux$2053_Y[22] Y[23]=$procmux$2053_Y[23] Y[24]=$procmux$2053_Y[24] Y[25]=$procmux$2053_Y[25] Y[26]=$procmux$2053_Y[26] Y[27]=$procmux$2053_Y[27] Y[28]=$procmux$2053_Y[28] Y[29]=$procmux$2053_Y[29] Y[30]=$procmux$2053_Y[30] Y[31]=$procmux$2053_Y[31]
|
||
|
|
.cname $procmux$2053
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:198"
|
||
|
|
.param WIDTH 00000000000000000000000000100000
|
||
|
|
.subckt $eq A=cmd[2] B=$false Y=$procmux$2054_CMP
|
||
|
|
.cname $procmux$2054_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:198"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000001
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000001
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $mux A[0]=D[0] A[1]=D[1] A[2]=D[2] A[3]=D[3] A[4]=D[4] A[5]=D[5] A[6]=D[6] A[7]=D[7] A[8]=D[8] A[9]=D[9] A[10]=D[10] A[11]=D[11] A[12]=D[12] A[13]=D[13] A[14]=D[14] A[15]=D[15] A[16]=D[16] A[17]=D[17] A[18]=D[18] A[19]=D[19] A[20]=D[20] A[21]=D[21] A[22]=D[22] A[23]=D[23] A[24]=D[24] A[25]=D[25] A[26]=D[26] A[27]=D[27] A[28]=D[28] A[29]=D[29] A[30]=D[30] A[31]=D[31] B[0]=$procmux$2053_Y[0] B[1]=$procmux$2053_Y[1] B[2]=$procmux$2053_Y[2] B[3]=$procmux$2053_Y[3] B[4]=$procmux$2053_Y[4] B[5]=$procmux$2053_Y[5] B[6]=$procmux$2053_Y[6] B[7]=$procmux$2053_Y[7] B[8]=$procmux$2053_Y[8] B[9]=$procmux$2053_Y[9] B[10]=$procmux$2053_Y[10] B[11]=$procmux$2053_Y[11] B[12]=$procmux$2053_Y[12] B[13]=$procmux$2053_Y[13] B[14]=$procmux$2053_Y[14] B[15]=$procmux$2053_Y[15] B[16]=$procmux$2053_Y[16] B[17]=$procmux$2053_Y[17] B[18]=$procmux$2053_Y[18] B[19]=$procmux$2053_Y[19] B[20]=$procmux$2053_Y[20] B[21]=$procmux$2053_Y[21] B[22]=$procmux$2053_Y[22] B[23]=$procmux$2053_Y[23] B[24]=$procmux$2053_Y[24] B[25]=$procmux$2053_Y[25] B[26]=$procmux$2053_Y[26] B[27]=$procmux$2053_Y[27] B[28]=$procmux$2053_Y[28] B[29]=$procmux$2053_Y[29] B[30]=$procmux$2053_Y[30] B[31]=$procmux$2053_Y[31] S=$procmux$2056_CMP Y[0]=$procmux$2055_Y[0] Y[1]=$procmux$2055_Y[1] Y[2]=$procmux$2055_Y[2] Y[3]=$procmux$2055_Y[3] Y[4]=$procmux$2055_Y[4] Y[5]=$procmux$2055_Y[5] Y[6]=$procmux$2055_Y[6] Y[7]=$procmux$2055_Y[7] Y[8]=$procmux$2055_Y[8] Y[9]=$procmux$2055_Y[9] Y[10]=$procmux$2055_Y[10] Y[11]=$procmux$2055_Y[11] Y[12]=$procmux$2055_Y[12] Y[13]=$procmux$2055_Y[13] Y[14]=$procmux$2055_Y[14] Y[15]=$procmux$2055_Y[15] Y[16]=$procmux$2055_Y[16] Y[17]=$procmux$2055_Y[17] Y[18]=$procmux$2055_Y[18] Y[19]=$procmux$2055_Y[19] Y[20]=$procmux$2055_Y[20] Y[21]=$procmux$2055_Y[21] Y[22]=$procmux$2055_Y[22] Y[23]=$procmux$2055_Y[23] Y[24]=$procmux$2055_Y[24] Y[25]=$procmux$2055_Y[25] Y[26]=$procmux$2055_Y[26] Y[27]=$procmux$2055_Y[27] Y[28]=$procmux$2055_Y[28] Y[29]=$procmux$2055_Y[29] Y[30]=$procmux$2055_Y[30] Y[31]=$procmux$2055_Y[31]
|
||
|
|
.cname $procmux$2055
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:191"
|
||
|
|
.param WIDTH 00000000000000000000000000100000
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$false B[1]=$false B[2]=$false B[3]=$false B[4]=$false B[5]=$false B[6]=$false Y=$procmux$2057_CMP
|
||
|
|
.cname $procmux$2057_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $mux A[0]=$procmux$1970_Y[0] A[1]=$procmux$1970_Y[1] A[2]=$procmux$1970_Y[2] A[3]=$procmux$1970_Y[3] A[4]=$procmux$1970_Y[4] A[5]=$procmux$1970_Y[5] A[6]=$procmux$1970_Y[6] A[7]=$procmux$1970_Y[7] A[8]=$procmux$1970_Y[8] A[9]=$procmux$1970_Y[9] A[10]=$procmux$1970_Y[10] A[11]=$procmux$1970_Y[11] A[12]=$procmux$1970_Y[12] A[13]=$procmux$1970_Y[13] A[14]=$procmux$1970_Y[14] A[15]=$procmux$1970_Y[15] A[16]=$procmux$1970_Y[16] A[17]=$procmux$1970_Y[17] A[18]=$procmux$1970_Y[18] A[19]=$procmux$1970_Y[19] A[20]=$procmux$1970_Y[20] A[21]=$procmux$1970_Y[21] A[22]=$procmux$1970_Y[22] A[23]=$procmux$1970_Y[23] A[24]=$procmux$1970_Y[24] A[25]=$procmux$1970_Y[25] A[26]=$procmux$1970_Y[26] A[27]=$procmux$1970_Y[27] A[28]=$procmux$1970_Y[28] A[29]=$procmux$1970_Y[29] A[30]=$procmux$1970_Y[30] A[31]=$procmux$1970_Y[31] B[0]=$false B[1]=$false B[2]=$false B[3]=$false B[4]=$false B[5]=$false B[6]=$false B[7]=$false B[8]=$false B[9]=$false B[10]=$false B[11]=$false B[12]=$false B[13]=$false B[14]=$false B[15]=$false B[16]=$false B[17]=$false B[18]=$false B[19]=$false B[20]=$false B[21]=$false B[22]=$false B[23]=$false B[24]=$false B[25]=$false B[26]=$false B[27]=$false B[28]=$false B[29]=$false B[30]=$false B[31]=$false S=$procmux$2060_CMP Y[0]=$procmux$2059_Y[0] Y[1]=$procmux$2059_Y[1] Y[2]=$procmux$2059_Y[2] Y[3]=$procmux$2059_Y[3] Y[4]=$procmux$2059_Y[4] Y[5]=$procmux$2059_Y[5] Y[6]=$procmux$2059_Y[6] Y[7]=$procmux$2059_Y[7] Y[8]=$procmux$2059_Y[8] Y[9]=$procmux$2059_Y[9] Y[10]=$procmux$2059_Y[10] Y[11]=$procmux$2059_Y[11] Y[12]=$procmux$2059_Y[12] Y[13]=$procmux$2059_Y[13] Y[14]=$procmux$2059_Y[14] Y[15]=$procmux$2059_Y[15] Y[16]=$procmux$2059_Y[16] Y[17]=$procmux$2059_Y[17] Y[18]=$procmux$2059_Y[18] Y[19]=$procmux$2059_Y[19] Y[20]=$procmux$2059_Y[20] Y[21]=$procmux$2059_Y[21] Y[22]=$procmux$2059_Y[22] Y[23]=$procmux$2059_Y[23] Y[24]=$procmux$2059_Y[24] Y[25]=$procmux$2059_Y[25] Y[26]=$procmux$2059_Y[26] Y[27]=$procmux$2059_Y[27] Y[28]=$procmux$2059_Y[28] Y[29]=$procmux$2059_Y[29] Y[30]=$procmux$2059_Y[30] Y[31]=$procmux$2059_Y[31]
|
||
|
|
.cname $procmux$2059
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:150"
|
||
|
|
.param WIDTH 00000000000000000000000000100000
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$false B[1]=$false B[2]=$false B[3]=$false B[4]=$true B[5]=$true B[6]=$false Y=$procmux$205_CMP
|
||
|
|
.cname $procmux$205_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $pmux A[0]=C[0] A[1]=C[1] A[2]=C[2] A[3]=C[3] A[4]=C[4] A[5]=C[5] A[6]=C[6] A[7]=C[7] A[8]=C[8] A[9]=C[9] A[10]=C[10] A[11]=C[11] A[12]=C[12] A[13]=C[13] A[14]=C[14] A[15]=C[15] A[16]=C[16] A[17]=C[17] A[18]=C[18] A[19]=C[19] A[20]=C[20] A[21]=C[21] A[22]=C[22] A[23]=C[23] A[24]=C[24] A[25]=C[25] A[26]=C[26] A[27]=C[27] A[28]=C[28] A[29]=C[29] A[30]=C[30] A[31]=C[31] B[0]=$add$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:2091$31_Y[0] B[1]=$add$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:2091$31_Y[1] B[2]=$add$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:2091$31_Y[2] B[3]=$add$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:2091$31_Y[3] B[4]=$add$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:2091$31_Y[4] B[5]=$add$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:2091$31_Y[5] B[6]=$add$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:2091$31_Y[6] B[7]=$add$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:2091$31_Y[7] B[8]=$add$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:2091$31_Y[8] B[9]=$add$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:2091$31_Y[9] B[10]=$add$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:2091$31_Y[10] B[11]=$add$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:2091$31_Y[11] B[12]=$add$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:2091$31_Y[12] B[13]=$add$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:2091$31_Y[13] B[14]=$add$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:2091$31_Y[14] B[15]=$add$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:2091$31_Y[15] B[16]=$add$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:2091$31_Y[16] B[17]=$add$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:2091$31_Y[17] B[18]=$add$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:2091$31_Y[18] B[19]=$add$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:2091$31_Y[19] B[20]=$add$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:2091$31_Y[20] B[21]=$add$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:2091$31_Y[21] B[22]=$add$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:2091$31_Y[22] B[23]=$add$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:2091$31_Y[23] B[24]=$add$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:2091$31_Y[24] B[25]=$add$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:2091$31_Y[25] B[26]=$add$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:2091$31_Y[26] B[27]=$add$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:2091$31_Y[27] B[28]=$add$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:2091$31_Y[28] B[29]=$add$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:2091$31_Y[29] B[30]=$add$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:2091$31_Y[30] B[31]=$add$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:2091$31_Y[31] B[32]=next_C[0] B[33]=next_C[1] B[34]=next_C[2] B[35]=next_C[3] B[36]=next_C[4] B[37]=next_C[5] B[38]=next_C[6] B[39]=next_C[7] B[40]=next_C[8] B[41]=next_C[9] B[42]=next_C[10] B[43]=next_C[11] B[44]=next_C[12] B[45]=next_C[13] B[46]=next_C[14] B[47]=next_C[15] B[48]=next_C[16] B[49]=next_C[17] B[50]=next_C[18] B[51]=next_C[19] B[52]=next_C[20] B[53]=next_C[21] B[54]=next_C[22] B[55]=next_C[23] B[56]=next_C[24] B[57]=next_C[25] B[58]=next_C[26] B[59]=next_C[27] B[60]=next_C[28] B[61]=next_C[29] B[62]=next_C[30] B[63]=next_C[31] B[64]=next_C[0] B[65]=next_C[1] B[66]=next_C[2] B[67]=next_C[3] B[68]=next_C[4] B[69]=next_C[5] B[70]=next_C[6] B[71]=next_C[7] B[72]=next_C[8] B[73]=next_C[9] B[74]=next_C[10] B[75]=next_C[11] B[76]=next_C[12] B[77]=next_C[13] B[78]=next_C[14] B[79]=next_C[15] B[80]=next_C[16] B[81]=next_C[17] B[82]=next_C[18] B[83]=next_C[19] B[84]=next_C[20] B[85]=next_C[21] B[86]=next_C[22] B[87]=next_C[23] B[88]=next_C[24] B[89]=next_C[25] B[90]=next_C[26] B[91]=next_C[27] B[92]=next_C[28] B[93]=next_C[29] B[94]=next_C[30] B[95]=next_C[31] B[96]=next_C[0] B[97]=next_C[1] B[98]=next_C[2] B[99]=next_C[3] B[100]=next_C[4] B[101]=next_C[5] B[102]=next_C[6] B[103]=next_C[7] B[104]=next_C[8] B[105]=next_C[9] B[106]=
|
||
|
|
.cname $procmux$2062
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param S_WIDTH 00000000000000000000000001010001
|
||
|
|
.param WIDTH 00000000000000000000000000100000
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$false B[1]=$false B[2]=$false B[3]=$false B[4]=$true B[5]=$false B[6]=$true Y=$procmux$2063_CMP
|
||
|
|
.cname $procmux$2063_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$true B[1]=$true B[2]=$true B[3]=$true B[4]=$false B[5]=$false B[6]=$true Y=$procmux$2064_CMP
|
||
|
|
.cname $procmux$2064_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$false B[1]=$true B[2]=$true B[3]=$true B[4]=$false B[5]=$false B[6]=$true Y=$procmux$2065_CMP
|
||
|
|
.cname $procmux$2065_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$true B[1]=$false B[2]=$true B[3]=$true B[4]=$false B[5]=$false B[6]=$true Y=$procmux$2066_CMP
|
||
|
|
.cname $procmux$2066_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$false B[1]=$false B[2]=$true B[3]=$true B[4]=$false B[5]=$false B[6]=$true Y=$procmux$2067_CMP
|
||
|
|
.cname $procmux$2067_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$true B[1]=$true B[2]=$false B[3]=$true B[4]=$false B[5]=$false B[6]=$true Y=$procmux$2068_CMP
|
||
|
|
.cname $procmux$2068_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$false B[1]=$true B[2]=$false B[3]=$true B[4]=$false B[5]=$false B[6]=$true Y=$procmux$2069_CMP
|
||
|
|
.cname $procmux$2069_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$true B[1]=$true B[2]=$true B[3]=$true B[4]=$false B[5]=$true B[6]=$false Y=$procmux$206_CMP
|
||
|
|
.cname $procmux$206_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$true B[1]=$false B[2]=$false B[3]=$true B[4]=$false B[5]=$false B[6]=$true Y=$procmux$2070_CMP
|
||
|
|
.cname $procmux$2070_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$false B[1]=$false B[2]=$false B[3]=$true B[4]=$false B[5]=$false B[6]=$true Y=$procmux$2071_CMP
|
||
|
|
.cname $procmux$2071_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$true B[1]=$true B[2]=$true B[3]=$false B[4]=$false B[5]=$false B[6]=$true Y=$procmux$2072_CMP
|
||
|
|
.cname $procmux$2072_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$false B[1]=$true B[2]=$true B[3]=$false B[4]=$false B[5]=$false B[6]=$true Y=$procmux$2073_CMP
|
||
|
|
.cname $procmux$2073_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$true B[1]=$false B[2]=$true B[3]=$false B[4]=$false B[5]=$false B[6]=$true Y=$procmux$2074_CMP
|
||
|
|
.cname $procmux$2074_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$false B[1]=$false B[2]=$true B[3]=$false B[4]=$false B[5]=$false B[6]=$true Y=$procmux$2075_CMP
|
||
|
|
.cname $procmux$2075_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$true B[1]=$true B[2]=$false B[3]=$false B[4]=$false B[5]=$false B[6]=$true Y=$procmux$2076_CMP
|
||
|
|
.cname $procmux$2076_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$false B[1]=$true B[2]=$false B[3]=$false B[4]=$false B[5]=$false B[6]=$true Y=$procmux$2077_CMP
|
||
|
|
.cname $procmux$2077_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$true B[1]=$false B[2]=$false B[3]=$false B[4]=$false B[5]=$false B[6]=$true Y=$procmux$2078_CMP
|
||
|
|
.cname $procmux$2078_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$false B[1]=$false B[2]=$false B[3]=$false B[4]=$false B[5]=$false B[6]=$true Y=$procmux$2079_CMP
|
||
|
|
.cname $procmux$2079_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$false B[1]=$true B[2]=$true B[3]=$true B[4]=$false B[5]=$true B[6]=$false Y=$procmux$207_CMP
|
||
|
|
.cname $procmux$207_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$true B[1]=$true B[2]=$true B[3]=$true B[4]=$true B[5]=$true B[6]=$false Y=$procmux$2080_CMP
|
||
|
|
.cname $procmux$2080_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$false B[1]=$true B[2]=$true B[3]=$true B[4]=$true B[5]=$true B[6]=$false Y=$procmux$2081_CMP
|
||
|
|
.cname $procmux$2081_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$true B[1]=$false B[2]=$true B[3]=$true B[4]=$true B[5]=$true B[6]=$false Y=$procmux$2082_CMP
|
||
|
|
.cname $procmux$2082_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$false B[1]=$false B[2]=$true B[3]=$true B[4]=$true B[5]=$true B[6]=$false Y=$procmux$2083_CMP
|
||
|
|
.cname $procmux$2083_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$true B[1]=$true B[2]=$false B[3]=$true B[4]=$true B[5]=$true B[6]=$false Y=$procmux$2084_CMP
|
||
|
|
.cname $procmux$2084_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$false B[1]=$true B[2]=$false B[3]=$true B[4]=$true B[5]=$true B[6]=$false Y=$procmux$2085_CMP
|
||
|
|
.cname $procmux$2085_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$true B[1]=$false B[2]=$false B[3]=$true B[4]=$true B[5]=$true B[6]=$false Y=$procmux$2086_CMP
|
||
|
|
.cname $procmux$2086_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$false B[1]=$false B[2]=$false B[3]=$true B[4]=$true B[5]=$true B[6]=$false Y=$procmux$2087_CMP
|
||
|
|
.cname $procmux$2087_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$true B[1]=$true B[2]=$true B[3]=$false B[4]=$true B[5]=$true B[6]=$false Y=$procmux$2088_CMP
|
||
|
|
.cname $procmux$2088_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$false B[1]=$true B[2]=$true B[3]=$false B[4]=$true B[5]=$true B[6]=$false Y=$procmux$2089_CMP
|
||
|
|
.cname $procmux$2089_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$true B[1]=$false B[2]=$true B[3]=$true B[4]=$false B[5]=$true B[6]=$false Y=$procmux$208_CMP
|
||
|
|
.cname $procmux$208_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$true B[1]=$false B[2]=$true B[3]=$false B[4]=$true B[5]=$true B[6]=$false Y=$procmux$2090_CMP
|
||
|
|
.cname $procmux$2090_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$false B[1]=$false B[2]=$true B[3]=$false B[4]=$true B[5]=$true B[6]=$false Y=$procmux$2091_CMP
|
||
|
|
.cname $procmux$2091_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$true B[1]=$true B[2]=$false B[3]=$false B[4]=$true B[5]=$true B[6]=$false Y=$procmux$2092_CMP
|
||
|
|
.cname $procmux$2092_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$false B[1]=$true B[2]=$false B[3]=$false B[4]=$true B[5]=$true B[6]=$false Y=$procmux$2093_CMP
|
||
|
|
.cname $procmux$2093_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$true B[1]=$false B[2]=$false B[3]=$false B[4]=$true B[5]=$true B[6]=$false Y=$procmux$2094_CMP
|
||
|
|
.cname $procmux$2094_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$false B[1]=$false B[2]=$false B[3]=$false B[4]=$true B[5]=$true B[6]=$false Y=$procmux$2095_CMP
|
||
|
|
.cname $procmux$2095_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$true B[1]=$true B[2]=$true B[3]=$true B[4]=$false B[5]=$true B[6]=$false Y=$procmux$2096_CMP
|
||
|
|
.cname $procmux$2096_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$false B[1]=$true B[2]=$true B[3]=$true B[4]=$false B[5]=$true B[6]=$false Y=$procmux$2097_CMP
|
||
|
|
.cname $procmux$2097_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$true B[1]=$false B[2]=$true B[3]=$true B[4]=$false B[5]=$true B[6]=$false Y=$procmux$2098_CMP
|
||
|
|
.cname $procmux$2098_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$false B[1]=$false B[2]=$true B[3]=$true B[4]=$false B[5]=$true B[6]=$false Y=$procmux$2099_CMP
|
||
|
|
.cname $procmux$2099_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$false B[1]=$false B[2]=$true B[3]=$true B[4]=$false B[5]=$true B[6]=$false Y=$procmux$209_CMP
|
||
|
|
.cname $procmux$209_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$true B[1]=$true B[2]=$false B[3]=$true B[4]=$false B[5]=$true B[6]=$false Y=$procmux$2100_CMP
|
||
|
|
.cname $procmux$2100_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$false B[1]=$true B[2]=$false B[3]=$true B[4]=$false B[5]=$true B[6]=$false Y=$procmux$2101_CMP
|
||
|
|
.cname $procmux$2101_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$true B[1]=$false B[2]=$false B[3]=$true B[4]=$false B[5]=$true B[6]=$false Y=$procmux$2102_CMP
|
||
|
|
.cname $procmux$2102_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$false B[1]=$false B[2]=$false B[3]=$true B[4]=$false B[5]=$true B[6]=$false Y=$procmux$2103_CMP
|
||
|
|
.cname $procmux$2103_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$true B[1]=$true B[2]=$true B[3]=$false B[4]=$false B[5]=$true B[6]=$false Y=$procmux$2104_CMP
|
||
|
|
.cname $procmux$2104_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$false B[1]=$true B[2]=$true B[3]=$false B[4]=$false B[5]=$true B[6]=$false Y=$procmux$2105_CMP
|
||
|
|
.cname $procmux$2105_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$true B[1]=$false B[2]=$true B[3]=$false B[4]=$false B[5]=$true B[6]=$false Y=$procmux$2106_CMP
|
||
|
|
.cname $procmux$2106_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$false B[1]=$false B[2]=$true B[3]=$false B[4]=$false B[5]=$true B[6]=$false Y=$procmux$2107_CMP
|
||
|
|
.cname $procmux$2107_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$true B[1]=$true B[2]=$false B[3]=$false B[4]=$false B[5]=$true B[6]=$false Y=$procmux$2108_CMP
|
||
|
|
.cname $procmux$2108_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$false B[1]=$true B[2]=$false B[3]=$false B[4]=$false B[5]=$true B[6]=$false Y=$procmux$2109_CMP
|
||
|
|
.cname $procmux$2109_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$true B[1]=$true B[2]=$false B[3]=$true B[4]=$false B[5]=$true B[6]=$false Y=$procmux$210_CMP
|
||
|
|
.cname $procmux$210_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$true B[1]=$false B[2]=$false B[3]=$false B[4]=$false B[5]=$true B[6]=$false Y=$procmux$2110_CMP
|
||
|
|
.cname $procmux$2110_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$false B[1]=$false B[2]=$false B[3]=$false B[4]=$false B[5]=$true B[6]=$false Y=$procmux$2111_CMP
|
||
|
|
.cname $procmux$2111_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$true B[1]=$true B[2]=$true B[3]=$true B[4]=$true B[5]=$false B[6]=$false Y=$procmux$2112_CMP
|
||
|
|
.cname $procmux$2112_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$false B[1]=$true B[2]=$true B[3]=$true B[4]=$true B[5]=$false B[6]=$false Y=$procmux$2113_CMP
|
||
|
|
.cname $procmux$2113_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$true B[1]=$false B[2]=$true B[3]=$true B[4]=$true B[5]=$false B[6]=$false Y=$procmux$2114_CMP
|
||
|
|
.cname $procmux$2114_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$false B[1]=$false B[2]=$true B[3]=$true B[4]=$true B[5]=$false B[6]=$false Y=$procmux$2115_CMP
|
||
|
|
.cname $procmux$2115_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$true B[1]=$true B[2]=$false B[3]=$true B[4]=$true B[5]=$false B[6]=$false Y=$procmux$2116_CMP
|
||
|
|
.cname $procmux$2116_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$false B[1]=$true B[2]=$false B[3]=$true B[4]=$true B[5]=$false B[6]=$false Y=$procmux$2117_CMP
|
||
|
|
.cname $procmux$2117_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$true B[1]=$false B[2]=$false B[3]=$true B[4]=$true B[5]=$false B[6]=$false Y=$procmux$2118_CMP
|
||
|
|
.cname $procmux$2118_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$false B[1]=$false B[2]=$false B[3]=$true B[4]=$true B[5]=$false B[6]=$false Y=$procmux$2119_CMP
|
||
|
|
.cname $procmux$2119_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$false B[1]=$true B[2]=$false B[3]=$true B[4]=$false B[5]=$true B[6]=$false Y=$procmux$211_CMP
|
||
|
|
.cname $procmux$211_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$true B[1]=$true B[2]=$true B[3]=$false B[4]=$true B[5]=$false B[6]=$false Y=$procmux$2120_CMP
|
||
|
|
.cname $procmux$2120_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$false B[1]=$true B[2]=$true B[3]=$false B[4]=$true B[5]=$false B[6]=$false Y=$procmux$2121_CMP
|
||
|
|
.cname $procmux$2121_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$true B[1]=$false B[2]=$true B[3]=$false B[4]=$true B[5]=$false B[6]=$false Y=$procmux$2122_CMP
|
||
|
|
.cname $procmux$2122_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$false B[1]=$false B[2]=$true B[3]=$false B[4]=$true B[5]=$false B[6]=$false Y=$procmux$2123_CMP
|
||
|
|
.cname $procmux$2123_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$true B[1]=$true B[2]=$false B[3]=$false B[4]=$true B[5]=$false B[6]=$false Y=$procmux$2124_CMP
|
||
|
|
.cname $procmux$2124_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$false B[1]=$true B[2]=$false B[3]=$false B[4]=$true B[5]=$false B[6]=$false Y=$procmux$2125_CMP
|
||
|
|
.cname $procmux$2125_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$true B[1]=$false B[2]=$false B[3]=$false B[4]=$true B[5]=$false B[6]=$false Y=$procmux$2126_CMP
|
||
|
|
.cname $procmux$2126_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$false B[1]=$false B[2]=$false B[3]=$false B[4]=$true B[5]=$false B[6]=$false Y=$procmux$2127_CMP
|
||
|
|
.cname $procmux$2127_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$true B[1]=$true B[2]=$true B[3]=$true B[4]=$false B[5]=$false B[6]=$false Y=$procmux$2128_CMP
|
||
|
|
.cname $procmux$2128_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$false B[1]=$true B[2]=$true B[3]=$true B[4]=$false B[5]=$false B[6]=$false Y=$procmux$2129_CMP
|
||
|
|
.cname $procmux$2129_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$true B[1]=$false B[2]=$false B[3]=$true B[4]=$false B[5]=$true B[6]=$false Y=$procmux$212_CMP
|
||
|
|
.cname $procmux$212_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$true B[1]=$false B[2]=$true B[3]=$true B[4]=$false B[5]=$false B[6]=$false Y=$procmux$2130_CMP
|
||
|
|
.cname $procmux$2130_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$false B[1]=$false B[2]=$true B[3]=$true B[4]=$false B[5]=$false B[6]=$false Y=$procmux$2131_CMP
|
||
|
|
.cname $procmux$2131_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$true B[1]=$true B[2]=$false B[3]=$true B[4]=$false B[5]=$false B[6]=$false Y=$procmux$2132_CMP
|
||
|
|
.cname $procmux$2132_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$false B[1]=$true B[2]=$false B[3]=$true B[4]=$false B[5]=$false B[6]=$false Y=$procmux$2133_CMP
|
||
|
|
.cname $procmux$2133_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$true B[1]=$false B[2]=$false B[3]=$true B[4]=$false B[5]=$false B[6]=$false Y=$procmux$2134_CMP
|
||
|
|
.cname $procmux$2134_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$false B[1]=$false B[2]=$false B[3]=$true B[4]=$false B[5]=$false B[6]=$false Y=$procmux$2135_CMP
|
||
|
|
.cname $procmux$2135_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$true B[1]=$true B[2]=$true B[3]=$false B[4]=$false B[5]=$false B[6]=$false Y=$procmux$2136_CMP
|
||
|
|
.cname $procmux$2136_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$false B[1]=$true B[2]=$true B[3]=$false B[4]=$false B[5]=$false B[6]=$false Y=$procmux$2137_CMP
|
||
|
|
.cname $procmux$2137_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$true B[1]=$false B[2]=$true B[3]=$false B[4]=$false B[5]=$false B[6]=$false Y=$procmux$2138_CMP
|
||
|
|
.cname $procmux$2138_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$false B[1]=$false B[2]=$true B[3]=$false B[4]=$false B[5]=$false B[6]=$false Y=$procmux$2139_CMP
|
||
|
|
.cname $procmux$2139_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$false B[1]=$false B[2]=$false B[3]=$true B[4]=$false B[5]=$true B[6]=$false Y=$procmux$213_CMP
|
||
|
|
.cname $procmux$213_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$true B[1]=$true B[2]=$false B[3]=$false B[4]=$false B[5]=$false B[6]=$false Y=$procmux$2140_CMP
|
||
|
|
.cname $procmux$2140_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$false B[1]=$true B[2]=$false B[3]=$false B[4]=$false B[5]=$false B[6]=$false Y=$procmux$2141_CMP
|
||
|
|
.cname $procmux$2141_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$true B[1]=$false B[2]=$false B[3]=$false B[4]=$false B[5]=$false B[6]=$false Y=$procmux$2142_CMP
|
||
|
|
.cname $procmux$2142_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $mux A[0]=C[0] A[1]=C[1] A[2]=C[2] A[3]=C[3] A[4]=C[4] A[5]=C[5] A[6]=C[6] A[7]=C[7] A[8]=C[8] A[9]=C[9] A[10]=C[10] A[11]=C[11] A[12]=C[12] A[13]=C[13] A[14]=C[14] A[15]=C[15] A[16]=C[16] A[17]=C[17] A[18]=C[18] A[19]=C[19] A[20]=C[20] A[21]=C[21] A[22]=C[22] A[23]=C[23] A[24]=C[24] A[25]=C[25] A[26]=C[26] A[27]=C[27] A[28]=C[28] A[29]=C[29] A[30]=C[30] A[31]=C[31] B[0]=$false B[1]=$true B[2]=$true B[3]=$true B[4]=$true B[5]=$true B[6]=$true B[7]=$true B[8]=$false B[9]=$false B[10]=$true B[11]=$true B[12]=$true B[13]=$false B[14]=$true B[15]=$true B[16]=$false B[17]=$true B[18]=$false B[19]=$true B[20]=$true B[21]=$true B[22]=$false B[23]=$true B[24]=$false B[25]=$false B[26]=$false B[27]=$true B[28]=$true B[29]=$false B[30]=$false B[31]=$true S=$procmux$2146_CMP Y[0]=$procmux$2145_Y[0] Y[1]=$procmux$2145_Y[1] Y[2]=$procmux$2145_Y[2] Y[3]=$procmux$2145_Y[3] Y[4]=$procmux$2145_Y[4] Y[5]=$procmux$2145_Y[5] Y[6]=$procmux$2145_Y[6] Y[7]=$procmux$2145_Y[7] Y[8]=$procmux$2145_Y[8] Y[9]=$procmux$2145_Y[9] Y[10]=$procmux$2145_Y[10] Y[11]=$procmux$2145_Y[11] Y[12]=$procmux$2145_Y[12] Y[13]=$procmux$2145_Y[13] Y[14]=$procmux$2145_Y[14] Y[15]=$procmux$2145_Y[15] Y[16]=$procmux$2145_Y[16] Y[17]=$procmux$2145_Y[17] Y[18]=$procmux$2145_Y[18] Y[19]=$procmux$2145_Y[19] Y[20]=$procmux$2145_Y[20] Y[21]=$procmux$2145_Y[21] Y[22]=$procmux$2145_Y[22] Y[23]=$procmux$2145_Y[23] Y[24]=$procmux$2145_Y[24] Y[25]=$procmux$2145_Y[25] Y[26]=$procmux$2145_Y[26] Y[27]=$procmux$2145_Y[27] Y[28]=$procmux$2145_Y[28] Y[29]=$procmux$2145_Y[29] Y[30]=$procmux$2145_Y[30] Y[31]=$procmux$2145_Y[31]
|
||
|
|
.cname $procmux$2145
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:198"
|
||
|
|
.param WIDTH 00000000000000000000000000100000
|
||
|
|
.subckt $eq A=cmd[2] B=$false Y=$procmux$2146_CMP
|
||
|
|
.cname $procmux$2146_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:198"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000001
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000001
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $mux A[0]=C[0] A[1]=C[1] A[2]=C[2] A[3]=C[3] A[4]=C[4] A[5]=C[5] A[6]=C[6] A[7]=C[7] A[8]=C[8] A[9]=C[9] A[10]=C[10] A[11]=C[11] A[12]=C[12] A[13]=C[13] A[14]=C[14] A[15]=C[15] A[16]=C[16] A[17]=C[17] A[18]=C[18] A[19]=C[19] A[20]=C[20] A[21]=C[21] A[22]=C[22] A[23]=C[23] A[24]=C[24] A[25]=C[25] A[26]=C[26] A[27]=C[27] A[28]=C[28] A[29]=C[29] A[30]=C[30] A[31]=C[31] B[0]=$procmux$2145_Y[0] B[1]=$procmux$2145_Y[1] B[2]=$procmux$2145_Y[2] B[3]=$procmux$2145_Y[3] B[4]=$procmux$2145_Y[4] B[5]=$procmux$2145_Y[5] B[6]=$procmux$2145_Y[6] B[7]=$procmux$2145_Y[7] B[8]=$procmux$2145_Y[8] B[9]=$procmux$2145_Y[9] B[10]=$procmux$2145_Y[10] B[11]=$procmux$2145_Y[11] B[12]=$procmux$2145_Y[12] B[13]=$procmux$2145_Y[13] B[14]=$procmux$2145_Y[14] B[15]=$procmux$2145_Y[15] B[16]=$procmux$2145_Y[16] B[17]=$procmux$2145_Y[17] B[18]=$procmux$2145_Y[18] B[19]=$procmux$2145_Y[19] B[20]=$procmux$2145_Y[20] B[21]=$procmux$2145_Y[21] B[22]=$procmux$2145_Y[22] B[23]=$procmux$2145_Y[23] B[24]=$procmux$2145_Y[24] B[25]=$procmux$2145_Y[25] B[26]=$procmux$2145_Y[26] B[27]=$procmux$2145_Y[27] B[28]=$procmux$2145_Y[28] B[29]=$procmux$2145_Y[29] B[30]=$procmux$2145_Y[30] B[31]=$procmux$2145_Y[31] S=$procmux$2148_CMP Y[0]=$procmux$2147_Y[0] Y[1]=$procmux$2147_Y[1] Y[2]=$procmux$2147_Y[2] Y[3]=$procmux$2147_Y[3] Y[4]=$procmux$2147_Y[4] Y[5]=$procmux$2147_Y[5] Y[6]=$procmux$2147_Y[6] Y[7]=$procmux$2147_Y[7] Y[8]=$procmux$2147_Y[8] Y[9]=$procmux$2147_Y[9] Y[10]=$procmux$2147_Y[10] Y[11]=$procmux$2147_Y[11] Y[12]=$procmux$2147_Y[12] Y[13]=$procmux$2147_Y[13] Y[14]=$procmux$2147_Y[14] Y[15]=$procmux$2147_Y[15] Y[16]=$procmux$2147_Y[16] Y[17]=$procmux$2147_Y[17] Y[18]=$procmux$2147_Y[18] Y[19]=$procmux$2147_Y[19] Y[20]=$procmux$2147_Y[20] Y[21]=$procmux$2147_Y[21] Y[22]=$procmux$2147_Y[22] Y[23]=$procmux$2147_Y[23] Y[24]=$procmux$2147_Y[24] Y[25]=$procmux$2147_Y[25] Y[26]=$procmux$2147_Y[26] Y[27]=$procmux$2147_Y[27] Y[28]=$procmux$2147_Y[28] Y[29]=$procmux$2147_Y[29] Y[30]=$procmux$2147_Y[30] Y[31]=$procmux$2147_Y[31]
|
||
|
|
.cname $procmux$2147
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:191"
|
||
|
|
.param WIDTH 00000000000000000000000000100000
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$false B[1]=$false B[2]=$false B[3]=$false B[4]=$false B[5]=$false B[6]=$false Y=$procmux$2149_CMP
|
||
|
|
.cname $procmux$2149_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$true B[1]=$true B[2]=$true B[3]=$false B[4]=$false B[5]=$true B[6]=$false Y=$procmux$214_CMP
|
||
|
|
.cname $procmux$214_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $mux A[0]=$procmux$2062_Y[0] A[1]=$procmux$2062_Y[1] A[2]=$procmux$2062_Y[2] A[3]=$procmux$2062_Y[3] A[4]=$procmux$2062_Y[4] A[5]=$procmux$2062_Y[5] A[6]=$procmux$2062_Y[6] A[7]=$procmux$2062_Y[7] A[8]=$procmux$2062_Y[8] A[9]=$procmux$2062_Y[9] A[10]=$procmux$2062_Y[10] A[11]=$procmux$2062_Y[11] A[12]=$procmux$2062_Y[12] A[13]=$procmux$2062_Y[13] A[14]=$procmux$2062_Y[14] A[15]=$procmux$2062_Y[15] A[16]=$procmux$2062_Y[16] A[17]=$procmux$2062_Y[17] A[18]=$procmux$2062_Y[18] A[19]=$procmux$2062_Y[19] A[20]=$procmux$2062_Y[20] A[21]=$procmux$2062_Y[21] A[22]=$procmux$2062_Y[22] A[23]=$procmux$2062_Y[23] A[24]=$procmux$2062_Y[24] A[25]=$procmux$2062_Y[25] A[26]=$procmux$2062_Y[26] A[27]=$procmux$2062_Y[27] A[28]=$procmux$2062_Y[28] A[29]=$procmux$2062_Y[29] A[30]=$procmux$2062_Y[30] A[31]=$procmux$2062_Y[31] B[0]=$false B[1]=$false B[2]=$false B[3]=$false B[4]=$false B[5]=$false B[6]=$false B[7]=$false B[8]=$false B[9]=$false B[10]=$false B[11]=$false B[12]=$false B[13]=$false B[14]=$false B[15]=$false B[16]=$false B[17]=$false B[18]=$false B[19]=$false B[20]=$false B[21]=$false B[22]=$false B[23]=$false B[24]=$false B[25]=$false B[26]=$false B[27]=$false B[28]=$false B[29]=$false B[30]=$false B[31]=$false S=$procmux$2152_CMP Y[0]=$procmux$2151_Y[0] Y[1]=$procmux$2151_Y[1] Y[2]=$procmux$2151_Y[2] Y[3]=$procmux$2151_Y[3] Y[4]=$procmux$2151_Y[4] Y[5]=$procmux$2151_Y[5] Y[6]=$procmux$2151_Y[6] Y[7]=$procmux$2151_Y[7] Y[8]=$procmux$2151_Y[8] Y[9]=$procmux$2151_Y[9] Y[10]=$procmux$2151_Y[10] Y[11]=$procmux$2151_Y[11] Y[12]=$procmux$2151_Y[12] Y[13]=$procmux$2151_Y[13] Y[14]=$procmux$2151_Y[14] Y[15]=$procmux$2151_Y[15] Y[16]=$procmux$2151_Y[16] Y[17]=$procmux$2151_Y[17] Y[18]=$procmux$2151_Y[18] Y[19]=$procmux$2151_Y[19] Y[20]=$procmux$2151_Y[20] Y[21]=$procmux$2151_Y[21] Y[22]=$procmux$2151_Y[22] Y[23]=$procmux$2151_Y[23] Y[24]=$procmux$2151_Y[24] Y[25]=$procmux$2151_Y[25] Y[26]=$procmux$2151_Y[26] Y[27]=$procmux$2151_Y[27] Y[28]=$procmux$2151_Y[28] Y[29]=$procmux$2151_Y[29] Y[30]=$procmux$2151_Y[30] Y[31]=$procmux$2151_Y[31]
|
||
|
|
.cname $procmux$2151
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:150"
|
||
|
|
.param WIDTH 00000000000000000000000000100000
|
||
|
|
.subckt $pmux A[0]=B[0] A[1]=B[1] A[2]=B[2] A[3]=B[3] A[4]=B[4] A[5]=B[5] A[6]=B[6] A[7]=B[7] A[8]=B[8] A[9]=B[9] A[10]=B[10] A[11]=B[11] A[12]=B[12] A[13]=B[13] A[14]=B[14] A[15]=B[15] A[16]=B[16] A[17]=B[17] A[18]=B[18] A[19]=B[19] A[20]=B[20] A[21]=B[21] A[22]=B[22] A[23]=B[23] A[24]=B[24] A[25]=B[25] A[26]=B[26] A[27]=B[27] A[28]=B[28] A[29]=B[29] A[30]=B[30] A[31]=B[31] B[0]=$add$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:2090$30_Y[0] B[1]=$add$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:2090$30_Y[1] B[2]=$add$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:2090$30_Y[2] B[3]=$add$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:2090$30_Y[3] B[4]=$add$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:2090$30_Y[4] B[5]=$add$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:2090$30_Y[5] B[6]=$add$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:2090$30_Y[6] B[7]=$add$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:2090$30_Y[7] B[8]=$add$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:2090$30_Y[8] B[9]=$add$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:2090$30_Y[9] B[10]=$add$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:2090$30_Y[10] B[11]=$add$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:2090$30_Y[11] B[12]=$add$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:2090$30_Y[12] B[13]=$add$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:2090$30_Y[13] B[14]=$add$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:2090$30_Y[14] B[15]=$add$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:2090$30_Y[15] B[16]=$add$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:2090$30_Y[16] B[17]=$add$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:2090$30_Y[17] B[18]=$add$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:2090$30_Y[18] B[19]=$add$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:2090$30_Y[19] B[20]=$add$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:2090$30_Y[20] B[21]=$add$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:2090$30_Y[21] B[22]=$add$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:2090$30_Y[22] B[23]=$add$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:2090$30_Y[23] B[24]=$add$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:2090$30_Y[24] B[25]=$add$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:2090$30_Y[25] B[26]=$add$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:2090$30_Y[26] B[27]=$add$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:2090$30_Y[27] B[28]=$add$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:2090$30_Y[28] B[29]=$add$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:2090$30_Y[29] B[30]=$add$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:2090$30_Y[30] B[31]=$add$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:2090$30_Y[31] B[32]=A[0] B[33]=A[1] B[34]=A[2] B[35]=A[3] B[36]=A[4] B[37]=A[5] B[38]=A[6] B[39]=A[7] B[40]=A[8] B[41]=A[9] B[42]=A[10] B[43]=A[11] B[44]=A[12] B[45]=A[13] B[46]=A[14] B[47]=A[15] B[48]=A[16] B[49]=A[17] B[50]=A[18] B[51]=A[19] B[52]=A[20] B[53]=A[21] B[54]=A[22] B[55]=A[23] B[56]=A[24] B[57]=A[25] B[58]=A[26] B[59]=A[27] B[60]=A[28] B[61]=A[29] B[62]=A[30] B[63]=A[31] B[64]=A[0] B[65]=A[1] B[66]=A[2] B[67]=A[3] B[68]=A[4] B[69]=A[5] B[70]=A[6] B[71]=A[7] B[72]=A[8] B[73]=A[9] B[74]=A[10] B[75]=A[11] B[76]=A[12] B[77]=A[13] B[78]=A[14] B[79]=A[15] B[80]=A[16] B[81]=A[17] B[82]=A[18] B[83]=A[19] B[84]=A[20] B[85]=A[21] B[86]=A[22] B[87]=A[23] B[88]=A[24] B[89]=A[25] B[90]=A[26] B[91]=A[27] B[92]=A[28] B[93]=A[29] B[94]=A[30] B[95]=A[31] B[96]=A[0] B[97]=A[1] B[98]=A[2] B[99]=A[3] B[100]=A[4] B[101]=A[5] B[102]=A[6] B[103]=A[7] B[104]=A[8] B[105]=A[9] B[106]=A[10] B[107]=A[11] B[108]=A[12] B[109]=A[13] B[110]=A[14] B[111]=A[15] B[112]=A[16] B[113]=A[17] B[114]=A[18] B[115]=A[19] B[116]=A[20] B[117]=A[21] B[118]=A[22] B[119]=A[23] B[120]=A[24] B[121]=A[25] B[122]=A[26] B[123]=A[27] B[124]=A[28] B[125]=A[29] B[126]=A[30] B[127]=A[31] B[128]=A[0] B[129]=A[1] B[130]=A[2] B[131]=A[3] B[132]=A[4] B[133]=A[5] B[134]=A[6] B[135]=
|
||
|
|
.cname $procmux$2154
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param S_WIDTH 00000000000000000000000001010001
|
||
|
|
.param WIDTH 00000000000000000000000000100000
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$false B[1]=$false B[2]=$false B[3]=$false B[4]=$true B[5]=$false B[6]=$true Y=$procmux$2155_CMP
|
||
|
|
.cname $procmux$2155_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$true B[1]=$true B[2]=$true B[3]=$true B[4]=$false B[5]=$false B[6]=$true Y=$procmux$2156_CMP
|
||
|
|
.cname $procmux$2156_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$false B[1]=$true B[2]=$true B[3]=$true B[4]=$false B[5]=$false B[6]=$true Y=$procmux$2157_CMP
|
||
|
|
.cname $procmux$2157_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$true B[1]=$false B[2]=$true B[3]=$true B[4]=$false B[5]=$false B[6]=$true Y=$procmux$2158_CMP
|
||
|
|
.cname $procmux$2158_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$false B[1]=$false B[2]=$true B[3]=$true B[4]=$false B[5]=$false B[6]=$true Y=$procmux$2159_CMP
|
||
|
|
.cname $procmux$2159_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$false B[1]=$true B[2]=$true B[3]=$false B[4]=$false B[5]=$true B[6]=$false Y=$procmux$215_CMP
|
||
|
|
.cname $procmux$215_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$true B[1]=$true B[2]=$false B[3]=$true B[4]=$false B[5]=$false B[6]=$true Y=$procmux$2160_CMP
|
||
|
|
.cname $procmux$2160_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$false B[1]=$true B[2]=$false B[3]=$true B[4]=$false B[5]=$false B[6]=$true Y=$procmux$2161_CMP
|
||
|
|
.cname $procmux$2161_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$true B[1]=$false B[2]=$false B[3]=$true B[4]=$false B[5]=$false B[6]=$true Y=$procmux$2162_CMP
|
||
|
|
.cname $procmux$2162_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$false B[1]=$false B[2]=$false B[3]=$true B[4]=$false B[5]=$false B[6]=$true Y=$procmux$2163_CMP
|
||
|
|
.cname $procmux$2163_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$true B[1]=$true B[2]=$true B[3]=$false B[4]=$false B[5]=$false B[6]=$true Y=$procmux$2164_CMP
|
||
|
|
.cname $procmux$2164_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$false B[1]=$true B[2]=$true B[3]=$false B[4]=$false B[5]=$false B[6]=$true Y=$procmux$2165_CMP
|
||
|
|
.cname $procmux$2165_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$true B[1]=$false B[2]=$true B[3]=$false B[4]=$false B[5]=$false B[6]=$true Y=$procmux$2166_CMP
|
||
|
|
.cname $procmux$2166_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$false B[1]=$false B[2]=$true B[3]=$false B[4]=$false B[5]=$false B[6]=$true Y=$procmux$2167_CMP
|
||
|
|
.cname $procmux$2167_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$true B[1]=$true B[2]=$false B[3]=$false B[4]=$false B[5]=$false B[6]=$true Y=$procmux$2168_CMP
|
||
|
|
.cname $procmux$2168_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$false B[1]=$true B[2]=$false B[3]=$false B[4]=$false B[5]=$false B[6]=$true Y=$procmux$2169_CMP
|
||
|
|
.cname $procmux$2169_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$true B[1]=$false B[2]=$true B[3]=$false B[4]=$false B[5]=$true B[6]=$false Y=$procmux$216_CMP
|
||
|
|
.cname $procmux$216_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$true B[1]=$false B[2]=$false B[3]=$false B[4]=$false B[5]=$false B[6]=$true Y=$procmux$2170_CMP
|
||
|
|
.cname $procmux$2170_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$false B[1]=$false B[2]=$false B[3]=$false B[4]=$false B[5]=$false B[6]=$true Y=$procmux$2171_CMP
|
||
|
|
.cname $procmux$2171_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$true B[1]=$true B[2]=$true B[3]=$true B[4]=$true B[5]=$true B[6]=$false Y=$procmux$2172_CMP
|
||
|
|
.cname $procmux$2172_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$false B[1]=$true B[2]=$true B[3]=$true B[4]=$true B[5]=$true B[6]=$false Y=$procmux$2173_CMP
|
||
|
|
.cname $procmux$2173_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$true B[1]=$false B[2]=$true B[3]=$true B[4]=$true B[5]=$true B[6]=$false Y=$procmux$2174_CMP
|
||
|
|
.cname $procmux$2174_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$false B[1]=$false B[2]=$true B[3]=$true B[4]=$true B[5]=$true B[6]=$false Y=$procmux$2175_CMP
|
||
|
|
.cname $procmux$2175_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$true B[1]=$true B[2]=$false B[3]=$true B[4]=$true B[5]=$true B[6]=$false Y=$procmux$2176_CMP
|
||
|
|
.cname $procmux$2176_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$false B[1]=$true B[2]=$false B[3]=$true B[4]=$true B[5]=$true B[6]=$false Y=$procmux$2177_CMP
|
||
|
|
.cname $procmux$2177_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$true B[1]=$false B[2]=$false B[3]=$true B[4]=$true B[5]=$true B[6]=$false Y=$procmux$2178_CMP
|
||
|
|
.cname $procmux$2178_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$false B[1]=$false B[2]=$false B[3]=$true B[4]=$true B[5]=$true B[6]=$false Y=$procmux$2179_CMP
|
||
|
|
.cname $procmux$2179_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$false B[1]=$false B[2]=$true B[3]=$false B[4]=$false B[5]=$true B[6]=$false Y=$procmux$217_CMP
|
||
|
|
.cname $procmux$217_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$true B[1]=$true B[2]=$true B[3]=$false B[4]=$true B[5]=$true B[6]=$false Y=$procmux$2180_CMP
|
||
|
|
.cname $procmux$2180_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$false B[1]=$true B[2]=$true B[3]=$false B[4]=$true B[5]=$true B[6]=$false Y=$procmux$2181_CMP
|
||
|
|
.cname $procmux$2181_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$true B[1]=$false B[2]=$true B[3]=$false B[4]=$true B[5]=$true B[6]=$false Y=$procmux$2182_CMP
|
||
|
|
.cname $procmux$2182_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$false B[1]=$false B[2]=$true B[3]=$false B[4]=$true B[5]=$true B[6]=$false Y=$procmux$2183_CMP
|
||
|
|
.cname $procmux$2183_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$true B[1]=$true B[2]=$false B[3]=$false B[4]=$true B[5]=$true B[6]=$false Y=$procmux$2184_CMP
|
||
|
|
.cname $procmux$2184_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$false B[1]=$true B[2]=$false B[3]=$false B[4]=$true B[5]=$true B[6]=$false Y=$procmux$2185_CMP
|
||
|
|
.cname $procmux$2185_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$true B[1]=$false B[2]=$false B[3]=$false B[4]=$true B[5]=$true B[6]=$false Y=$procmux$2186_CMP
|
||
|
|
.cname $procmux$2186_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$false B[1]=$false B[2]=$false B[3]=$false B[4]=$true B[5]=$true B[6]=$false Y=$procmux$2187_CMP
|
||
|
|
.cname $procmux$2187_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$true B[1]=$true B[2]=$true B[3]=$true B[4]=$false B[5]=$true B[6]=$false Y=$procmux$2188_CMP
|
||
|
|
.cname $procmux$2188_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$false B[1]=$true B[2]=$true B[3]=$true B[4]=$false B[5]=$true B[6]=$false Y=$procmux$2189_CMP
|
||
|
|
.cname $procmux$2189_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$true B[1]=$true B[2]=$false B[3]=$false B[4]=$false B[5]=$true B[6]=$false Y=$procmux$218_CMP
|
||
|
|
.cname $procmux$218_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$true B[1]=$false B[2]=$true B[3]=$true B[4]=$false B[5]=$true B[6]=$false Y=$procmux$2190_CMP
|
||
|
|
.cname $procmux$2190_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$false B[1]=$false B[2]=$true B[3]=$true B[4]=$false B[5]=$true B[6]=$false Y=$procmux$2191_CMP
|
||
|
|
.cname $procmux$2191_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$true B[1]=$true B[2]=$false B[3]=$true B[4]=$false B[5]=$true B[6]=$false Y=$procmux$2192_CMP
|
||
|
|
.cname $procmux$2192_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$false B[1]=$true B[2]=$false B[3]=$true B[4]=$false B[5]=$true B[6]=$false Y=$procmux$2193_CMP
|
||
|
|
.cname $procmux$2193_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$true B[1]=$false B[2]=$false B[3]=$true B[4]=$false B[5]=$true B[6]=$false Y=$procmux$2194_CMP
|
||
|
|
.cname $procmux$2194_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$false B[1]=$false B[2]=$false B[3]=$true B[4]=$false B[5]=$true B[6]=$false Y=$procmux$2195_CMP
|
||
|
|
.cname $procmux$2195_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$true B[1]=$true B[2]=$true B[3]=$false B[4]=$false B[5]=$true B[6]=$false Y=$procmux$2196_CMP
|
||
|
|
.cname $procmux$2196_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$false B[1]=$true B[2]=$true B[3]=$false B[4]=$false B[5]=$true B[6]=$false Y=$procmux$2197_CMP
|
||
|
|
.cname $procmux$2197_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$true B[1]=$false B[2]=$true B[3]=$false B[4]=$false B[5]=$true B[6]=$false Y=$procmux$2198_CMP
|
||
|
|
.cname $procmux$2198_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$false B[1]=$false B[2]=$true B[3]=$false B[4]=$false B[5]=$true B[6]=$false Y=$procmux$2199_CMP
|
||
|
|
.cname $procmux$2199_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$false B[1]=$true B[2]=$false B[3]=$false B[4]=$false B[5]=$true B[6]=$false Y=$procmux$219_CMP
|
||
|
|
.cname $procmux$219_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$true B[1]=$true B[2]=$false B[3]=$false B[4]=$false B[5]=$true B[6]=$false Y=$procmux$2200_CMP
|
||
|
|
.cname $procmux$2200_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$false B[1]=$true B[2]=$false B[3]=$false B[4]=$false B[5]=$true B[6]=$false Y=$procmux$2201_CMP
|
||
|
|
.cname $procmux$2201_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$true B[1]=$false B[2]=$false B[3]=$false B[4]=$false B[5]=$true B[6]=$false Y=$procmux$2202_CMP
|
||
|
|
.cname $procmux$2202_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$false B[1]=$false B[2]=$false B[3]=$false B[4]=$false B[5]=$true B[6]=$false Y=$procmux$2203_CMP
|
||
|
|
.cname $procmux$2203_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$true B[1]=$true B[2]=$true B[3]=$true B[4]=$true B[5]=$false B[6]=$false Y=$procmux$2204_CMP
|
||
|
|
.cname $procmux$2204_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$false B[1]=$true B[2]=$true B[3]=$true B[4]=$true B[5]=$false B[6]=$false Y=$procmux$2205_CMP
|
||
|
|
.cname $procmux$2205_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$true B[1]=$false B[2]=$true B[3]=$true B[4]=$true B[5]=$false B[6]=$false Y=$procmux$2206_CMP
|
||
|
|
.cname $procmux$2206_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$false B[1]=$false B[2]=$true B[3]=$true B[4]=$true B[5]=$false B[6]=$false Y=$procmux$2207_CMP
|
||
|
|
.cname $procmux$2207_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$true B[1]=$true B[2]=$false B[3]=$true B[4]=$true B[5]=$false B[6]=$false Y=$procmux$2208_CMP
|
||
|
|
.cname $procmux$2208_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$false B[1]=$true B[2]=$false B[3]=$true B[4]=$true B[5]=$false B[6]=$false Y=$procmux$2209_CMP
|
||
|
|
.cname $procmux$2209_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$true B[1]=$false B[2]=$false B[3]=$false B[4]=$false B[5]=$true B[6]=$false Y=$procmux$220_CMP
|
||
|
|
.cname $procmux$220_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$true B[1]=$false B[2]=$false B[3]=$true B[4]=$true B[5]=$false B[6]=$false Y=$procmux$2210_CMP
|
||
|
|
.cname $procmux$2210_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$false B[1]=$false B[2]=$false B[3]=$true B[4]=$true B[5]=$false B[6]=$false Y=$procmux$2211_CMP
|
||
|
|
.cname $procmux$2211_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$true B[1]=$true B[2]=$true B[3]=$false B[4]=$true B[5]=$false B[6]=$false Y=$procmux$2212_CMP
|
||
|
|
.cname $procmux$2212_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$false B[1]=$true B[2]=$true B[3]=$false B[4]=$true B[5]=$false B[6]=$false Y=$procmux$2213_CMP
|
||
|
|
.cname $procmux$2213_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$true B[1]=$false B[2]=$true B[3]=$false B[4]=$true B[5]=$false B[6]=$false Y=$procmux$2214_CMP
|
||
|
|
.cname $procmux$2214_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$false B[1]=$false B[2]=$true B[3]=$false B[4]=$true B[5]=$false B[6]=$false Y=$procmux$2215_CMP
|
||
|
|
.cname $procmux$2215_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$true B[1]=$true B[2]=$false B[3]=$false B[4]=$true B[5]=$false B[6]=$false Y=$procmux$2216_CMP
|
||
|
|
.cname $procmux$2216_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$false B[1]=$true B[2]=$false B[3]=$false B[4]=$true B[5]=$false B[6]=$false Y=$procmux$2217_CMP
|
||
|
|
.cname $procmux$2217_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$true B[1]=$false B[2]=$false B[3]=$false B[4]=$true B[5]=$false B[6]=$false Y=$procmux$2218_CMP
|
||
|
|
.cname $procmux$2218_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$false B[1]=$false B[2]=$false B[3]=$false B[4]=$true B[5]=$false B[6]=$false Y=$procmux$2219_CMP
|
||
|
|
.cname $procmux$2219_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$false B[1]=$false B[2]=$false B[3]=$false B[4]=$false B[5]=$true B[6]=$false Y=$procmux$221_CMP
|
||
|
|
.cname $procmux$221_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$true B[1]=$true B[2]=$true B[3]=$true B[4]=$false B[5]=$false B[6]=$false Y=$procmux$2220_CMP
|
||
|
|
.cname $procmux$2220_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$false B[1]=$true B[2]=$true B[3]=$true B[4]=$false B[5]=$false B[6]=$false Y=$procmux$2221_CMP
|
||
|
|
.cname $procmux$2221_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$true B[1]=$false B[2]=$true B[3]=$true B[4]=$false B[5]=$false B[6]=$false Y=$procmux$2222_CMP
|
||
|
|
.cname $procmux$2222_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$false B[1]=$false B[2]=$true B[3]=$true B[4]=$false B[5]=$false B[6]=$false Y=$procmux$2223_CMP
|
||
|
|
.cname $procmux$2223_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$true B[1]=$true B[2]=$false B[3]=$true B[4]=$false B[5]=$false B[6]=$false Y=$procmux$2224_CMP
|
||
|
|
.cname $procmux$2224_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$false B[1]=$true B[2]=$false B[3]=$true B[4]=$false B[5]=$false B[6]=$false Y=$procmux$2225_CMP
|
||
|
|
.cname $procmux$2225_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$true B[1]=$false B[2]=$false B[3]=$true B[4]=$false B[5]=$false B[6]=$false Y=$procmux$2226_CMP
|
||
|
|
.cname $procmux$2226_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$false B[1]=$false B[2]=$false B[3]=$true B[4]=$false B[5]=$false B[6]=$false Y=$procmux$2227_CMP
|
||
|
|
.cname $procmux$2227_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$true B[1]=$true B[2]=$true B[3]=$false B[4]=$false B[5]=$false B[6]=$false Y=$procmux$2228_CMP
|
||
|
|
.cname $procmux$2228_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$false B[1]=$true B[2]=$true B[3]=$false B[4]=$false B[5]=$false B[6]=$false Y=$procmux$2229_CMP
|
||
|
|
.cname $procmux$2229_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$true B[1]=$true B[2]=$true B[3]=$true B[4]=$true B[5]=$false B[6]=$false Y=$procmux$222_CMP
|
||
|
|
.cname $procmux$222_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$true B[1]=$false B[2]=$true B[3]=$false B[4]=$false B[5]=$false B[6]=$false Y=$procmux$2230_CMP
|
||
|
|
.cname $procmux$2230_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$false B[1]=$false B[2]=$true B[3]=$false B[4]=$false B[5]=$false B[6]=$false Y=$procmux$2231_CMP
|
||
|
|
.cname $procmux$2231_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$true B[1]=$true B[2]=$false B[3]=$false B[4]=$false B[5]=$false B[6]=$false Y=$procmux$2232_CMP
|
||
|
|
.cname $procmux$2232_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$false B[1]=$true B[2]=$false B[3]=$false B[4]=$false B[5]=$false B[6]=$false Y=$procmux$2233_CMP
|
||
|
|
.cname $procmux$2233_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$true B[1]=$false B[2]=$false B[3]=$false B[4]=$false B[5]=$false B[6]=$false Y=$procmux$2234_CMP
|
||
|
|
.cname $procmux$2234_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $mux A[0]=B[0] A[1]=B[1] A[2]=B[2] A[3]=B[3] A[4]=B[4] A[5]=B[5] A[6]=B[6] A[7]=B[7] A[8]=B[8] A[9]=B[9] A[10]=B[10] A[11]=B[11] A[12]=B[12] A[13]=B[13] A[14]=B[14] A[15]=B[15] A[16]=B[16] A[17]=B[17] A[18]=B[18] A[19]=B[19] A[20]=B[20] A[21]=B[21] A[22]=B[22] A[23]=B[23] A[24]=B[24] A[25]=B[25] A[26]=B[26] A[27]=B[27] A[28]=B[28] A[29]=B[29] A[30]=B[30] A[31]=B[31] B[0]=$true B[1]=$false B[2]=$false B[3]=$true B[4]=$false B[5]=$false B[6]=$false B[7]=$true B[8]=$true B[9]=$true B[10]=$false B[11]=$true B[12]=$false B[13]=$true B[14]=$false B[15]=$true B[16]=$true B[17]=$false B[18]=$true B[19]=$true B[20]=$false B[21]=$false B[22]=$true B[23]=$true B[24]=$true B[25]=$true B[26]=$true B[27]=$true B[28]=$false B[29]=$true B[30]=$true B[31]=$true S=$procmux$2238_CMP Y[0]=$procmux$2237_Y[0] Y[1]=$procmux$2237_Y[1] Y[2]=$procmux$2237_Y[2] Y[3]=$procmux$2237_Y[3] Y[4]=$procmux$2237_Y[4] Y[5]=$procmux$2237_Y[5] Y[6]=$procmux$2237_Y[6] Y[7]=$procmux$2237_Y[7] Y[8]=$procmux$2237_Y[8] Y[9]=$procmux$2237_Y[9] Y[10]=$procmux$2237_Y[10] Y[11]=$procmux$2237_Y[11] Y[12]=$procmux$2237_Y[12] Y[13]=$procmux$2237_Y[13] Y[14]=$procmux$2237_Y[14] Y[15]=$procmux$2237_Y[15] Y[16]=$procmux$2237_Y[16] Y[17]=$procmux$2237_Y[17] Y[18]=$procmux$2237_Y[18] Y[19]=$procmux$2237_Y[19] Y[20]=$procmux$2237_Y[20] Y[21]=$procmux$2237_Y[21] Y[22]=$procmux$2237_Y[22] Y[23]=$procmux$2237_Y[23] Y[24]=$procmux$2237_Y[24] Y[25]=$procmux$2237_Y[25] Y[26]=$procmux$2237_Y[26] Y[27]=$procmux$2237_Y[27] Y[28]=$procmux$2237_Y[28] Y[29]=$procmux$2237_Y[29] Y[30]=$procmux$2237_Y[30] Y[31]=$procmux$2237_Y[31]
|
||
|
|
.cname $procmux$2237
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:198"
|
||
|
|
.param WIDTH 00000000000000000000000000100000
|
||
|
|
.subckt $eq A=cmd[2] B=$false Y=$procmux$2238_CMP
|
||
|
|
.cname $procmux$2238_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:198"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000001
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000001
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $mux A[0]=B[0] A[1]=B[1] A[2]=B[2] A[3]=B[3] A[4]=B[4] A[5]=B[5] A[6]=B[6] A[7]=B[7] A[8]=B[8] A[9]=B[9] A[10]=B[10] A[11]=B[11] A[12]=B[12] A[13]=B[13] A[14]=B[14] A[15]=B[15] A[16]=B[16] A[17]=B[17] A[18]=B[18] A[19]=B[19] A[20]=B[20] A[21]=B[21] A[22]=B[22] A[23]=B[23] A[24]=B[24] A[25]=B[25] A[26]=B[26] A[27]=B[27] A[28]=B[28] A[29]=B[29] A[30]=B[30] A[31]=B[31] B[0]=$procmux$2237_Y[0] B[1]=$procmux$2237_Y[1] B[2]=$procmux$2237_Y[2] B[3]=$procmux$2237_Y[3] B[4]=$procmux$2237_Y[4] B[5]=$procmux$2237_Y[5] B[6]=$procmux$2237_Y[6] B[7]=$procmux$2237_Y[7] B[8]=$procmux$2237_Y[8] B[9]=$procmux$2237_Y[9] B[10]=$procmux$2237_Y[10] B[11]=$procmux$2237_Y[11] B[12]=$procmux$2237_Y[12] B[13]=$procmux$2237_Y[13] B[14]=$procmux$2237_Y[14] B[15]=$procmux$2237_Y[15] B[16]=$procmux$2237_Y[16] B[17]=$procmux$2237_Y[17] B[18]=$procmux$2237_Y[18] B[19]=$procmux$2237_Y[19] B[20]=$procmux$2237_Y[20] B[21]=$procmux$2237_Y[21] B[22]=$procmux$2237_Y[22] B[23]=$procmux$2237_Y[23] B[24]=$procmux$2237_Y[24] B[25]=$procmux$2237_Y[25] B[26]=$procmux$2237_Y[26] B[27]=$procmux$2237_Y[27] B[28]=$procmux$2237_Y[28] B[29]=$procmux$2237_Y[29] B[30]=$procmux$2237_Y[30] B[31]=$procmux$2237_Y[31] S=$procmux$2240_CMP Y[0]=$procmux$2239_Y[0] Y[1]=$procmux$2239_Y[1] Y[2]=$procmux$2239_Y[2] Y[3]=$procmux$2239_Y[3] Y[4]=$procmux$2239_Y[4] Y[5]=$procmux$2239_Y[5] Y[6]=$procmux$2239_Y[6] Y[7]=$procmux$2239_Y[7] Y[8]=$procmux$2239_Y[8] Y[9]=$procmux$2239_Y[9] Y[10]=$procmux$2239_Y[10] Y[11]=$procmux$2239_Y[11] Y[12]=$procmux$2239_Y[12] Y[13]=$procmux$2239_Y[13] Y[14]=$procmux$2239_Y[14] Y[15]=$procmux$2239_Y[15] Y[16]=$procmux$2239_Y[16] Y[17]=$procmux$2239_Y[17] Y[18]=$procmux$2239_Y[18] Y[19]=$procmux$2239_Y[19] Y[20]=$procmux$2239_Y[20] Y[21]=$procmux$2239_Y[21] Y[22]=$procmux$2239_Y[22] Y[23]=$procmux$2239_Y[23] Y[24]=$procmux$2239_Y[24] Y[25]=$procmux$2239_Y[25] Y[26]=$procmux$2239_Y[26] Y[27]=$procmux$2239_Y[27] Y[28]=$procmux$2239_Y[28] Y[29]=$procmux$2239_Y[29] Y[30]=$procmux$2239_Y[30] Y[31]=$procmux$2239_Y[31]
|
||
|
|
.cname $procmux$2239
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:191"
|
||
|
|
.param WIDTH 00000000000000000000000000100000
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$false B[1]=$true B[2]=$true B[3]=$true B[4]=$true B[5]=$false B[6]=$false Y=$procmux$223_CMP
|
||
|
|
.cname $procmux$223_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$false B[1]=$false B[2]=$false B[3]=$false B[4]=$false B[5]=$false B[6]=$false Y=$procmux$2241_CMP
|
||
|
|
.cname $procmux$2241_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $mux A[0]=$procmux$2154_Y[0] A[1]=$procmux$2154_Y[1] A[2]=$procmux$2154_Y[2] A[3]=$procmux$2154_Y[3] A[4]=$procmux$2154_Y[4] A[5]=$procmux$2154_Y[5] A[6]=$procmux$2154_Y[6] A[7]=$procmux$2154_Y[7] A[8]=$procmux$2154_Y[8] A[9]=$procmux$2154_Y[9] A[10]=$procmux$2154_Y[10] A[11]=$procmux$2154_Y[11] A[12]=$procmux$2154_Y[12] A[13]=$procmux$2154_Y[13] A[14]=$procmux$2154_Y[14] A[15]=$procmux$2154_Y[15] A[16]=$procmux$2154_Y[16] A[17]=$procmux$2154_Y[17] A[18]=$procmux$2154_Y[18] A[19]=$procmux$2154_Y[19] A[20]=$procmux$2154_Y[20] A[21]=$procmux$2154_Y[21] A[22]=$procmux$2154_Y[22] A[23]=$procmux$2154_Y[23] A[24]=$procmux$2154_Y[24] A[25]=$procmux$2154_Y[25] A[26]=$procmux$2154_Y[26] A[27]=$procmux$2154_Y[27] A[28]=$procmux$2154_Y[28] A[29]=$procmux$2154_Y[29] A[30]=$procmux$2154_Y[30] A[31]=$procmux$2154_Y[31] B[0]=$false B[1]=$false B[2]=$false B[3]=$false B[4]=$false B[5]=$false B[6]=$false B[7]=$false B[8]=$false B[9]=$false B[10]=$false B[11]=$false B[12]=$false B[13]=$false B[14]=$false B[15]=$false B[16]=$false B[17]=$false B[18]=$false B[19]=$false B[20]=$false B[21]=$false B[22]=$false B[23]=$false B[24]=$false B[25]=$false B[26]=$false B[27]=$false B[28]=$false B[29]=$false B[30]=$false B[31]=$false S=$procmux$2244_CMP Y[0]=$procmux$2243_Y[0] Y[1]=$procmux$2243_Y[1] Y[2]=$procmux$2243_Y[2] Y[3]=$procmux$2243_Y[3] Y[4]=$procmux$2243_Y[4] Y[5]=$procmux$2243_Y[5] Y[6]=$procmux$2243_Y[6] Y[7]=$procmux$2243_Y[7] Y[8]=$procmux$2243_Y[8] Y[9]=$procmux$2243_Y[9] Y[10]=$procmux$2243_Y[10] Y[11]=$procmux$2243_Y[11] Y[12]=$procmux$2243_Y[12] Y[13]=$procmux$2243_Y[13] Y[14]=$procmux$2243_Y[14] Y[15]=$procmux$2243_Y[15] Y[16]=$procmux$2243_Y[16] Y[17]=$procmux$2243_Y[17] Y[18]=$procmux$2243_Y[18] Y[19]=$procmux$2243_Y[19] Y[20]=$procmux$2243_Y[20] Y[21]=$procmux$2243_Y[21] Y[22]=$procmux$2243_Y[22] Y[23]=$procmux$2243_Y[23] Y[24]=$procmux$2243_Y[24] Y[25]=$procmux$2243_Y[25] Y[26]=$procmux$2243_Y[26] Y[27]=$procmux$2243_Y[27] Y[28]=$procmux$2243_Y[28] Y[29]=$procmux$2243_Y[29] Y[30]=$procmux$2243_Y[30] Y[31]=$procmux$2243_Y[31]
|
||
|
|
.cname $procmux$2243
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:150"
|
||
|
|
.param WIDTH 00000000000000000000000000100000
|
||
|
|
.subckt $pmux A[0]=A[0] A[1]=A[1] A[2]=A[2] A[3]=A[3] A[4]=A[4] A[5]=A[5] A[6]=A[6] A[7]=A[7] A[8]=A[8] A[9]=A[9] A[10]=A[10] A[11]=A[11] A[12]=A[12] A[13]=A[13] A[14]=A[14] A[15]=A[15] A[16]=A[16] A[17]=A[17] A[18]=A[18] A[19]=A[19] A[20]=A[20] A[21]=A[21] A[22]=A[22] A[23]=A[23] A[24]=A[24] A[25]=A[25] A[26]=A[26] A[27]=A[27] A[28]=A[28] A[29]=A[29] A[30]=A[30] A[31]=A[31] B[0]=$add$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:2089$29_Y[0] B[1]=$add$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:2089$29_Y[1] B[2]=$add$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:2089$29_Y[2] B[3]=$add$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:2089$29_Y[3] B[4]=$add$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:2089$29_Y[4] B[5]=$add$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:2089$29_Y[5] B[6]=$add$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:2089$29_Y[6] B[7]=$add$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:2089$29_Y[7] B[8]=$add$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:2089$29_Y[8] B[9]=$add$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:2089$29_Y[9] B[10]=$add$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:2089$29_Y[10] B[11]=$add$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:2089$29_Y[11] B[12]=$add$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:2089$29_Y[12] B[13]=$add$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:2089$29_Y[13] B[14]=$add$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:2089$29_Y[14] B[15]=$add$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:2089$29_Y[15] B[16]=$add$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:2089$29_Y[16] B[17]=$add$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:2089$29_Y[17] B[18]=$add$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:2089$29_Y[18] B[19]=$add$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:2089$29_Y[19] B[20]=$add$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:2089$29_Y[20] B[21]=$add$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:2089$29_Y[21] B[22]=$add$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:2089$29_Y[22] B[23]=$add$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:2089$29_Y[23] B[24]=$add$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:2089$29_Y[24] B[25]=$add$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:2089$29_Y[25] B[26]=$add$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:2089$29_Y[26] B[27]=$add$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:2089$29_Y[27] B[28]=$add$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:2089$29_Y[28] B[29]=$add$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:2089$29_Y[29] B[30]=$add$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:2089$29_Y[30] B[31]=$add$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:2089$29_Y[31] B[32]=next_A[0] B[33]=next_A[1] B[34]=next_A[2] B[35]=next_A[3] B[36]=next_A[4] B[37]=next_A[5] B[38]=next_A[6] B[39]=next_A[7] B[40]=next_A[8] B[41]=next_A[9] B[42]=next_A[10] B[43]=next_A[11] B[44]=next_A[12] B[45]=next_A[13] B[46]=next_A[14] B[47]=next_A[15] B[48]=next_A[16] B[49]=next_A[17] B[50]=next_A[18] B[51]=next_A[19] B[52]=next_A[20] B[53]=next_A[21] B[54]=next_A[22] B[55]=next_A[23] B[56]=next_A[24] B[57]=next_A[25] B[58]=next_A[26] B[59]=next_A[27] B[60]=next_A[28] B[61]=next_A[29] B[62]=next_A[30] B[63]=next_A[31] B[64]=next_A[0] B[65]=next_A[1] B[66]=next_A[2] B[67]=next_A[3] B[68]=next_A[4] B[69]=next_A[5] B[70]=next_A[6] B[71]=next_A[7] B[72]=next_A[8] B[73]=next_A[9] B[74]=next_A[10] B[75]=next_A[11] B[76]=next_A[12] B[77]=next_A[13] B[78]=next_A[14] B[79]=next_A[15] B[80]=next_A[16] B[81]=next_A[17] B[82]=next_A[18] B[83]=next_A[19] B[84]=next_A[20] B[85]=next_A[21] B[86]=next_A[22] B[87]=next_A[23] B[88]=next_A[24] B[89]=next_A[25] B[90]=next_A[26] B[91]=next_A[27] B[92]=next_A[28] B[93]=next_A[29] B[94]=next_A[30] B[95]=next_A[31] B[96]=next_A[0] B[97]=next_A[1] B[98]=next_A[2] B[99]=next_A[3] B[100]=next_A[4] B[101]=next_A[5] B[102]=next_A[6] B[103]=next_A[7] B[104]=next_A[8] B[105]=next_A[9] B[106]=
|
||
|
|
.cname $procmux$2246
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param S_WIDTH 00000000000000000000000001010001
|
||
|
|
.param WIDTH 00000000000000000000000000100000
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$false B[1]=$false B[2]=$false B[3]=$false B[4]=$true B[5]=$false B[6]=$true Y=$procmux$2247_CMP
|
||
|
|
.cname $procmux$2247_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$true B[1]=$true B[2]=$true B[3]=$true B[4]=$false B[5]=$false B[6]=$true Y=$procmux$2248_CMP
|
||
|
|
.cname $procmux$2248_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$false B[1]=$true B[2]=$true B[3]=$true B[4]=$false B[5]=$false B[6]=$true Y=$procmux$2249_CMP
|
||
|
|
.cname $procmux$2249_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$true B[1]=$false B[2]=$true B[3]=$true B[4]=$true B[5]=$false B[6]=$false Y=$procmux$224_CMP
|
||
|
|
.cname $procmux$224_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$true B[1]=$false B[2]=$true B[3]=$true B[4]=$false B[5]=$false B[6]=$true Y=$procmux$2250_CMP
|
||
|
|
.cname $procmux$2250_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$false B[1]=$false B[2]=$true B[3]=$true B[4]=$false B[5]=$false B[6]=$true Y=$procmux$2251_CMP
|
||
|
|
.cname $procmux$2251_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$true B[1]=$true B[2]=$false B[3]=$true B[4]=$false B[5]=$false B[6]=$true Y=$procmux$2252_CMP
|
||
|
|
.cname $procmux$2252_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$false B[1]=$true B[2]=$false B[3]=$true B[4]=$false B[5]=$false B[6]=$true Y=$procmux$2253_CMP
|
||
|
|
.cname $procmux$2253_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$true B[1]=$false B[2]=$false B[3]=$true B[4]=$false B[5]=$false B[6]=$true Y=$procmux$2254_CMP
|
||
|
|
.cname $procmux$2254_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$false B[1]=$false B[2]=$false B[3]=$true B[4]=$false B[5]=$false B[6]=$true Y=$procmux$2255_CMP
|
||
|
|
.cname $procmux$2255_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$true B[1]=$true B[2]=$true B[3]=$false B[4]=$false B[5]=$false B[6]=$true Y=$procmux$2256_CMP
|
||
|
|
.cname $procmux$2256_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$false B[1]=$true B[2]=$true B[3]=$false B[4]=$false B[5]=$false B[6]=$true Y=$procmux$2257_CMP
|
||
|
|
.cname $procmux$2257_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$true B[1]=$false B[2]=$true B[3]=$false B[4]=$false B[5]=$false B[6]=$true Y=$procmux$2258_CMP
|
||
|
|
.cname $procmux$2258_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$false B[1]=$false B[2]=$true B[3]=$false B[4]=$false B[5]=$false B[6]=$true Y=$procmux$2259_CMP
|
||
|
|
.cname $procmux$2259_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$false B[1]=$false B[2]=$true B[3]=$true B[4]=$true B[5]=$false B[6]=$false Y=$procmux$225_CMP
|
||
|
|
.cname $procmux$225_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$true B[1]=$true B[2]=$false B[3]=$false B[4]=$false B[5]=$false B[6]=$true Y=$procmux$2260_CMP
|
||
|
|
.cname $procmux$2260_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$false B[1]=$true B[2]=$false B[3]=$false B[4]=$false B[5]=$false B[6]=$true Y=$procmux$2261_CMP
|
||
|
|
.cname $procmux$2261_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$true B[1]=$false B[2]=$false B[3]=$false B[4]=$false B[5]=$false B[6]=$true Y=$procmux$2262_CMP
|
||
|
|
.cname $procmux$2262_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$false B[1]=$false B[2]=$false B[3]=$false B[4]=$false B[5]=$false B[6]=$true Y=$procmux$2263_CMP
|
||
|
|
.cname $procmux$2263_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$true B[1]=$true B[2]=$true B[3]=$true B[4]=$true B[5]=$true B[6]=$false Y=$procmux$2264_CMP
|
||
|
|
.cname $procmux$2264_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$false B[1]=$true B[2]=$true B[3]=$true B[4]=$true B[5]=$true B[6]=$false Y=$procmux$2265_CMP
|
||
|
|
.cname $procmux$2265_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$true B[1]=$false B[2]=$true B[3]=$true B[4]=$true B[5]=$true B[6]=$false Y=$procmux$2266_CMP
|
||
|
|
.cname $procmux$2266_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$false B[1]=$false B[2]=$true B[3]=$true B[4]=$true B[5]=$true B[6]=$false Y=$procmux$2267_CMP
|
||
|
|
.cname $procmux$2267_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$true B[1]=$true B[2]=$false B[3]=$true B[4]=$true B[5]=$true B[6]=$false Y=$procmux$2268_CMP
|
||
|
|
.cname $procmux$2268_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$false B[1]=$true B[2]=$false B[3]=$true B[4]=$true B[5]=$true B[6]=$false Y=$procmux$2269_CMP
|
||
|
|
.cname $procmux$2269_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$true B[1]=$true B[2]=$false B[3]=$true B[4]=$true B[5]=$false B[6]=$false Y=$procmux$226_CMP
|
||
|
|
.cname $procmux$226_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$true B[1]=$false B[2]=$false B[3]=$true B[4]=$true B[5]=$true B[6]=$false Y=$procmux$2270_CMP
|
||
|
|
.cname $procmux$2270_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$false B[1]=$false B[2]=$false B[3]=$true B[4]=$true B[5]=$true B[6]=$false Y=$procmux$2271_CMP
|
||
|
|
.cname $procmux$2271_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$true B[1]=$true B[2]=$true B[3]=$false B[4]=$true B[5]=$true B[6]=$false Y=$procmux$2272_CMP
|
||
|
|
.cname $procmux$2272_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$false B[1]=$true B[2]=$true B[3]=$false B[4]=$true B[5]=$true B[6]=$false Y=$procmux$2273_CMP
|
||
|
|
.cname $procmux$2273_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$true B[1]=$false B[2]=$true B[3]=$false B[4]=$true B[5]=$true B[6]=$false Y=$procmux$2274_CMP
|
||
|
|
.cname $procmux$2274_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$false B[1]=$false B[2]=$true B[3]=$false B[4]=$true B[5]=$true B[6]=$false Y=$procmux$2275_CMP
|
||
|
|
.cname $procmux$2275_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$true B[1]=$true B[2]=$false B[3]=$false B[4]=$true B[5]=$true B[6]=$false Y=$procmux$2276_CMP
|
||
|
|
.cname $procmux$2276_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$false B[1]=$true B[2]=$false B[3]=$false B[4]=$true B[5]=$true B[6]=$false Y=$procmux$2277_CMP
|
||
|
|
.cname $procmux$2277_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$true B[1]=$false B[2]=$false B[3]=$false B[4]=$true B[5]=$true B[6]=$false Y=$procmux$2278_CMP
|
||
|
|
.cname $procmux$2278_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$false B[1]=$false B[2]=$false B[3]=$false B[4]=$true B[5]=$true B[6]=$false Y=$procmux$2279_CMP
|
||
|
|
.cname $procmux$2279_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$false B[1]=$true B[2]=$false B[3]=$true B[4]=$true B[5]=$false B[6]=$false Y=$procmux$227_CMP
|
||
|
|
.cname $procmux$227_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$true B[1]=$true B[2]=$true B[3]=$true B[4]=$false B[5]=$true B[6]=$false Y=$procmux$2280_CMP
|
||
|
|
.cname $procmux$2280_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$false B[1]=$true B[2]=$true B[3]=$true B[4]=$false B[5]=$true B[6]=$false Y=$procmux$2281_CMP
|
||
|
|
.cname $procmux$2281_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$true B[1]=$false B[2]=$true B[3]=$true B[4]=$false B[5]=$true B[6]=$false Y=$procmux$2282_CMP
|
||
|
|
.cname $procmux$2282_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$false B[1]=$false B[2]=$true B[3]=$true B[4]=$false B[5]=$true B[6]=$false Y=$procmux$2283_CMP
|
||
|
|
.cname $procmux$2283_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$true B[1]=$true B[2]=$false B[3]=$true B[4]=$false B[5]=$true B[6]=$false Y=$procmux$2284_CMP
|
||
|
|
.cname $procmux$2284_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$false B[1]=$true B[2]=$false B[3]=$true B[4]=$false B[5]=$true B[6]=$false Y=$procmux$2285_CMP
|
||
|
|
.cname $procmux$2285_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$true B[1]=$false B[2]=$false B[3]=$true B[4]=$false B[5]=$true B[6]=$false Y=$procmux$2286_CMP
|
||
|
|
.cname $procmux$2286_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$false B[1]=$false B[2]=$false B[3]=$true B[4]=$false B[5]=$true B[6]=$false Y=$procmux$2287_CMP
|
||
|
|
.cname $procmux$2287_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$true B[1]=$true B[2]=$true B[3]=$false B[4]=$false B[5]=$true B[6]=$false Y=$procmux$2288_CMP
|
||
|
|
.cname $procmux$2288_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$false B[1]=$true B[2]=$true B[3]=$false B[4]=$false B[5]=$true B[6]=$false Y=$procmux$2289_CMP
|
||
|
|
.cname $procmux$2289_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$true B[1]=$false B[2]=$false B[3]=$true B[4]=$true B[5]=$false B[6]=$false Y=$procmux$228_CMP
|
||
|
|
.cname $procmux$228_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$true B[1]=$false B[2]=$true B[3]=$false B[4]=$false B[5]=$true B[6]=$false Y=$procmux$2290_CMP
|
||
|
|
.cname $procmux$2290_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$false B[1]=$false B[2]=$true B[3]=$false B[4]=$false B[5]=$true B[6]=$false Y=$procmux$2291_CMP
|
||
|
|
.cname $procmux$2291_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$true B[1]=$true B[2]=$false B[3]=$false B[4]=$false B[5]=$true B[6]=$false Y=$procmux$2292_CMP
|
||
|
|
.cname $procmux$2292_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$false B[1]=$true B[2]=$false B[3]=$false B[4]=$false B[5]=$true B[6]=$false Y=$procmux$2293_CMP
|
||
|
|
.cname $procmux$2293_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$true B[1]=$false B[2]=$false B[3]=$false B[4]=$false B[5]=$true B[6]=$false Y=$procmux$2294_CMP
|
||
|
|
.cname $procmux$2294_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$false B[1]=$false B[2]=$false B[3]=$false B[4]=$false B[5]=$true B[6]=$false Y=$procmux$2295_CMP
|
||
|
|
.cname $procmux$2295_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$true B[1]=$true B[2]=$true B[3]=$true B[4]=$true B[5]=$false B[6]=$false Y=$procmux$2296_CMP
|
||
|
|
.cname $procmux$2296_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$false B[1]=$true B[2]=$true B[3]=$true B[4]=$true B[5]=$false B[6]=$false Y=$procmux$2297_CMP
|
||
|
|
.cname $procmux$2297_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$true B[1]=$false B[2]=$true B[3]=$true B[4]=$true B[5]=$false B[6]=$false Y=$procmux$2298_CMP
|
||
|
|
.cname $procmux$2298_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$false B[1]=$false B[2]=$true B[3]=$true B[4]=$true B[5]=$false B[6]=$false Y=$procmux$2299_CMP
|
||
|
|
.cname $procmux$2299_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$false B[1]=$false B[2]=$false B[3]=$true B[4]=$true B[5]=$false B[6]=$false Y=$procmux$229_CMP
|
||
|
|
.cname $procmux$229_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$true B[1]=$true B[2]=$false B[3]=$true B[4]=$true B[5]=$false B[6]=$false Y=$procmux$2300_CMP
|
||
|
|
.cname $procmux$2300_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$false B[1]=$true B[2]=$false B[3]=$true B[4]=$true B[5]=$false B[6]=$false Y=$procmux$2301_CMP
|
||
|
|
.cname $procmux$2301_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$true B[1]=$false B[2]=$false B[3]=$true B[4]=$true B[5]=$false B[6]=$false Y=$procmux$2302_CMP
|
||
|
|
.cname $procmux$2302_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$false B[1]=$false B[2]=$false B[3]=$true B[4]=$true B[5]=$false B[6]=$false Y=$procmux$2303_CMP
|
||
|
|
.cname $procmux$2303_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$true B[1]=$true B[2]=$true B[3]=$false B[4]=$true B[5]=$false B[6]=$false Y=$procmux$2304_CMP
|
||
|
|
.cname $procmux$2304_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$false B[1]=$true B[2]=$true B[3]=$false B[4]=$true B[5]=$false B[6]=$false Y=$procmux$2305_CMP
|
||
|
|
.cname $procmux$2305_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$true B[1]=$false B[2]=$true B[3]=$false B[4]=$true B[5]=$false B[6]=$false Y=$procmux$2306_CMP
|
||
|
|
.cname $procmux$2306_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$false B[1]=$false B[2]=$true B[3]=$false B[4]=$true B[5]=$false B[6]=$false Y=$procmux$2307_CMP
|
||
|
|
.cname $procmux$2307_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$true B[1]=$true B[2]=$false B[3]=$false B[4]=$true B[5]=$false B[6]=$false Y=$procmux$2308_CMP
|
||
|
|
.cname $procmux$2308_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$false B[1]=$true B[2]=$false B[3]=$false B[4]=$true B[5]=$false B[6]=$false Y=$procmux$2309_CMP
|
||
|
|
.cname $procmux$2309_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$true B[1]=$true B[2]=$true B[3]=$false B[4]=$true B[5]=$false B[6]=$false Y=$procmux$230_CMP
|
||
|
|
.cname $procmux$230_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$true B[1]=$false B[2]=$false B[3]=$false B[4]=$true B[5]=$false B[6]=$false Y=$procmux$2310_CMP
|
||
|
|
.cname $procmux$2310_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$false B[1]=$false B[2]=$false B[3]=$false B[4]=$true B[5]=$false B[6]=$false Y=$procmux$2311_CMP
|
||
|
|
.cname $procmux$2311_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$true B[1]=$true B[2]=$true B[3]=$true B[4]=$false B[5]=$false B[6]=$false Y=$procmux$2312_CMP
|
||
|
|
.cname $procmux$2312_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$false B[1]=$true B[2]=$true B[3]=$true B[4]=$false B[5]=$false B[6]=$false Y=$procmux$2313_CMP
|
||
|
|
.cname $procmux$2313_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$true B[1]=$false B[2]=$true B[3]=$true B[4]=$false B[5]=$false B[6]=$false Y=$procmux$2314_CMP
|
||
|
|
.cname $procmux$2314_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$false B[1]=$false B[2]=$true B[3]=$true B[4]=$false B[5]=$false B[6]=$false Y=$procmux$2315_CMP
|
||
|
|
.cname $procmux$2315_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$true B[1]=$true B[2]=$false B[3]=$true B[4]=$false B[5]=$false B[6]=$false Y=$procmux$2316_CMP
|
||
|
|
.cname $procmux$2316_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$false B[1]=$true B[2]=$false B[3]=$true B[4]=$false B[5]=$false B[6]=$false Y=$procmux$2317_CMP
|
||
|
|
.cname $procmux$2317_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$true B[1]=$false B[2]=$false B[3]=$true B[4]=$false B[5]=$false B[6]=$false Y=$procmux$2318_CMP
|
||
|
|
.cname $procmux$2318_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$false B[1]=$false B[2]=$false B[3]=$true B[4]=$false B[5]=$false B[6]=$false Y=$procmux$2319_CMP
|
||
|
|
.cname $procmux$2319_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$false B[1]=$true B[2]=$true B[3]=$false B[4]=$true B[5]=$false B[6]=$false Y=$procmux$231_CMP
|
||
|
|
.cname $procmux$231_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$true B[1]=$true B[2]=$true B[3]=$false B[4]=$false B[5]=$false B[6]=$false Y=$procmux$2320_CMP
|
||
|
|
.cname $procmux$2320_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$false B[1]=$true B[2]=$true B[3]=$false B[4]=$false B[5]=$false B[6]=$false Y=$procmux$2321_CMP
|
||
|
|
.cname $procmux$2321_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$true B[1]=$false B[2]=$true B[3]=$false B[4]=$false B[5]=$false B[6]=$false Y=$procmux$2322_CMP
|
||
|
|
.cname $procmux$2322_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$false B[1]=$false B[2]=$true B[3]=$false B[4]=$false B[5]=$false B[6]=$false Y=$procmux$2323_CMP
|
||
|
|
.cname $procmux$2323_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$true B[1]=$true B[2]=$false B[3]=$false B[4]=$false B[5]=$false B[6]=$false Y=$procmux$2324_CMP
|
||
|
|
.cname $procmux$2324_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$false B[1]=$true B[2]=$false B[3]=$false B[4]=$false B[5]=$false B[6]=$false Y=$procmux$2325_CMP
|
||
|
|
.cname $procmux$2325_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$true B[1]=$false B[2]=$false B[3]=$false B[4]=$false B[5]=$false B[6]=$false Y=$procmux$2326_CMP
|
||
|
|
.cname $procmux$2326_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $mux A[0]=A[0] A[1]=A[1] A[2]=A[2] A[3]=A[3] A[4]=A[4] A[5]=A[5] A[6]=A[6] A[7]=A[7] A[8]=A[8] A[9]=A[9] A[10]=A[10] A[11]=A[11] A[12]=A[12] A[13]=A[13] A[14]=A[14] A[15]=A[15] A[16]=A[16] A[17]=A[17] A[18]=A[18] A[19]=A[19] A[20]=A[20] A[21]=A[21] A[22]=A[22] A[23]=A[23] A[24]=A[24] A[25]=A[25] A[26]=A[26] A[27]=A[27] A[28]=A[28] A[29]=A[29] A[30]=A[30] A[31]=A[31] B[0]=$true B[1]=$false B[2]=$false B[3]=$false B[4]=$false B[5]=$false B[6]=$false B[7]=$false B[8]=$true B[9]=$true B[10]=$false B[11]=$false B[12]=$false B[13]=$true B[14]=$false B[15]=$false B[16]=$true B[17]=$false B[18]=$true B[19]=$false B[20]=$false B[21]=$false B[22]=$true B[23]=$false B[24]=$true B[25]=$true B[26]=$true B[27]=$false B[28]=$false B[29]=$true B[30]=$true B[31]=$false S=$procmux$2330_CMP Y[0]=$procmux$2329_Y[0] Y[1]=$procmux$2329_Y[1] Y[2]=$procmux$2329_Y[2] Y[3]=$procmux$2329_Y[3] Y[4]=$procmux$2329_Y[4] Y[5]=$procmux$2329_Y[5] Y[6]=$procmux$2329_Y[6] Y[7]=$procmux$2329_Y[7] Y[8]=$procmux$2329_Y[8] Y[9]=$procmux$2329_Y[9] Y[10]=$procmux$2329_Y[10] Y[11]=$procmux$2329_Y[11] Y[12]=$procmux$2329_Y[12] Y[13]=$procmux$2329_Y[13] Y[14]=$procmux$2329_Y[14] Y[15]=$procmux$2329_Y[15] Y[16]=$procmux$2329_Y[16] Y[17]=$procmux$2329_Y[17] Y[18]=$procmux$2329_Y[18] Y[19]=$procmux$2329_Y[19] Y[20]=$procmux$2329_Y[20] Y[21]=$procmux$2329_Y[21] Y[22]=$procmux$2329_Y[22] Y[23]=$procmux$2329_Y[23] Y[24]=$procmux$2329_Y[24] Y[25]=$procmux$2329_Y[25] Y[26]=$procmux$2329_Y[26] Y[27]=$procmux$2329_Y[27] Y[28]=$procmux$2329_Y[28] Y[29]=$procmux$2329_Y[29] Y[30]=$procmux$2329_Y[30] Y[31]=$procmux$2329_Y[31]
|
||
|
|
.cname $procmux$2329
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:198"
|
||
|
|
.param WIDTH 00000000000000000000000000100000
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$true B[1]=$false B[2]=$true B[3]=$false B[4]=$true B[5]=$false B[6]=$false Y=$procmux$232_CMP
|
||
|
|
.cname $procmux$232_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A=cmd[2] B=$false Y=$procmux$2330_CMP
|
||
|
|
.cname $procmux$2330_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:198"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000001
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000001
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $mux A[0]=A[0] A[1]=A[1] A[2]=A[2] A[3]=A[3] A[4]=A[4] A[5]=A[5] A[6]=A[6] A[7]=A[7] A[8]=A[8] A[9]=A[9] A[10]=A[10] A[11]=A[11] A[12]=A[12] A[13]=A[13] A[14]=A[14] A[15]=A[15] A[16]=A[16] A[17]=A[17] A[18]=A[18] A[19]=A[19] A[20]=A[20] A[21]=A[21] A[22]=A[22] A[23]=A[23] A[24]=A[24] A[25]=A[25] A[26]=A[26] A[27]=A[27] A[28]=A[28] A[29]=A[29] A[30]=A[30] A[31]=A[31] B[0]=$procmux$2329_Y[0] B[1]=$procmux$2329_Y[1] B[2]=$procmux$2329_Y[2] B[3]=$procmux$2329_Y[3] B[4]=$procmux$2329_Y[4] B[5]=$procmux$2329_Y[5] B[6]=$procmux$2329_Y[6] B[7]=$procmux$2329_Y[7] B[8]=$procmux$2329_Y[8] B[9]=$procmux$2329_Y[9] B[10]=$procmux$2329_Y[10] B[11]=$procmux$2329_Y[11] B[12]=$procmux$2329_Y[12] B[13]=$procmux$2329_Y[13] B[14]=$procmux$2329_Y[14] B[15]=$procmux$2329_Y[15] B[16]=$procmux$2329_Y[16] B[17]=$procmux$2329_Y[17] B[18]=$procmux$2329_Y[18] B[19]=$procmux$2329_Y[19] B[20]=$procmux$2329_Y[20] B[21]=$procmux$2329_Y[21] B[22]=$procmux$2329_Y[22] B[23]=$procmux$2329_Y[23] B[24]=$procmux$2329_Y[24] B[25]=$procmux$2329_Y[25] B[26]=$procmux$2329_Y[26] B[27]=$procmux$2329_Y[27] B[28]=$procmux$2329_Y[28] B[29]=$procmux$2329_Y[29] B[30]=$procmux$2329_Y[30] B[31]=$procmux$2329_Y[31] S=$procmux$2332_CMP Y[0]=$procmux$2331_Y[0] Y[1]=$procmux$2331_Y[1] Y[2]=$procmux$2331_Y[2] Y[3]=$procmux$2331_Y[3] Y[4]=$procmux$2331_Y[4] Y[5]=$procmux$2331_Y[5] Y[6]=$procmux$2331_Y[6] Y[7]=$procmux$2331_Y[7] Y[8]=$procmux$2331_Y[8] Y[9]=$procmux$2331_Y[9] Y[10]=$procmux$2331_Y[10] Y[11]=$procmux$2331_Y[11] Y[12]=$procmux$2331_Y[12] Y[13]=$procmux$2331_Y[13] Y[14]=$procmux$2331_Y[14] Y[15]=$procmux$2331_Y[15] Y[16]=$procmux$2331_Y[16] Y[17]=$procmux$2331_Y[17] Y[18]=$procmux$2331_Y[18] Y[19]=$procmux$2331_Y[19] Y[20]=$procmux$2331_Y[20] Y[21]=$procmux$2331_Y[21] Y[22]=$procmux$2331_Y[22] Y[23]=$procmux$2331_Y[23] Y[24]=$procmux$2331_Y[24] Y[25]=$procmux$2331_Y[25] Y[26]=$procmux$2331_Y[26] Y[27]=$procmux$2331_Y[27] Y[28]=$procmux$2331_Y[28] Y[29]=$procmux$2331_Y[29] Y[30]=$procmux$2331_Y[30] Y[31]=$procmux$2331_Y[31]
|
||
|
|
.cname $procmux$2331
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:191"
|
||
|
|
.param WIDTH 00000000000000000000000000100000
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$false B[1]=$false B[2]=$false B[3]=$false B[4]=$false B[5]=$false B[6]=$false Y=$procmux$2333_CMP
|
||
|
|
.cname $procmux$2333_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $mux A[0]=$procmux$2246_Y[0] A[1]=$procmux$2246_Y[1] A[2]=$procmux$2246_Y[2] A[3]=$procmux$2246_Y[3] A[4]=$procmux$2246_Y[4] A[5]=$procmux$2246_Y[5] A[6]=$procmux$2246_Y[6] A[7]=$procmux$2246_Y[7] A[8]=$procmux$2246_Y[8] A[9]=$procmux$2246_Y[9] A[10]=$procmux$2246_Y[10] A[11]=$procmux$2246_Y[11] A[12]=$procmux$2246_Y[12] A[13]=$procmux$2246_Y[13] A[14]=$procmux$2246_Y[14] A[15]=$procmux$2246_Y[15] A[16]=$procmux$2246_Y[16] A[17]=$procmux$2246_Y[17] A[18]=$procmux$2246_Y[18] A[19]=$procmux$2246_Y[19] A[20]=$procmux$2246_Y[20] A[21]=$procmux$2246_Y[21] A[22]=$procmux$2246_Y[22] A[23]=$procmux$2246_Y[23] A[24]=$procmux$2246_Y[24] A[25]=$procmux$2246_Y[25] A[26]=$procmux$2246_Y[26] A[27]=$procmux$2246_Y[27] A[28]=$procmux$2246_Y[28] A[29]=$procmux$2246_Y[29] A[30]=$procmux$2246_Y[30] A[31]=$procmux$2246_Y[31] B[0]=$false B[1]=$false B[2]=$false B[3]=$false B[4]=$false B[5]=$false B[6]=$false B[7]=$false B[8]=$false B[9]=$false B[10]=$false B[11]=$false B[12]=$false B[13]=$false B[14]=$false B[15]=$false B[16]=$false B[17]=$false B[18]=$false B[19]=$false B[20]=$false B[21]=$false B[22]=$false B[23]=$false B[24]=$false B[25]=$false B[26]=$false B[27]=$false B[28]=$false B[29]=$false B[30]=$false B[31]=$false S=$procmux$2336_CMP Y[0]=$procmux$2335_Y[0] Y[1]=$procmux$2335_Y[1] Y[2]=$procmux$2335_Y[2] Y[3]=$procmux$2335_Y[3] Y[4]=$procmux$2335_Y[4] Y[5]=$procmux$2335_Y[5] Y[6]=$procmux$2335_Y[6] Y[7]=$procmux$2335_Y[7] Y[8]=$procmux$2335_Y[8] Y[9]=$procmux$2335_Y[9] Y[10]=$procmux$2335_Y[10] Y[11]=$procmux$2335_Y[11] Y[12]=$procmux$2335_Y[12] Y[13]=$procmux$2335_Y[13] Y[14]=$procmux$2335_Y[14] Y[15]=$procmux$2335_Y[15] Y[16]=$procmux$2335_Y[16] Y[17]=$procmux$2335_Y[17] Y[18]=$procmux$2335_Y[18] Y[19]=$procmux$2335_Y[19] Y[20]=$procmux$2335_Y[20] Y[21]=$procmux$2335_Y[21] Y[22]=$procmux$2335_Y[22] Y[23]=$procmux$2335_Y[23] Y[24]=$procmux$2335_Y[24] Y[25]=$procmux$2335_Y[25] Y[26]=$procmux$2335_Y[26] Y[27]=$procmux$2335_Y[27] Y[28]=$procmux$2335_Y[28] Y[29]=$procmux$2335_Y[29] Y[30]=$procmux$2335_Y[30] Y[31]=$procmux$2335_Y[31]
|
||
|
|
.cname $procmux$2335
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:150"
|
||
|
|
.param WIDTH 00000000000000000000000000100000
|
||
|
|
.subckt $mux A=cmd[2] B=cmd_i[2] S=$procmux$2339_CMP Y=$procmux$2338_Y
|
||
|
|
.cname $procmux$2338
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:111"
|
||
|
|
.param WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$false B[1]=$false B[2]=$true B[3]=$false B[4]=$true B[5]=$false B[6]=$false Y=$procmux$233_CMP
|
||
|
|
.cname $procmux$233_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $mux A=$procmux$2338_Y B=$false S=$procmux$2342_CMP Y=$procmux$2341_Y
|
||
|
|
.cname $procmux$2341
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:108"
|
||
|
|
.param WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $mux A[0]=cmd[0] A[1]=cmd[1] B[0]=$false B[1]=$false S=$procmux$2345_CMP Y[0]=$procmux$2344_Y[0] Y[1]=$procmux$2344_Y[1]
|
||
|
|
.cname $procmux$2344
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:116"
|
||
|
|
.param WIDTH 00000000000000000000000000000010
|
||
|
|
.subckt $mux A[0]=$procmux$2344_Y[0] A[1]=$procmux$2344_Y[1] B[0]=cmd_i[0] B[1]=cmd_i[1] S=$procmux$2348_CMP Y[0]=$procmux$2347_Y[0] Y[1]=$procmux$2347_Y[1]
|
||
|
|
.cname $procmux$2347
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:111"
|
||
|
|
.param WIDTH 00000000000000000000000000000010
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$true B[1]=$true B[2]=$false B[3]=$false B[4]=$true B[5]=$false B[6]=$false Y=$procmux$234_CMP
|
||
|
|
.cname $procmux$234_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $mux A[0]=$procmux$2347_Y[0] A[1]=$procmux$2347_Y[1] B[0]=$false B[1]=$false S=$procmux$2351_CMP Y[0]=$procmux$2350_Y[0] Y[1]=$procmux$2350_Y[1]
|
||
|
|
.cname $procmux$2350
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:108"
|
||
|
|
.param WIDTH 00000000000000000000000000000010
|
||
|
|
.subckt $mux A=busy B=cmd[3] S=$procmux$2354_CMP Y=$procmux$2353_Y
|
||
|
|
.cname $procmux$2353
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:111"
|
||
|
|
.param WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $mux A=$procmux$2353_Y B=$false S=$procmux$2357_CMP Y=$procmux$2356_Y
|
||
|
|
.cname $procmux$2356
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:108"
|
||
|
|
.param WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$false B[1]=$true B[2]=$false B[3]=$false B[4]=$true B[5]=$false B[6]=$false Y=$procmux$235_CMP
|
||
|
|
.cname $procmux$235_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$true B[1]=$false B[2]=$false B[3]=$false B[4]=$true B[5]=$false B[6]=$false Y=$procmux$236_CMP
|
||
|
|
.cname $procmux$236_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$false B[1]=$false B[2]=$false B[3]=$false B[4]=$true B[5]=$false B[6]=$false Y=$procmux$237_CMP
|
||
|
|
.cname $procmux$237_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$true B[1]=$true B[2]=$true B[3]=$true B[4]=$false B[5]=$false B[6]=$false Y=$procmux$238_CMP
|
||
|
|
.cname $procmux$238_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$false B[1]=$true B[2]=$true B[3]=$true B[4]=$false B[5]=$false B[6]=$false Y=$procmux$239_CMP
|
||
|
|
.cname $procmux$239_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$true B[1]=$false B[2]=$true B[3]=$true B[4]=$false B[5]=$false B[6]=$false Y=$procmux$240_CMP
|
||
|
|
.cname $procmux$240_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$false B[1]=$false B[2]=$true B[3]=$true B[4]=$false B[5]=$false B[6]=$false Y=$procmux$241_CMP
|
||
|
|
.cname $procmux$241_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$true B[1]=$true B[2]=$false B[3]=$true B[4]=$false B[5]=$false B[6]=$false Y=$procmux$242_CMP
|
||
|
|
.cname $procmux$242_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$false B[1]=$true B[2]=$false B[3]=$true B[4]=$false B[5]=$false B[6]=$false Y=$procmux$243_CMP
|
||
|
|
.cname $procmux$243_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$true B[1]=$false B[2]=$false B[3]=$true B[4]=$false B[5]=$false B[6]=$false Y=$procmux$244_CMP
|
||
|
|
.cname $procmux$244_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$false B[1]=$false B[2]=$false B[3]=$true B[4]=$false B[5]=$false B[6]=$false Y=$procmux$245_CMP
|
||
|
|
.cname $procmux$245_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$true B[1]=$true B[2]=$true B[3]=$false B[4]=$false B[5]=$false B[6]=$false Y=$procmux$246_CMP
|
||
|
|
.cname $procmux$246_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$false B[1]=$true B[2]=$true B[3]=$false B[4]=$false B[5]=$false B[6]=$false Y=$procmux$247_CMP
|
||
|
|
.cname $procmux$247_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$true B[1]=$false B[2]=$true B[3]=$false B[4]=$false B[5]=$false B[6]=$false Y=$procmux$248_CMP
|
||
|
|
.cname $procmux$248_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$false B[1]=$false B[2]=$true B[3]=$false B[4]=$false B[5]=$false B[6]=$false Y=$procmux$249_CMP
|
||
|
|
.cname $procmux$249_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$true B[1]=$true B[2]=$false B[3]=$false B[4]=$false B[5]=$false B[6]=$false Y=$procmux$250_CMP
|
||
|
|
.cname $procmux$250_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$false B[1]=$true B[2]=$false B[3]=$false B[4]=$false B[5]=$false B[6]=$false Y=$procmux$251_CMP
|
||
|
|
.cname $procmux$251_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$true B[1]=$false B[2]=$false B[3]=$false B[4]=$false B[5]=$false B[6]=$false Y=$procmux$252_CMP
|
||
|
|
.cname $procmux$252_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $mux A[0]=Wt[0] A[1]=Wt[1] A[2]=Wt[2] A[3]=Wt[3] A[4]=Wt[4] A[5]=Wt[5] A[6]=Wt[6] A[7]=Wt[7] A[8]=Wt[8] A[9]=Wt[9] A[10]=Wt[10] A[11]=Wt[11] A[12]=Wt[12] A[13]=Wt[13] A[14]=Wt[14] A[15]=Wt[15] A[16]=Wt[16] A[17]=Wt[17] A[18]=Wt[18] A[19]=Wt[19] A[20]=Wt[20] A[21]=Wt[21] A[22]=Wt[22] A[23]=Wt[23] A[24]=Wt[24] A[25]=Wt[25] A[26]=Wt[26] A[27]=Wt[27] A[28]=Wt[28] A[29]=Wt[29] A[30]=Wt[30] A[31]=Wt[31] B[0]=text_i[0] B[1]=text_i[1] B[2]=text_i[2] B[3]=text_i[3] B[4]=text_i[4] B[5]=text_i[5] B[6]=text_i[6] B[7]=text_i[7] B[8]=text_i[8] B[9]=text_i[9] B[10]=text_i[10] B[11]=text_i[11] B[12]=text_i[12] B[13]=text_i[13] B[14]=text_i[14] B[15]=text_i[15] B[16]=text_i[16] B[17]=text_i[17] B[18]=text_i[18] B[19]=text_i[19] B[20]=text_i[20] B[21]=text_i[21] B[22]=text_i[22] B[23]=text_i[23] B[24]=text_i[24] B[25]=text_i[25] B[26]=text_i[26] B[27]=text_i[27] B[28]=text_i[28] B[29]=text_i[29] B[30]=text_i[30] B[31]=text_i[31] S=$procmux$255_CMP Y[0]=$procmux$254_Y[0] Y[1]=$procmux$254_Y[1] Y[2]=$procmux$254_Y[2] Y[3]=$procmux$254_Y[3] Y[4]=$procmux$254_Y[4] Y[5]=$procmux$254_Y[5] Y[6]=$procmux$254_Y[6] Y[7]=$procmux$254_Y[7] Y[8]=$procmux$254_Y[8] Y[9]=$procmux$254_Y[9] Y[10]=$procmux$254_Y[10] Y[11]=$procmux$254_Y[11] Y[12]=$procmux$254_Y[12] Y[13]=$procmux$254_Y[13] Y[14]=$procmux$254_Y[14] Y[15]=$procmux$254_Y[15] Y[16]=$procmux$254_Y[16] Y[17]=$procmux$254_Y[17] Y[18]=$procmux$254_Y[18] Y[19]=$procmux$254_Y[19] Y[20]=$procmux$254_Y[20] Y[21]=$procmux$254_Y[21] Y[22]=$procmux$254_Y[22] Y[23]=$procmux$254_Y[23] Y[24]=$procmux$254_Y[24] Y[25]=$procmux$254_Y[25] Y[26]=$procmux$254_Y[26] Y[27]=$procmux$254_Y[27] Y[28]=$procmux$254_Y[28] Y[29]=$procmux$254_Y[29] Y[30]=$procmux$254_Y[30] Y[31]=$procmux$254_Y[31]
|
||
|
|
.cname $procmux$254
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:191"
|
||
|
|
.param WIDTH 00000000000000000000000000100000
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$false B[1]=$false B[2]=$false B[3]=$false B[4]=$false B[5]=$false B[6]=$false Y=$procmux$256_CMP
|
||
|
|
.cname $procmux$256_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $mux A[0]=$procmux$173_Y[0] A[1]=$procmux$173_Y[1] A[2]=$procmux$173_Y[2] A[3]=$procmux$173_Y[3] A[4]=$procmux$173_Y[4] A[5]=$procmux$173_Y[5] A[6]=$procmux$173_Y[6] A[7]=$procmux$173_Y[7] A[8]=$procmux$173_Y[8] A[9]=$procmux$173_Y[9] A[10]=$procmux$173_Y[10] A[11]=$procmux$173_Y[11] A[12]=$procmux$173_Y[12] A[13]=$procmux$173_Y[13] A[14]=$procmux$173_Y[14] A[15]=$procmux$173_Y[15] A[16]=$procmux$173_Y[16] A[17]=$procmux$173_Y[17] A[18]=$procmux$173_Y[18] A[19]=$procmux$173_Y[19] A[20]=$procmux$173_Y[20] A[21]=$procmux$173_Y[21] A[22]=$procmux$173_Y[22] A[23]=$procmux$173_Y[23] A[24]=$procmux$173_Y[24] A[25]=$procmux$173_Y[25] A[26]=$procmux$173_Y[26] A[27]=$procmux$173_Y[27] A[28]=$procmux$173_Y[28] A[29]=$procmux$173_Y[29] A[30]=$procmux$173_Y[30] A[31]=$procmux$173_Y[31] B[0]=$false B[1]=$false B[2]=$false B[3]=$false B[4]=$false B[5]=$false B[6]=$false B[7]=$false B[8]=$false B[9]=$false B[10]=$false B[11]=$false B[12]=$false B[13]=$false B[14]=$false B[15]=$false B[16]=$false B[17]=$false B[18]=$false B[19]=$false B[20]=$false B[21]=$false B[22]=$false B[23]=$false B[24]=$false B[25]=$false B[26]=$false B[27]=$false B[28]=$false B[29]=$false B[30]=$false B[31]=$false S=$procmux$259_CMP Y[0]=$procmux$258_Y[0] Y[1]=$procmux$258_Y[1] Y[2]=$procmux$258_Y[2] Y[3]=$procmux$258_Y[3] Y[4]=$procmux$258_Y[4] Y[5]=$procmux$258_Y[5] Y[6]=$procmux$258_Y[6] Y[7]=$procmux$258_Y[7] Y[8]=$procmux$258_Y[8] Y[9]=$procmux$258_Y[9] Y[10]=$procmux$258_Y[10] Y[11]=$procmux$258_Y[11] Y[12]=$procmux$258_Y[12] Y[13]=$procmux$258_Y[13] Y[14]=$procmux$258_Y[14] Y[15]=$procmux$258_Y[15] Y[16]=$procmux$258_Y[16] Y[17]=$procmux$258_Y[17] Y[18]=$procmux$258_Y[18] Y[19]=$procmux$258_Y[19] Y[20]=$procmux$258_Y[20] Y[21]=$procmux$258_Y[21] Y[22]=$procmux$258_Y[22] Y[23]=$procmux$258_Y[23] Y[24]=$procmux$258_Y[24] Y[25]=$procmux$258_Y[25] Y[26]=$procmux$258_Y[26] Y[27]=$procmux$258_Y[27] Y[28]=$procmux$258_Y[28] Y[29]=$procmux$258_Y[29] Y[30]=$procmux$258_Y[30] Y[31]=$procmux$258_Y[31]
|
||
|
|
.cname $procmux$258
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:150"
|
||
|
|
.param WIDTH 00000000000000000000000000100000
|
||
|
|
.subckt $pmux A[0]=W14[0] A[1]=W14[1] A[2]=W14[2] A[3]=W14[3] A[4]=W14[4] A[5]=W14[5] A[6]=W14[6] A[7]=W14[7] A[8]=W14[8] A[9]=W14[9] A[10]=W14[10] A[11]=W14[11] A[12]=W14[12] A[13]=W14[13] A[14]=W14[14] A[15]=W14[15] A[16]=W14[16] A[17]=W14[17] A[18]=W14[18] A[19]=W14[19] A[20]=W14[20] A[21]=W14[21] A[22]=W14[22] A[23]=W14[23] A[24]=W14[24] A[25]=W14[25] A[26]=W14[26] A[27]=W14[27] A[28]=W14[28] A[29]=W14[29] A[30]=W14[30] A[31]=W14[31] B[0]=Wt[0] B[1]=Wt[1] B[2]=Wt[2] B[3]=Wt[3] B[4]=Wt[4] B[5]=Wt[5] B[6]=Wt[6] B[7]=Wt[7] B[8]=Wt[8] B[9]=Wt[9] B[10]=Wt[10] B[11]=Wt[11] B[12]=Wt[12] B[13]=Wt[13] B[14]=Wt[14] B[15]=Wt[15] B[16]=Wt[16] B[17]=Wt[17] B[18]=Wt[18] B[19]=Wt[19] B[20]=Wt[20] B[21]=Wt[21] B[22]=Wt[22] B[23]=Wt[23] B[24]=Wt[24] B[25]=Wt[25] B[26]=Wt[26] B[27]=Wt[27] B[28]=Wt[28] B[29]=Wt[29] B[30]=Wt[30] B[31]=Wt[31] B[32]=Wt[0] B[33]=Wt[1] B[34]=Wt[2] B[35]=Wt[3] B[36]=Wt[4] B[37]=Wt[5] B[38]=Wt[6] B[39]=Wt[7] B[40]=Wt[8] B[41]=Wt[9] B[42]=Wt[10] B[43]=Wt[11] B[44]=Wt[12] B[45]=Wt[13] B[46]=Wt[14] B[47]=Wt[15] B[48]=Wt[16] B[49]=Wt[17] B[50]=Wt[18] B[51]=Wt[19] B[52]=Wt[20] B[53]=Wt[21] B[54]=Wt[22] B[55]=Wt[23] B[56]=Wt[24] B[57]=Wt[25] B[58]=Wt[26] B[59]=Wt[27] B[60]=Wt[28] B[61]=Wt[29] B[62]=Wt[30] B[63]=Wt[31] B[64]=Wt[0] B[65]=Wt[1] B[66]=Wt[2] B[67]=Wt[3] B[68]=Wt[4] B[69]=Wt[5] B[70]=Wt[6] B[71]=Wt[7] B[72]=Wt[8] B[73]=Wt[9] B[74]=Wt[10] B[75]=Wt[11] B[76]=Wt[12] B[77]=Wt[13] B[78]=Wt[14] B[79]=Wt[15] B[80]=Wt[16] B[81]=Wt[17] B[82]=Wt[18] B[83]=Wt[19] B[84]=Wt[20] B[85]=Wt[21] B[86]=Wt[22] B[87]=Wt[23] B[88]=Wt[24] B[89]=Wt[25] B[90]=Wt[26] B[91]=Wt[27] B[92]=Wt[28] B[93]=Wt[29] B[94]=Wt[30] B[95]=Wt[31] B[96]=Wt[0] B[97]=Wt[1] B[98]=Wt[2] B[99]=Wt[3] B[100]=Wt[4] B[101]=Wt[5] B[102]=Wt[6] B[103]=Wt[7] B[104]=Wt[8] B[105]=Wt[9] B[106]=Wt[10] B[107]=Wt[11] B[108]=Wt[12] B[109]=Wt[13] B[110]=Wt[14] B[111]=Wt[15] B[112]=Wt[16] B[113]=Wt[17] B[114]=Wt[18] B[115]=Wt[19] B[116]=Wt[20] B[117]=Wt[21] B[118]=Wt[22] B[119]=Wt[23] B[120]=Wt[24] B[121]=Wt[25] B[122]=Wt[26] B[123]=Wt[27] B[124]=Wt[28] B[125]=Wt[29] B[126]=Wt[30] B[127]=Wt[31] B[128]=Wt[0] B[129]=Wt[1] B[130]=Wt[2] B[131]=Wt[3] B[132]=Wt[4] B[133]=Wt[5] B[134]=Wt[6] B[135]=Wt[7] B[136]=Wt[8] B[137]=Wt[9] B[138]=Wt[10] B[139]=Wt[11] B[140]=Wt[12] B[141]=Wt[13] B[142]=Wt[14] B[143]=Wt[15] B[144]=Wt[16] B[145]=Wt[17] B[146]=Wt[18] B[147]=Wt[19] B[148]=Wt[20] B[149]=Wt[21] B[150]=Wt[22] B[151]=Wt[23] B[152]=Wt[24] B[153]=Wt[25] B[154]=Wt[26] B[155]=Wt[27] B[156]=Wt[28] B[157]=Wt[29] B[158]=Wt[30] B[159]=Wt[31] B[160]=Wt[0] B[161]=Wt[1] B[162]=Wt[2] B[163]=Wt[3] B[164]=Wt[4] B[165]=Wt[5] B[166]=Wt[6] B[167]=Wt[7] B[168]=Wt[8] B[169]=Wt[9] B[170]=Wt[10] B[171]=Wt[11] B[172]=Wt[12] B[173]=Wt[13] B[174]=Wt[14] B[175]=Wt[15] B[176]=Wt[16] B[177]=Wt[17] B[178]=Wt[18] B[179]=Wt[19] B[180]=Wt[20] B[181]=Wt[21] B[182]=Wt[22] B[183]=Wt[23] B[184]=Wt[24] B[185]=Wt[25] B[186]=Wt[26] B[187]=Wt[27] B[188]=Wt[28] B[189]=Wt[29] B[190]=Wt[30] B[191]=Wt[31] B[192]=Wt[0] B[193]=Wt[1] B[194]=Wt[2] B[195]=Wt[3] B[196]=Wt[4] B[197]=Wt[5] B[198]=Wt[6] B[199]=Wt[7] B[200]=Wt[8] B[201]=Wt[9] B[202]=Wt[10] B[203]=Wt[11] B[204]=Wt[12] B[205]=Wt[13] B[206]=Wt[14] B[207]=Wt[15] B[208]=Wt[16] B[209]=Wt[17] B[210]=Wt[18] B[211]=Wt[19] B[212]=Wt[20] B[213]=Wt[21] B[214]=Wt[22] B[215]=Wt[23] B[216]=Wt[24] B[217]=Wt[25] B[218]=Wt[26] B[219]=Wt[27] B[220]=Wt[28] B[221]=Wt[29] B[222]=Wt[30] B[223]=Wt[31] B[224]=Wt[0] B[225]=Wt[1] B[226]=Wt[2] B[227]=Wt[3] B[228]=Wt[4] B[229]=Wt[5] B[230]=Wt[6] B[231]=Wt[7] B[232]=Wt[8] B[233]=Wt[9] B[234]=Wt[10] B[235]=Wt[11] B[236]=Wt[12] B[237]=Wt[13] B[238]=Wt[14] B[239]=Wt[15] B[240]=Wt[16] B[241]=Wt[17] B[242]=Wt[18] B[243]=Wt[19] B[244]=Wt[20] B[245]=Wt[21] B[246]=Wt[22] B[247]=Wt[23] B[248]=Wt[24] B[249]=Wt[25] B[250]=Wt[26] B[251]=Wt[27] B[252]=Wt[28] B[253]=Wt[29] B[254]=Wt[30] B[255]=Wt[31] B[256]=Wt[0] B[257]=Wt[1] B[258]=Wt[2] B[259]=Wt[3] B[260]=Wt[4] B[261]=Wt[5] B[262]=Wt[6] B[263]=Wt[7] B[264]=Wt[8] B[265]=Wt[9] B[266]=Wt[10] B[267]=Wt[11] B[268]=Wt[12] B[269]=Wt[13] B[270]=Wt[14] B[271]=Wt[15] B[272]=Wt[16] B[273]=Wt[17] B[274]=Wt[18] B[2
|
||
|
|
.cname $procmux$262
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param S_WIDTH 00000000000000000000000001000001
|
||
|
|
.param WIDTH 00000000000000000000000000100000
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$true B[1]=$true B[2]=$true B[3]=$true B[4]=$false B[5]=$false B[6]=$true Y=$procmux$263_CMP
|
||
|
|
.cname $procmux$263_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$false B[1]=$true B[2]=$true B[3]=$true B[4]=$false B[5]=$false B[6]=$true Y=$procmux$264_CMP
|
||
|
|
.cname $procmux$264_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$true B[1]=$false B[2]=$true B[3]=$true B[4]=$false B[5]=$false B[6]=$true Y=$procmux$265_CMP
|
||
|
|
.cname $procmux$265_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$false B[1]=$false B[2]=$true B[3]=$true B[4]=$false B[5]=$false B[6]=$true Y=$procmux$266_CMP
|
||
|
|
.cname $procmux$266_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$true B[1]=$true B[2]=$false B[3]=$true B[4]=$false B[5]=$false B[6]=$true Y=$procmux$267_CMP
|
||
|
|
.cname $procmux$267_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$false B[1]=$true B[2]=$false B[3]=$true B[4]=$false B[5]=$false B[6]=$true Y=$procmux$268_CMP
|
||
|
|
.cname $procmux$268_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$true B[1]=$false B[2]=$false B[3]=$true B[4]=$false B[5]=$false B[6]=$true Y=$procmux$269_CMP
|
||
|
|
.cname $procmux$269_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$false B[1]=$false B[2]=$false B[3]=$true B[4]=$false B[5]=$false B[6]=$true Y=$procmux$270_CMP
|
||
|
|
.cname $procmux$270_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$true B[1]=$true B[2]=$true B[3]=$false B[4]=$false B[5]=$false B[6]=$true Y=$procmux$271_CMP
|
||
|
|
.cname $procmux$271_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$false B[1]=$true B[2]=$true B[3]=$false B[4]=$false B[5]=$false B[6]=$true Y=$procmux$272_CMP
|
||
|
|
.cname $procmux$272_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$true B[1]=$false B[2]=$true B[3]=$false B[4]=$false B[5]=$false B[6]=$true Y=$procmux$273_CMP
|
||
|
|
.cname $procmux$273_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$false B[1]=$false B[2]=$true B[3]=$false B[4]=$false B[5]=$false B[6]=$true Y=$procmux$274_CMP
|
||
|
|
.cname $procmux$274_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$true B[1]=$true B[2]=$false B[3]=$false B[4]=$false B[5]=$false B[6]=$true Y=$procmux$275_CMP
|
||
|
|
.cname $procmux$275_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$false B[1]=$true B[2]=$false B[3]=$false B[4]=$false B[5]=$false B[6]=$true Y=$procmux$276_CMP
|
||
|
|
.cname $procmux$276_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$true B[1]=$false B[2]=$false B[3]=$false B[4]=$false B[5]=$false B[6]=$true Y=$procmux$277_CMP
|
||
|
|
.cname $procmux$277_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$false B[1]=$false B[2]=$false B[3]=$false B[4]=$false B[5]=$false B[6]=$true Y=$procmux$278_CMP
|
||
|
|
.cname $procmux$278_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$true B[1]=$true B[2]=$true B[3]=$true B[4]=$true B[5]=$true B[6]=$false Y=$procmux$279_CMP
|
||
|
|
.cname $procmux$279_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$false B[1]=$true B[2]=$true B[3]=$true B[4]=$true B[5]=$true B[6]=$false Y=$procmux$280_CMP
|
||
|
|
.cname $procmux$280_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$true B[1]=$false B[2]=$true B[3]=$true B[4]=$true B[5]=$true B[6]=$false Y=$procmux$281_CMP
|
||
|
|
.cname $procmux$281_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$false B[1]=$false B[2]=$true B[3]=$true B[4]=$true B[5]=$true B[6]=$false Y=$procmux$282_CMP
|
||
|
|
.cname $procmux$282_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$true B[1]=$true B[2]=$false B[3]=$true B[4]=$true B[5]=$true B[6]=$false Y=$procmux$283_CMP
|
||
|
|
.cname $procmux$283_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$false B[1]=$true B[2]=$false B[3]=$true B[4]=$true B[5]=$true B[6]=$false Y=$procmux$284_CMP
|
||
|
|
.cname $procmux$284_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$true B[1]=$false B[2]=$false B[3]=$true B[4]=$true B[5]=$true B[6]=$false Y=$procmux$285_CMP
|
||
|
|
.cname $procmux$285_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$false B[1]=$false B[2]=$false B[3]=$true B[4]=$true B[5]=$true B[6]=$false Y=$procmux$286_CMP
|
||
|
|
.cname $procmux$286_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$true B[1]=$true B[2]=$true B[3]=$false B[4]=$true B[5]=$true B[6]=$false Y=$procmux$287_CMP
|
||
|
|
.cname $procmux$287_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$false B[1]=$true B[2]=$true B[3]=$false B[4]=$true B[5]=$true B[6]=$false Y=$procmux$288_CMP
|
||
|
|
.cname $procmux$288_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$true B[1]=$false B[2]=$true B[3]=$false B[4]=$true B[5]=$true B[6]=$false Y=$procmux$289_CMP
|
||
|
|
.cname $procmux$289_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$false B[1]=$false B[2]=$true B[3]=$false B[4]=$true B[5]=$true B[6]=$false Y=$procmux$290_CMP
|
||
|
|
.cname $procmux$290_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$true B[1]=$true B[2]=$false B[3]=$false B[4]=$true B[5]=$true B[6]=$false Y=$procmux$291_CMP
|
||
|
|
.cname $procmux$291_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$false B[1]=$true B[2]=$false B[3]=$false B[4]=$true B[5]=$true B[6]=$false Y=$procmux$292_CMP
|
||
|
|
.cname $procmux$292_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$true B[1]=$false B[2]=$false B[3]=$false B[4]=$true B[5]=$true B[6]=$false Y=$procmux$293_CMP
|
||
|
|
.cname $procmux$293_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$false B[1]=$false B[2]=$false B[3]=$false B[4]=$true B[5]=$true B[6]=$false Y=$procmux$294_CMP
|
||
|
|
.cname $procmux$294_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$true B[1]=$true B[2]=$true B[3]=$true B[4]=$false B[5]=$true B[6]=$false Y=$procmux$295_CMP
|
||
|
|
.cname $procmux$295_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$false B[1]=$true B[2]=$true B[3]=$true B[4]=$false B[5]=$true B[6]=$false Y=$procmux$296_CMP
|
||
|
|
.cname $procmux$296_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$true B[1]=$false B[2]=$true B[3]=$true B[4]=$false B[5]=$true B[6]=$false Y=$procmux$297_CMP
|
||
|
|
.cname $procmux$297_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$false B[1]=$false B[2]=$true B[3]=$true B[4]=$false B[5]=$true B[6]=$false Y=$procmux$298_CMP
|
||
|
|
.cname $procmux$298_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$true B[1]=$true B[2]=$false B[3]=$true B[4]=$false B[5]=$true B[6]=$false Y=$procmux$299_CMP
|
||
|
|
.cname $procmux$299_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$false B[1]=$true B[2]=$false B[3]=$true B[4]=$false B[5]=$true B[6]=$false Y=$procmux$300_CMP
|
||
|
|
.cname $procmux$300_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$true B[1]=$false B[2]=$false B[3]=$true B[4]=$false B[5]=$true B[6]=$false Y=$procmux$301_CMP
|
||
|
|
.cname $procmux$301_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$false B[1]=$false B[2]=$false B[3]=$true B[4]=$false B[5]=$true B[6]=$false Y=$procmux$302_CMP
|
||
|
|
.cname $procmux$302_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$true B[1]=$true B[2]=$true B[3]=$false B[4]=$false B[5]=$true B[6]=$false Y=$procmux$303_CMP
|
||
|
|
.cname $procmux$303_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$false B[1]=$true B[2]=$true B[3]=$false B[4]=$false B[5]=$true B[6]=$false Y=$procmux$304_CMP
|
||
|
|
.cname $procmux$304_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$true B[1]=$false B[2]=$true B[3]=$false B[4]=$false B[5]=$true B[6]=$false Y=$procmux$305_CMP
|
||
|
|
.cname $procmux$305_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$false B[1]=$false B[2]=$true B[3]=$false B[4]=$false B[5]=$true B[6]=$false Y=$procmux$306_CMP
|
||
|
|
.cname $procmux$306_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$true B[1]=$true B[2]=$false B[3]=$false B[4]=$false B[5]=$true B[6]=$false Y=$procmux$307_CMP
|
||
|
|
.cname $procmux$307_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$false B[1]=$true B[2]=$false B[3]=$false B[4]=$false B[5]=$true B[6]=$false Y=$procmux$308_CMP
|
||
|
|
.cname $procmux$308_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$true B[1]=$false B[2]=$false B[3]=$false B[4]=$false B[5]=$true B[6]=$false Y=$procmux$309_CMP
|
||
|
|
.cname $procmux$309_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$false B[1]=$false B[2]=$false B[3]=$false B[4]=$false B[5]=$true B[6]=$false Y=$procmux$310_CMP
|
||
|
|
.cname $procmux$310_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$true B[1]=$true B[2]=$true B[3]=$true B[4]=$true B[5]=$false B[6]=$false Y=$procmux$311_CMP
|
||
|
|
.cname $procmux$311_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$false B[1]=$true B[2]=$true B[3]=$true B[4]=$true B[5]=$false B[6]=$false Y=$procmux$312_CMP
|
||
|
|
.cname $procmux$312_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$true B[1]=$false B[2]=$true B[3]=$true B[4]=$true B[5]=$false B[6]=$false Y=$procmux$313_CMP
|
||
|
|
.cname $procmux$313_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$false B[1]=$false B[2]=$true B[3]=$true B[4]=$true B[5]=$false B[6]=$false Y=$procmux$314_CMP
|
||
|
|
.cname $procmux$314_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$true B[1]=$true B[2]=$false B[3]=$true B[4]=$true B[5]=$false B[6]=$false Y=$procmux$315_CMP
|
||
|
|
.cname $procmux$315_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$false B[1]=$true B[2]=$false B[3]=$true B[4]=$true B[5]=$false B[6]=$false Y=$procmux$316_CMP
|
||
|
|
.cname $procmux$316_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$true B[1]=$false B[2]=$false B[3]=$true B[4]=$true B[5]=$false B[6]=$false Y=$procmux$317_CMP
|
||
|
|
.cname $procmux$317_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$false B[1]=$false B[2]=$false B[3]=$true B[4]=$true B[5]=$false B[6]=$false Y=$procmux$318_CMP
|
||
|
|
.cname $procmux$318_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$true B[1]=$true B[2]=$true B[3]=$false B[4]=$true B[5]=$false B[6]=$false Y=$procmux$319_CMP
|
||
|
|
.cname $procmux$319_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$false B[1]=$true B[2]=$true B[3]=$false B[4]=$true B[5]=$false B[6]=$false Y=$procmux$320_CMP
|
||
|
|
.cname $procmux$320_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$true B[1]=$false B[2]=$true B[3]=$false B[4]=$true B[5]=$false B[6]=$false Y=$procmux$321_CMP
|
||
|
|
.cname $procmux$321_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$false B[1]=$false B[2]=$true B[3]=$false B[4]=$true B[5]=$false B[6]=$false Y=$procmux$322_CMP
|
||
|
|
.cname $procmux$322_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$true B[1]=$true B[2]=$false B[3]=$false B[4]=$true B[5]=$false B[6]=$false Y=$procmux$323_CMP
|
||
|
|
.cname $procmux$323_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$false B[1]=$true B[2]=$false B[3]=$false B[4]=$true B[5]=$false B[6]=$false Y=$procmux$324_CMP
|
||
|
|
.cname $procmux$324_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$true B[1]=$false B[2]=$false B[3]=$false B[4]=$true B[5]=$false B[6]=$false Y=$procmux$325_CMP
|
||
|
|
.cname $procmux$325_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$false B[1]=$false B[2]=$false B[3]=$false B[4]=$true B[5]=$false B[6]=$false Y=$procmux$326_CMP
|
||
|
|
.cname $procmux$326_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$false B[1]=$true B[2]=$true B[3]=$true B[4]=$false B[5]=$false B[6]=$false Y=$procmux$327_CMP
|
||
|
|
.cname $procmux$327_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $mux A[0]=$procmux$262_Y[0] A[1]=$procmux$262_Y[1] A[2]=$procmux$262_Y[2] A[3]=$procmux$262_Y[3] A[4]=$procmux$262_Y[4] A[5]=$procmux$262_Y[5] A[6]=$procmux$262_Y[6] A[7]=$procmux$262_Y[7] A[8]=$procmux$262_Y[8] A[9]=$procmux$262_Y[9] A[10]=$procmux$262_Y[10] A[11]=$procmux$262_Y[11] A[12]=$procmux$262_Y[12] A[13]=$procmux$262_Y[13] A[14]=$procmux$262_Y[14] A[15]=$procmux$262_Y[15] A[16]=$procmux$262_Y[16] A[17]=$procmux$262_Y[17] A[18]=$procmux$262_Y[18] A[19]=$procmux$262_Y[19] A[20]=$procmux$262_Y[20] A[21]=$procmux$262_Y[21] A[22]=$procmux$262_Y[22] A[23]=$procmux$262_Y[23] A[24]=$procmux$262_Y[24] A[25]=$procmux$262_Y[25] A[26]=$procmux$262_Y[26] A[27]=$procmux$262_Y[27] A[28]=$procmux$262_Y[28] A[29]=$procmux$262_Y[29] A[30]=$procmux$262_Y[30] A[31]=$procmux$262_Y[31] B[0]=$false B[1]=$false B[2]=$false B[3]=$false B[4]=$false B[5]=$false B[6]=$false B[7]=$false B[8]=$false B[9]=$false B[10]=$false B[11]=$false B[12]=$false B[13]=$false B[14]=$false B[15]=$false B[16]=$false B[17]=$false B[18]=$false B[19]=$false B[20]=$false B[21]=$false B[22]=$false B[23]=$false B[24]=$false B[25]=$false B[26]=$false B[27]=$false B[28]=$false B[29]=$false B[30]=$false B[31]=$false S=$procmux$330_CMP Y[0]=$procmux$329_Y[0] Y[1]=$procmux$329_Y[1] Y[2]=$procmux$329_Y[2] Y[3]=$procmux$329_Y[3] Y[4]=$procmux$329_Y[4] Y[5]=$procmux$329_Y[5] Y[6]=$procmux$329_Y[6] Y[7]=$procmux$329_Y[7] Y[8]=$procmux$329_Y[8] Y[9]=$procmux$329_Y[9] Y[10]=$procmux$329_Y[10] Y[11]=$procmux$329_Y[11] Y[12]=$procmux$329_Y[12] Y[13]=$procmux$329_Y[13] Y[14]=$procmux$329_Y[14] Y[15]=$procmux$329_Y[15] Y[16]=$procmux$329_Y[16] Y[17]=$procmux$329_Y[17] Y[18]=$procmux$329_Y[18] Y[19]=$procmux$329_Y[19] Y[20]=$procmux$329_Y[20] Y[21]=$procmux$329_Y[21] Y[22]=$procmux$329_Y[22] Y[23]=$procmux$329_Y[23] Y[24]=$procmux$329_Y[24] Y[25]=$procmux$329_Y[25] Y[26]=$procmux$329_Y[26] Y[27]=$procmux$329_Y[27] Y[28]=$procmux$329_Y[28] Y[29]=$procmux$329_Y[29] Y[30]=$procmux$329_Y[30] Y[31]=$procmux$329_Y[31]
|
||
|
|
.cname $procmux$329
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:150"
|
||
|
|
.param WIDTH 00000000000000000000000000100000
|
||
|
|
.subckt $pmux A[0]=W13[0] A[1]=W13[1] A[2]=W13[2] A[3]=W13[3] A[4]=W13[4] A[5]=W13[5] A[6]=W13[6] A[7]=W13[7] A[8]=W13[8] A[9]=W13[9] A[10]=W13[10] A[11]=W13[11] A[12]=W13[12] A[13]=W13[13] A[14]=W13[14] A[15]=W13[15] A[16]=W13[16] A[17]=W13[17] A[18]=W13[18] A[19]=W13[19] A[20]=W13[20] A[21]=W13[21] A[22]=W13[22] A[23]=W13[23] A[24]=W13[24] A[25]=W13[25] A[26]=W13[26] A[27]=W13[27] A[28]=W13[28] A[29]=W13[29] A[30]=W13[30] A[31]=W13[31] B[0]=W14[0] B[1]=W14[1] B[2]=W14[2] B[3]=W14[3] B[4]=W14[4] B[5]=W14[5] B[6]=W14[6] B[7]=W14[7] B[8]=W14[8] B[9]=W14[9] B[10]=W14[10] B[11]=W14[11] B[12]=W14[12] B[13]=W14[13] B[14]=W14[14] B[15]=W14[15] B[16]=W14[16] B[17]=W14[17] B[18]=W14[18] B[19]=W14[19] B[20]=W14[20] B[21]=W14[21] B[22]=W14[22] B[23]=W14[23] B[24]=W14[24] B[25]=W14[25] B[26]=W14[26] B[27]=W14[27] B[28]=W14[28] B[29]=W14[29] B[30]=W14[30] B[31]=W14[31] B[32]=W14[0] B[33]=W14[1] B[34]=W14[2] B[35]=W14[3] B[36]=W14[4] B[37]=W14[5] B[38]=W14[6] B[39]=W14[7] B[40]=W14[8] B[41]=W14[9] B[42]=W14[10] B[43]=W14[11] B[44]=W14[12] B[45]=W14[13] B[46]=W14[14] B[47]=W14[15] B[48]=W14[16] B[49]=W14[17] B[50]=W14[18] B[51]=W14[19] B[52]=W14[20] B[53]=W14[21] B[54]=W14[22] B[55]=W14[23] B[56]=W14[24] B[57]=W14[25] B[58]=W14[26] B[59]=W14[27] B[60]=W14[28] B[61]=W14[29] B[62]=W14[30] B[63]=W14[31] B[64]=W14[0] B[65]=W14[1] B[66]=W14[2] B[67]=W14[3] B[68]=W14[4] B[69]=W14[5] B[70]=W14[6] B[71]=W14[7] B[72]=W14[8] B[73]=W14[9] B[74]=W14[10] B[75]=W14[11] B[76]=W14[12] B[77]=W14[13] B[78]=W14[14] B[79]=W14[15] B[80]=W14[16] B[81]=W14[17] B[82]=W14[18] B[83]=W14[19] B[84]=W14[20] B[85]=W14[21] B[86]=W14[22] B[87]=W14[23] B[88]=W14[24] B[89]=W14[25] B[90]=W14[26] B[91]=W14[27] B[92]=W14[28] B[93]=W14[29] B[94]=W14[30] B[95]=W14[31] B[96]=W14[0] B[97]=W14[1] B[98]=W14[2] B[99]=W14[3] B[100]=W14[4] B[101]=W14[5] B[102]=W14[6] B[103]=W14[7] B[104]=W14[8] B[105]=W14[9] B[106]=W14[10] B[107]=W14[11] B[108]=W14[12] B[109]=W14[13] B[110]=W14[14] B[111]=W14[15] B[112]=W14[16] B[113]=W14[17] B[114]=W14[18] B[115]=W14[19] B[116]=W14[20] B[117]=W14[21] B[118]=W14[22] B[119]=W14[23] B[120]=W14[24] B[121]=W14[25] B[122]=W14[26] B[123]=W14[27] B[124]=W14[28] B[125]=W14[29] B[126]=W14[30] B[127]=W14[31] B[128]=W14[0] B[129]=W14[1] B[130]=W14[2] B[131]=W14[3] B[132]=W14[4] B[133]=W14[5] B[134]=W14[6] B[135]=W14[7] B[136]=W14[8] B[137]=W14[9] B[138]=W14[10] B[139]=W14[11] B[140]=W14[12] B[141]=W14[13] B[142]=W14[14] B[143]=W14[15] B[144]=W14[16] B[145]=W14[17] B[146]=W14[18] B[147]=W14[19] B[148]=W14[20] B[149]=W14[21] B[150]=W14[22] B[151]=W14[23] B[152]=W14[24] B[153]=W14[25] B[154]=W14[26] B[155]=W14[27] B[156]=W14[28] B[157]=W14[29] B[158]=W14[30] B[159]=W14[31] B[160]=W14[0] B[161]=W14[1] B[162]=W14[2] B[163]=W14[3] B[164]=W14[4] B[165]=W14[5] B[166]=W14[6] B[167]=W14[7] B[168]=W14[8] B[169]=W14[9] B[170]=W14[10] B[171]=W14[11] B[172]=W14[12] B[173]=W14[13] B[174]=W14[14] B[175]=W14[15] B[176]=W14[16] B[177]=W14[17] B[178]=W14[18] B[179]=W14[19] B[180]=W14[20] B[181]=W14[21] B[182]=W14[22] B[183]=W14[23] B[184]=W14[24] B[185]=W14[25] B[186]=W14[26] B[187]=W14[27] B[188]=W14[28] B[189]=W14[29] B[190]=W14[30] B[191]=W14[31] B[192]=W14[0] B[193]=W14[1] B[194]=W14[2] B[195]=W14[3] B[196]=W14[4] B[197]=W14[5] B[198]=W14[6] B[199]=W14[7] B[200]=W14[8] B[201]=W14[9] B[202]=W14[10] B[203]=W14[11] B[204]=W14[12] B[205]=W14[13] B[206]=W14[14] B[207]=W14[15] B[208]=W14[16] B[209]=W14[17] B[210]=W14[18] B[211]=W14[19] B[212]=W14[20] B[213]=W14[21] B[214]=W14[22] B[215]=W14[23] B[216]=W14[24] B[217]=W14[25] B[218]=W14[26] B[219]=W14[27] B[220]=W14[28] B[221]=W14[29] B[222]=W14[30] B[223]=W14[31] B[224]=W14[0] B[225]=W14[1] B[226]=W14[2] B[227]=W14[3] B[228]=W14[4] B[229]=W14[5] B[230]=W14[6] B[231]=W14[7] B[232]=W14[8] B[233]=W14[9] B[234]=W14[10] B[235]=W14[11] B[236]=W14[12] B[237]=W14[13] B[238]=W14[14] B[239]=W14[15] B[240]=W14[16] B[241]=W14[17] B[242]=W14[18] B[243]=W14[19] B[244]=W14[20] B[245]=W14[21] B[246]=W14[22] B[247]=W14[23] B[248]=W14[24] B[249]=W14[25] B[250]=W14[26] B[251]=W14[27] B[252]=W14[28] B[253]=W14[29] B[254]=W14[30] B[255]=W14[31] B[2
|
||
|
|
.cname $procmux$333
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param S_WIDTH 00000000000000000000000001000001
|
||
|
|
.param WIDTH 00000000000000000000000000100000
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$true B[1]=$true B[2]=$true B[3]=$true B[4]=$false B[5]=$false B[6]=$true Y=$procmux$334_CMP
|
||
|
|
.cname $procmux$334_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$false B[1]=$true B[2]=$true B[3]=$true B[4]=$false B[5]=$false B[6]=$true Y=$procmux$335_CMP
|
||
|
|
.cname $procmux$335_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$true B[1]=$false B[2]=$true B[3]=$true B[4]=$false B[5]=$false B[6]=$true Y=$procmux$336_CMP
|
||
|
|
.cname $procmux$336_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$false B[1]=$false B[2]=$true B[3]=$true B[4]=$false B[5]=$false B[6]=$true Y=$procmux$337_CMP
|
||
|
|
.cname $procmux$337_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$true B[1]=$true B[2]=$false B[3]=$true B[4]=$false B[5]=$false B[6]=$true Y=$procmux$338_CMP
|
||
|
|
.cname $procmux$338_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$false B[1]=$true B[2]=$false B[3]=$true B[4]=$false B[5]=$false B[6]=$true Y=$procmux$339_CMP
|
||
|
|
.cname $procmux$339_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$true B[1]=$false B[2]=$false B[3]=$true B[4]=$false B[5]=$false B[6]=$true Y=$procmux$340_CMP
|
||
|
|
.cname $procmux$340_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$false B[1]=$false B[2]=$false B[3]=$true B[4]=$false B[5]=$false B[6]=$true Y=$procmux$341_CMP
|
||
|
|
.cname $procmux$341_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$true B[1]=$true B[2]=$true B[3]=$false B[4]=$false B[5]=$false B[6]=$true Y=$procmux$342_CMP
|
||
|
|
.cname $procmux$342_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$false B[1]=$true B[2]=$true B[3]=$false B[4]=$false B[5]=$false B[6]=$true Y=$procmux$343_CMP
|
||
|
|
.cname $procmux$343_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$true B[1]=$false B[2]=$true B[3]=$false B[4]=$false B[5]=$false B[6]=$true Y=$procmux$344_CMP
|
||
|
|
.cname $procmux$344_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$false B[1]=$false B[2]=$true B[3]=$false B[4]=$false B[5]=$false B[6]=$true Y=$procmux$345_CMP
|
||
|
|
.cname $procmux$345_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$true B[1]=$true B[2]=$false B[3]=$false B[4]=$false B[5]=$false B[6]=$true Y=$procmux$346_CMP
|
||
|
|
.cname $procmux$346_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$false B[1]=$true B[2]=$false B[3]=$false B[4]=$false B[5]=$false B[6]=$true Y=$procmux$347_CMP
|
||
|
|
.cname $procmux$347_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$true B[1]=$false B[2]=$false B[3]=$false B[4]=$false B[5]=$false B[6]=$true Y=$procmux$348_CMP
|
||
|
|
.cname $procmux$348_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$false B[1]=$false B[2]=$false B[3]=$false B[4]=$false B[5]=$false B[6]=$true Y=$procmux$349_CMP
|
||
|
|
.cname $procmux$349_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$true B[1]=$true B[2]=$true B[3]=$true B[4]=$true B[5]=$true B[6]=$false Y=$procmux$350_CMP
|
||
|
|
.cname $procmux$350_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$false B[1]=$true B[2]=$true B[3]=$true B[4]=$true B[5]=$true B[6]=$false Y=$procmux$351_CMP
|
||
|
|
.cname $procmux$351_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$true B[1]=$false B[2]=$true B[3]=$true B[4]=$true B[5]=$true B[6]=$false Y=$procmux$352_CMP
|
||
|
|
.cname $procmux$352_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$false B[1]=$false B[2]=$true B[3]=$true B[4]=$true B[5]=$true B[6]=$false Y=$procmux$353_CMP
|
||
|
|
.cname $procmux$353_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$true B[1]=$true B[2]=$false B[3]=$true B[4]=$true B[5]=$true B[6]=$false Y=$procmux$354_CMP
|
||
|
|
.cname $procmux$354_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$false B[1]=$true B[2]=$false B[3]=$true B[4]=$true B[5]=$true B[6]=$false Y=$procmux$355_CMP
|
||
|
|
.cname $procmux$355_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$true B[1]=$false B[2]=$false B[3]=$true B[4]=$true B[5]=$true B[6]=$false Y=$procmux$356_CMP
|
||
|
|
.cname $procmux$356_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$false B[1]=$false B[2]=$false B[3]=$true B[4]=$true B[5]=$true B[6]=$false Y=$procmux$357_CMP
|
||
|
|
.cname $procmux$357_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$true B[1]=$true B[2]=$true B[3]=$false B[4]=$true B[5]=$true B[6]=$false Y=$procmux$358_CMP
|
||
|
|
.cname $procmux$358_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$false B[1]=$true B[2]=$true B[3]=$false B[4]=$true B[5]=$true B[6]=$false Y=$procmux$359_CMP
|
||
|
|
.cname $procmux$359_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$true B[1]=$false B[2]=$true B[3]=$false B[4]=$true B[5]=$true B[6]=$false Y=$procmux$360_CMP
|
||
|
|
.cname $procmux$360_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$false B[1]=$false B[2]=$true B[3]=$false B[4]=$true B[5]=$true B[6]=$false Y=$procmux$361_CMP
|
||
|
|
.cname $procmux$361_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$true B[1]=$true B[2]=$false B[3]=$false B[4]=$true B[5]=$true B[6]=$false Y=$procmux$362_CMP
|
||
|
|
.cname $procmux$362_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$false B[1]=$true B[2]=$false B[3]=$false B[4]=$true B[5]=$true B[6]=$false Y=$procmux$363_CMP
|
||
|
|
.cname $procmux$363_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$true B[1]=$false B[2]=$false B[3]=$false B[4]=$true B[5]=$true B[6]=$false Y=$procmux$364_CMP
|
||
|
|
.cname $procmux$364_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$false B[1]=$false B[2]=$false B[3]=$false B[4]=$true B[5]=$true B[6]=$false Y=$procmux$365_CMP
|
||
|
|
.cname $procmux$365_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$true B[1]=$true B[2]=$true B[3]=$true B[4]=$false B[5]=$true B[6]=$false Y=$procmux$366_CMP
|
||
|
|
.cname $procmux$366_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$false B[1]=$true B[2]=$true B[3]=$true B[4]=$false B[5]=$true B[6]=$false Y=$procmux$367_CMP
|
||
|
|
.cname $procmux$367_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$true B[1]=$false B[2]=$true B[3]=$true B[4]=$false B[5]=$true B[6]=$false Y=$procmux$368_CMP
|
||
|
|
.cname $procmux$368_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$false B[1]=$false B[2]=$true B[3]=$true B[4]=$false B[5]=$true B[6]=$false Y=$procmux$369_CMP
|
||
|
|
.cname $procmux$369_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$true B[1]=$true B[2]=$false B[3]=$true B[4]=$false B[5]=$true B[6]=$false Y=$procmux$370_CMP
|
||
|
|
.cname $procmux$370_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$false B[1]=$true B[2]=$false B[3]=$true B[4]=$false B[5]=$true B[6]=$false Y=$procmux$371_CMP
|
||
|
|
.cname $procmux$371_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$true B[1]=$false B[2]=$false B[3]=$true B[4]=$false B[5]=$true B[6]=$false Y=$procmux$372_CMP
|
||
|
|
.cname $procmux$372_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$false B[1]=$false B[2]=$false B[3]=$true B[4]=$false B[5]=$true B[6]=$false Y=$procmux$373_CMP
|
||
|
|
.cname $procmux$373_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$true B[1]=$true B[2]=$true B[3]=$false B[4]=$false B[5]=$true B[6]=$false Y=$procmux$374_CMP
|
||
|
|
.cname $procmux$374_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$false B[1]=$true B[2]=$true B[3]=$false B[4]=$false B[5]=$true B[6]=$false Y=$procmux$375_CMP
|
||
|
|
.cname $procmux$375_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$true B[1]=$false B[2]=$true B[3]=$false B[4]=$false B[5]=$true B[6]=$false Y=$procmux$376_CMP
|
||
|
|
.cname $procmux$376_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$false B[1]=$false B[2]=$true B[3]=$false B[4]=$false B[5]=$true B[6]=$false Y=$procmux$377_CMP
|
||
|
|
.cname $procmux$377_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$true B[1]=$true B[2]=$false B[3]=$false B[4]=$false B[5]=$true B[6]=$false Y=$procmux$378_CMP
|
||
|
|
.cname $procmux$378_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$false B[1]=$true B[2]=$false B[3]=$false B[4]=$false B[5]=$true B[6]=$false Y=$procmux$379_CMP
|
||
|
|
.cname $procmux$379_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$true B[1]=$false B[2]=$false B[3]=$false B[4]=$false B[5]=$true B[6]=$false Y=$procmux$380_CMP
|
||
|
|
.cname $procmux$380_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$false B[1]=$false B[2]=$false B[3]=$false B[4]=$false B[5]=$true B[6]=$false Y=$procmux$381_CMP
|
||
|
|
.cname $procmux$381_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$true B[1]=$true B[2]=$true B[3]=$true B[4]=$true B[5]=$false B[6]=$false Y=$procmux$382_CMP
|
||
|
|
.cname $procmux$382_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$false B[1]=$true B[2]=$true B[3]=$true B[4]=$true B[5]=$false B[6]=$false Y=$procmux$383_CMP
|
||
|
|
.cname $procmux$383_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$true B[1]=$false B[2]=$true B[3]=$true B[4]=$true B[5]=$false B[6]=$false Y=$procmux$384_CMP
|
||
|
|
.cname $procmux$384_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$false B[1]=$false B[2]=$true B[3]=$true B[4]=$true B[5]=$false B[6]=$false Y=$procmux$385_CMP
|
||
|
|
.cname $procmux$385_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$true B[1]=$true B[2]=$false B[3]=$true B[4]=$true B[5]=$false B[6]=$false Y=$procmux$386_CMP
|
||
|
|
.cname $procmux$386_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$false B[1]=$true B[2]=$false B[3]=$true B[4]=$true B[5]=$false B[6]=$false Y=$procmux$387_CMP
|
||
|
|
.cname $procmux$387_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$true B[1]=$false B[2]=$false B[3]=$true B[4]=$true B[5]=$false B[6]=$false Y=$procmux$388_CMP
|
||
|
|
.cname $procmux$388_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$false B[1]=$false B[2]=$false B[3]=$true B[4]=$true B[5]=$false B[6]=$false Y=$procmux$389_CMP
|
||
|
|
.cname $procmux$389_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$true B[1]=$true B[2]=$true B[3]=$false B[4]=$true B[5]=$false B[6]=$false Y=$procmux$390_CMP
|
||
|
|
.cname $procmux$390_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$false B[1]=$true B[2]=$true B[3]=$false B[4]=$true B[5]=$false B[6]=$false Y=$procmux$391_CMP
|
||
|
|
.cname $procmux$391_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$true B[1]=$false B[2]=$true B[3]=$false B[4]=$true B[5]=$false B[6]=$false Y=$procmux$392_CMP
|
||
|
|
.cname $procmux$392_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$false B[1]=$false B[2]=$true B[3]=$false B[4]=$true B[5]=$false B[6]=$false Y=$procmux$393_CMP
|
||
|
|
.cname $procmux$393_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$true B[1]=$true B[2]=$false B[3]=$false B[4]=$true B[5]=$false B[6]=$false Y=$procmux$394_CMP
|
||
|
|
.cname $procmux$394_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$false B[1]=$true B[2]=$false B[3]=$false B[4]=$true B[5]=$false B[6]=$false Y=$procmux$395_CMP
|
||
|
|
.cname $procmux$395_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$true B[1]=$false B[2]=$false B[3]=$false B[4]=$true B[5]=$false B[6]=$false Y=$procmux$396_CMP
|
||
|
|
.cname $procmux$396_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$false B[1]=$false B[2]=$false B[3]=$false B[4]=$true B[5]=$false B[6]=$false Y=$procmux$397_CMP
|
||
|
|
.cname $procmux$397_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$true B[1]=$false B[2]=$true B[3]=$true B[4]=$false B[5]=$false B[6]=$false Y=$procmux$398_CMP
|
||
|
|
.cname $procmux$398_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $mux A[0]=$procmux$333_Y[0] A[1]=$procmux$333_Y[1] A[2]=$procmux$333_Y[2] A[3]=$procmux$333_Y[3] A[4]=$procmux$333_Y[4] A[5]=$procmux$333_Y[5] A[6]=$procmux$333_Y[6] A[7]=$procmux$333_Y[7] A[8]=$procmux$333_Y[8] A[9]=$procmux$333_Y[9] A[10]=$procmux$333_Y[10] A[11]=$procmux$333_Y[11] A[12]=$procmux$333_Y[12] A[13]=$procmux$333_Y[13] A[14]=$procmux$333_Y[14] A[15]=$procmux$333_Y[15] A[16]=$procmux$333_Y[16] A[17]=$procmux$333_Y[17] A[18]=$procmux$333_Y[18] A[19]=$procmux$333_Y[19] A[20]=$procmux$333_Y[20] A[21]=$procmux$333_Y[21] A[22]=$procmux$333_Y[22] A[23]=$procmux$333_Y[23] A[24]=$procmux$333_Y[24] A[25]=$procmux$333_Y[25] A[26]=$procmux$333_Y[26] A[27]=$procmux$333_Y[27] A[28]=$procmux$333_Y[28] A[29]=$procmux$333_Y[29] A[30]=$procmux$333_Y[30] A[31]=$procmux$333_Y[31] B[0]=$false B[1]=$false B[2]=$false B[3]=$false B[4]=$false B[5]=$false B[6]=$false B[7]=$false B[8]=$false B[9]=$false B[10]=$false B[11]=$false B[12]=$false B[13]=$false B[14]=$false B[15]=$false B[16]=$false B[17]=$false B[18]=$false B[19]=$false B[20]=$false B[21]=$false B[22]=$false B[23]=$false B[24]=$false B[25]=$false B[26]=$false B[27]=$false B[28]=$false B[29]=$false B[30]=$false B[31]=$false S=$procmux$401_CMP Y[0]=$procmux$400_Y[0] Y[1]=$procmux$400_Y[1] Y[2]=$procmux$400_Y[2] Y[3]=$procmux$400_Y[3] Y[4]=$procmux$400_Y[4] Y[5]=$procmux$400_Y[5] Y[6]=$procmux$400_Y[6] Y[7]=$procmux$400_Y[7] Y[8]=$procmux$400_Y[8] Y[9]=$procmux$400_Y[9] Y[10]=$procmux$400_Y[10] Y[11]=$procmux$400_Y[11] Y[12]=$procmux$400_Y[12] Y[13]=$procmux$400_Y[13] Y[14]=$procmux$400_Y[14] Y[15]=$procmux$400_Y[15] Y[16]=$procmux$400_Y[16] Y[17]=$procmux$400_Y[17] Y[18]=$procmux$400_Y[18] Y[19]=$procmux$400_Y[19] Y[20]=$procmux$400_Y[20] Y[21]=$procmux$400_Y[21] Y[22]=$procmux$400_Y[22] Y[23]=$procmux$400_Y[23] Y[24]=$procmux$400_Y[24] Y[25]=$procmux$400_Y[25] Y[26]=$procmux$400_Y[26] Y[27]=$procmux$400_Y[27] Y[28]=$procmux$400_Y[28] Y[29]=$procmux$400_Y[29] Y[30]=$procmux$400_Y[30] Y[31]=$procmux$400_Y[31]
|
||
|
|
.cname $procmux$400
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:150"
|
||
|
|
.param WIDTH 00000000000000000000000000100000
|
||
|
|
.subckt $pmux A[0]=W12[0] A[1]=W12[1] A[2]=W12[2] A[3]=W12[3] A[4]=W12[4] A[5]=W12[5] A[6]=W12[6] A[7]=W12[7] A[8]=W12[8] A[9]=W12[9] A[10]=W12[10] A[11]=W12[11] A[12]=W12[12] A[13]=W12[13] A[14]=W12[14] A[15]=W12[15] A[16]=W12[16] A[17]=W12[17] A[18]=W12[18] A[19]=W12[19] A[20]=W12[20] A[21]=W12[21] A[22]=W12[22] A[23]=W12[23] A[24]=W12[24] A[25]=W12[25] A[26]=W12[26] A[27]=W12[27] A[28]=W12[28] A[29]=W12[29] A[30]=W12[30] A[31]=W12[31] B[0]=W13[0] B[1]=W13[1] B[2]=W13[2] B[3]=W13[3] B[4]=W13[4] B[5]=W13[5] B[6]=W13[6] B[7]=W13[7] B[8]=W13[8] B[9]=W13[9] B[10]=W13[10] B[11]=W13[11] B[12]=W13[12] B[13]=W13[13] B[14]=W13[14] B[15]=W13[15] B[16]=W13[16] B[17]=W13[17] B[18]=W13[18] B[19]=W13[19] B[20]=W13[20] B[21]=W13[21] B[22]=W13[22] B[23]=W13[23] B[24]=W13[24] B[25]=W13[25] B[26]=W13[26] B[27]=W13[27] B[28]=W13[28] B[29]=W13[29] B[30]=W13[30] B[31]=W13[31] B[32]=W13[0] B[33]=W13[1] B[34]=W13[2] B[35]=W13[3] B[36]=W13[4] B[37]=W13[5] B[38]=W13[6] B[39]=W13[7] B[40]=W13[8] B[41]=W13[9] B[42]=W13[10] B[43]=W13[11] B[44]=W13[12] B[45]=W13[13] B[46]=W13[14] B[47]=W13[15] B[48]=W13[16] B[49]=W13[17] B[50]=W13[18] B[51]=W13[19] B[52]=W13[20] B[53]=W13[21] B[54]=W13[22] B[55]=W13[23] B[56]=W13[24] B[57]=W13[25] B[58]=W13[26] B[59]=W13[27] B[60]=W13[28] B[61]=W13[29] B[62]=W13[30] B[63]=W13[31] B[64]=W13[0] B[65]=W13[1] B[66]=W13[2] B[67]=W13[3] B[68]=W13[4] B[69]=W13[5] B[70]=W13[6] B[71]=W13[7] B[72]=W13[8] B[73]=W13[9] B[74]=W13[10] B[75]=W13[11] B[76]=W13[12] B[77]=W13[13] B[78]=W13[14] B[79]=W13[15] B[80]=W13[16] B[81]=W13[17] B[82]=W13[18] B[83]=W13[19] B[84]=W13[20] B[85]=W13[21] B[86]=W13[22] B[87]=W13[23] B[88]=W13[24] B[89]=W13[25] B[90]=W13[26] B[91]=W13[27] B[92]=W13[28] B[93]=W13[29] B[94]=W13[30] B[95]=W13[31] B[96]=W13[0] B[97]=W13[1] B[98]=W13[2] B[99]=W13[3] B[100]=W13[4] B[101]=W13[5] B[102]=W13[6] B[103]=W13[7] B[104]=W13[8] B[105]=W13[9] B[106]=W13[10] B[107]=W13[11] B[108]=W13[12] B[109]=W13[13] B[110]=W13[14] B[111]=W13[15] B[112]=W13[16] B[113]=W13[17] B[114]=W13[18] B[115]=W13[19] B[116]=W13[20] B[117]=W13[21] B[118]=W13[22] B[119]=W13[23] B[120]=W13[24] B[121]=W13[25] B[122]=W13[26] B[123]=W13[27] B[124]=W13[28] B[125]=W13[29] B[126]=W13[30] B[127]=W13[31] B[128]=W13[0] B[129]=W13[1] B[130]=W13[2] B[131]=W13[3] B[132]=W13[4] B[133]=W13[5] B[134]=W13[6] B[135]=W13[7] B[136]=W13[8] B[137]=W13[9] B[138]=W13[10] B[139]=W13[11] B[140]=W13[12] B[141]=W13[13] B[142]=W13[14] B[143]=W13[15] B[144]=W13[16] B[145]=W13[17] B[146]=W13[18] B[147]=W13[19] B[148]=W13[20] B[149]=W13[21] B[150]=W13[22] B[151]=W13[23] B[152]=W13[24] B[153]=W13[25] B[154]=W13[26] B[155]=W13[27] B[156]=W13[28] B[157]=W13[29] B[158]=W13[30] B[159]=W13[31] B[160]=W13[0] B[161]=W13[1] B[162]=W13[2] B[163]=W13[3] B[164]=W13[4] B[165]=W13[5] B[166]=W13[6] B[167]=W13[7] B[168]=W13[8] B[169]=W13[9] B[170]=W13[10] B[171]=W13[11] B[172]=W13[12] B[173]=W13[13] B[174]=W13[14] B[175]=W13[15] B[176]=W13[16] B[177]=W13[17] B[178]=W13[18] B[179]=W13[19] B[180]=W13[20] B[181]=W13[21] B[182]=W13[22] B[183]=W13[23] B[184]=W13[24] B[185]=W13[25] B[186]=W13[26] B[187]=W13[27] B[188]=W13[28] B[189]=W13[29] B[190]=W13[30] B[191]=W13[31] B[192]=W13[0] B[193]=W13[1] B[194]=W13[2] B[195]=W13[3] B[196]=W13[4] B[197]=W13[5] B[198]=W13[6] B[199]=W13[7] B[200]=W13[8] B[201]=W13[9] B[202]=W13[10] B[203]=W13[11] B[204]=W13[12] B[205]=W13[13] B[206]=W13[14] B[207]=W13[15] B[208]=W13[16] B[209]=W13[17] B[210]=W13[18] B[211]=W13[19] B[212]=W13[20] B[213]=W13[21] B[214]=W13[22] B[215]=W13[23] B[216]=W13[24] B[217]=W13[25] B[218]=W13[26] B[219]=W13[27] B[220]=W13[28] B[221]=W13[29] B[222]=W13[30] B[223]=W13[31] B[224]=W13[0] B[225]=W13[1] B[226]=W13[2] B[227]=W13[3] B[228]=W13[4] B[229]=W13[5] B[230]=W13[6] B[231]=W13[7] B[232]=W13[8] B[233]=W13[9] B[234]=W13[10] B[235]=W13[11] B[236]=W13[12] B[237]=W13[13] B[238]=W13[14] B[239]=W13[15] B[240]=W13[16] B[241]=W13[17] B[242]=W13[18] B[243]=W13[19] B[244]=W13[20] B[245]=W13[21] B[246]=W13[22] B[247]=W13[23] B[248]=W13[24] B[249]=W13[25] B[250]=W13[26] B[251]=W13[27] B[252]=W13[28] B[253]=W13[29] B[254]=W13[30] B[255]=W13[31] B[2
|
||
|
|
.cname $procmux$404
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param S_WIDTH 00000000000000000000000001000001
|
||
|
|
.param WIDTH 00000000000000000000000000100000
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$true B[1]=$true B[2]=$true B[3]=$true B[4]=$false B[5]=$false B[6]=$true Y=$procmux$405_CMP
|
||
|
|
.cname $procmux$405_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$false B[1]=$true B[2]=$true B[3]=$true B[4]=$false B[5]=$false B[6]=$true Y=$procmux$406_CMP
|
||
|
|
.cname $procmux$406_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$true B[1]=$false B[2]=$true B[3]=$true B[4]=$false B[5]=$false B[6]=$true Y=$procmux$407_CMP
|
||
|
|
.cname $procmux$407_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$false B[1]=$false B[2]=$true B[3]=$true B[4]=$false B[5]=$false B[6]=$true Y=$procmux$408_CMP
|
||
|
|
.cname $procmux$408_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$true B[1]=$true B[2]=$false B[3]=$true B[4]=$false B[5]=$false B[6]=$true Y=$procmux$409_CMP
|
||
|
|
.cname $procmux$409_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$false B[1]=$true B[2]=$false B[3]=$true B[4]=$false B[5]=$false B[6]=$true Y=$procmux$410_CMP
|
||
|
|
.cname $procmux$410_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$true B[1]=$false B[2]=$false B[3]=$true B[4]=$false B[5]=$false B[6]=$true Y=$procmux$411_CMP
|
||
|
|
.cname $procmux$411_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$false B[1]=$false B[2]=$false B[3]=$true B[4]=$false B[5]=$false B[6]=$true Y=$procmux$412_CMP
|
||
|
|
.cname $procmux$412_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$true B[1]=$true B[2]=$true B[3]=$false B[4]=$false B[5]=$false B[6]=$true Y=$procmux$413_CMP
|
||
|
|
.cname $procmux$413_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$false B[1]=$true B[2]=$true B[3]=$false B[4]=$false B[5]=$false B[6]=$true Y=$procmux$414_CMP
|
||
|
|
.cname $procmux$414_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$true B[1]=$false B[2]=$true B[3]=$false B[4]=$false B[5]=$false B[6]=$true Y=$procmux$415_CMP
|
||
|
|
.cname $procmux$415_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$false B[1]=$false B[2]=$true B[3]=$false B[4]=$false B[5]=$false B[6]=$true Y=$procmux$416_CMP
|
||
|
|
.cname $procmux$416_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$true B[1]=$true B[2]=$false B[3]=$false B[4]=$false B[5]=$false B[6]=$true Y=$procmux$417_CMP
|
||
|
|
.cname $procmux$417_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$false B[1]=$true B[2]=$false B[3]=$false B[4]=$false B[5]=$false B[6]=$true Y=$procmux$418_CMP
|
||
|
|
.cname $procmux$418_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$true B[1]=$false B[2]=$false B[3]=$false B[4]=$false B[5]=$false B[6]=$true Y=$procmux$419_CMP
|
||
|
|
.cname $procmux$419_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$false B[1]=$false B[2]=$false B[3]=$false B[4]=$false B[5]=$false B[6]=$true Y=$procmux$420_CMP
|
||
|
|
.cname $procmux$420_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$true B[1]=$true B[2]=$true B[3]=$true B[4]=$true B[5]=$true B[6]=$false Y=$procmux$421_CMP
|
||
|
|
.cname $procmux$421_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$false B[1]=$true B[2]=$true B[3]=$true B[4]=$true B[5]=$true B[6]=$false Y=$procmux$422_CMP
|
||
|
|
.cname $procmux$422_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$true B[1]=$false B[2]=$true B[3]=$true B[4]=$true B[5]=$true B[6]=$false Y=$procmux$423_CMP
|
||
|
|
.cname $procmux$423_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$false B[1]=$false B[2]=$true B[3]=$true B[4]=$true B[5]=$true B[6]=$false Y=$procmux$424_CMP
|
||
|
|
.cname $procmux$424_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$true B[1]=$true B[2]=$false B[3]=$true B[4]=$true B[5]=$true B[6]=$false Y=$procmux$425_CMP
|
||
|
|
.cname $procmux$425_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$false B[1]=$true B[2]=$false B[3]=$true B[4]=$true B[5]=$true B[6]=$false Y=$procmux$426_CMP
|
||
|
|
.cname $procmux$426_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$true B[1]=$false B[2]=$false B[3]=$true B[4]=$true B[5]=$true B[6]=$false Y=$procmux$427_CMP
|
||
|
|
.cname $procmux$427_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$false B[1]=$false B[2]=$false B[3]=$true B[4]=$true B[5]=$true B[6]=$false Y=$procmux$428_CMP
|
||
|
|
.cname $procmux$428_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$true B[1]=$true B[2]=$true B[3]=$false B[4]=$true B[5]=$true B[6]=$false Y=$procmux$429_CMP
|
||
|
|
.cname $procmux$429_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$false B[1]=$true B[2]=$true B[3]=$false B[4]=$true B[5]=$true B[6]=$false Y=$procmux$430_CMP
|
||
|
|
.cname $procmux$430_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$true B[1]=$false B[2]=$true B[3]=$false B[4]=$true B[5]=$true B[6]=$false Y=$procmux$431_CMP
|
||
|
|
.cname $procmux$431_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$false B[1]=$false B[2]=$true B[3]=$false B[4]=$true B[5]=$true B[6]=$false Y=$procmux$432_CMP
|
||
|
|
.cname $procmux$432_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$true B[1]=$true B[2]=$false B[3]=$false B[4]=$true B[5]=$true B[6]=$false Y=$procmux$433_CMP
|
||
|
|
.cname $procmux$433_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$false B[1]=$true B[2]=$false B[3]=$false B[4]=$true B[5]=$true B[6]=$false Y=$procmux$434_CMP
|
||
|
|
.cname $procmux$434_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$true B[1]=$false B[2]=$false B[3]=$false B[4]=$true B[5]=$true B[6]=$false Y=$procmux$435_CMP
|
||
|
|
.cname $procmux$435_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$false B[1]=$false B[2]=$false B[3]=$false B[4]=$true B[5]=$true B[6]=$false Y=$procmux$436_CMP
|
||
|
|
.cname $procmux$436_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$true B[1]=$true B[2]=$true B[3]=$true B[4]=$false B[5]=$true B[6]=$false Y=$procmux$437_CMP
|
||
|
|
.cname $procmux$437_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$false B[1]=$true B[2]=$true B[3]=$true B[4]=$false B[5]=$true B[6]=$false Y=$procmux$438_CMP
|
||
|
|
.cname $procmux$438_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$true B[1]=$false B[2]=$true B[3]=$true B[4]=$false B[5]=$true B[6]=$false Y=$procmux$439_CMP
|
||
|
|
.cname $procmux$439_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $mux A[0]=read_counter[0] A[1]=read_counter[1] A[2]=read_counter[2] B[0]=$sub$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:2160$41_Y[0] B[1]=$sub$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:2160$41_Y[1] B[2]=$sub$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:2160$41_Y[2] S=$procmux$45_CMP Y[0]=$procmux$44_Y[0] Y[1]=$procmux$44_Y[1] Y[2]=$procmux$44_Y[2]
|
||
|
|
.cname $procmux$44
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:2159"
|
||
|
|
.param WIDTH 00000000000000000000000000000011
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$false B[1]=$false B[2]=$true B[3]=$true B[4]=$false B[5]=$true B[6]=$false Y=$procmux$440_CMP
|
||
|
|
.cname $procmux$440_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$true B[1]=$true B[2]=$false B[3]=$true B[4]=$false B[5]=$true B[6]=$false Y=$procmux$441_CMP
|
||
|
|
.cname $procmux$441_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$false B[1]=$true B[2]=$false B[3]=$true B[4]=$false B[5]=$true B[6]=$false Y=$procmux$442_CMP
|
||
|
|
.cname $procmux$442_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$true B[1]=$false B[2]=$false B[3]=$true B[4]=$false B[5]=$true B[6]=$false Y=$procmux$443_CMP
|
||
|
|
.cname $procmux$443_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$false B[1]=$false B[2]=$false B[3]=$true B[4]=$false B[5]=$true B[6]=$false Y=$procmux$444_CMP
|
||
|
|
.cname $procmux$444_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$true B[1]=$true B[2]=$true B[3]=$false B[4]=$false B[5]=$true B[6]=$false Y=$procmux$445_CMP
|
||
|
|
.cname $procmux$445_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$false B[1]=$true B[2]=$true B[3]=$false B[4]=$false B[5]=$true B[6]=$false Y=$procmux$446_CMP
|
||
|
|
.cname $procmux$446_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$true B[1]=$false B[2]=$true B[3]=$false B[4]=$false B[5]=$true B[6]=$false Y=$procmux$447_CMP
|
||
|
|
.cname $procmux$447_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$false B[1]=$false B[2]=$true B[3]=$false B[4]=$false B[5]=$true B[6]=$false Y=$procmux$448_CMP
|
||
|
|
.cname $procmux$448_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$true B[1]=$true B[2]=$false B[3]=$false B[4]=$false B[5]=$true B[6]=$false Y=$procmux$449_CMP
|
||
|
|
.cname $procmux$449_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$false B[1]=$true B[2]=$false B[3]=$false B[4]=$false B[5]=$true B[6]=$false Y=$procmux$450_CMP
|
||
|
|
.cname $procmux$450_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$true B[1]=$false B[2]=$false B[3]=$false B[4]=$false B[5]=$true B[6]=$false Y=$procmux$451_CMP
|
||
|
|
.cname $procmux$451_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$false B[1]=$false B[2]=$false B[3]=$false B[4]=$false B[5]=$true B[6]=$false Y=$procmux$452_CMP
|
||
|
|
.cname $procmux$452_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$true B[1]=$true B[2]=$true B[3]=$true B[4]=$true B[5]=$false B[6]=$false Y=$procmux$453_CMP
|
||
|
|
.cname $procmux$453_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$false B[1]=$true B[2]=$true B[3]=$true B[4]=$true B[5]=$false B[6]=$false Y=$procmux$454_CMP
|
||
|
|
.cname $procmux$454_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$true B[1]=$false B[2]=$true B[3]=$true B[4]=$true B[5]=$false B[6]=$false Y=$procmux$455_CMP
|
||
|
|
.cname $procmux$455_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$false B[1]=$false B[2]=$true B[3]=$true B[4]=$true B[5]=$false B[6]=$false Y=$procmux$456_CMP
|
||
|
|
.cname $procmux$456_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$true B[1]=$true B[2]=$false B[3]=$true B[4]=$true B[5]=$false B[6]=$false Y=$procmux$457_CMP
|
||
|
|
.cname $procmux$457_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$false B[1]=$true B[2]=$false B[3]=$true B[4]=$true B[5]=$false B[6]=$false Y=$procmux$458_CMP
|
||
|
|
.cname $procmux$458_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$true B[1]=$false B[2]=$false B[3]=$true B[4]=$true B[5]=$false B[6]=$false Y=$procmux$459_CMP
|
||
|
|
.cname $procmux$459_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $mux A[0]=read_counter[0] A[1]=read_counter[1] A[2]=read_counter[2] B[0]=$procmux$44_Y[0] B[1]=$procmux$44_Y[1] B[2]=$procmux$44_Y[2] S=$procmux$47_CMP Y[0]=$procmux$46_Y[0] Y[1]=$procmux$46_Y[1] Y[2]=$procmux$46_Y[2]
|
||
|
|
.cname $procmux$46
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:2149"
|
||
|
|
.param WIDTH 00000000000000000000000000000011
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$false B[1]=$false B[2]=$false B[3]=$true B[4]=$true B[5]=$false B[6]=$false Y=$procmux$460_CMP
|
||
|
|
.cname $procmux$460_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$true B[1]=$true B[2]=$true B[3]=$false B[4]=$true B[5]=$false B[6]=$false Y=$procmux$461_CMP
|
||
|
|
.cname $procmux$461_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$false B[1]=$true B[2]=$true B[3]=$false B[4]=$true B[5]=$false B[6]=$false Y=$procmux$462_CMP
|
||
|
|
.cname $procmux$462_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$true B[1]=$false B[2]=$true B[3]=$false B[4]=$true B[5]=$false B[6]=$false Y=$procmux$463_CMP
|
||
|
|
.cname $procmux$463_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$false B[1]=$false B[2]=$true B[3]=$false B[4]=$true B[5]=$false B[6]=$false Y=$procmux$464_CMP
|
||
|
|
.cname $procmux$464_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$true B[1]=$true B[2]=$false B[3]=$false B[4]=$true B[5]=$false B[6]=$false Y=$procmux$465_CMP
|
||
|
|
.cname $procmux$465_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$false B[1]=$true B[2]=$false B[3]=$false B[4]=$true B[5]=$false B[6]=$false Y=$procmux$466_CMP
|
||
|
|
.cname $procmux$466_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$true B[1]=$false B[2]=$false B[3]=$false B[4]=$true B[5]=$false B[6]=$false Y=$procmux$467_CMP
|
||
|
|
.cname $procmux$467_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$false B[1]=$false B[2]=$false B[3]=$false B[4]=$true B[5]=$false B[6]=$false Y=$procmux$468_CMP
|
||
|
|
.cname $procmux$468_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$false B[1]=$false B[2]=$true B[3]=$true B[4]=$false B[5]=$false B[6]=$false Y=$procmux$469_CMP
|
||
|
|
.cname $procmux$469_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $mux A[0]=$procmux$404_Y[0] A[1]=$procmux$404_Y[1] A[2]=$procmux$404_Y[2] A[3]=$procmux$404_Y[3] A[4]=$procmux$404_Y[4] A[5]=$procmux$404_Y[5] A[6]=$procmux$404_Y[6] A[7]=$procmux$404_Y[7] A[8]=$procmux$404_Y[8] A[9]=$procmux$404_Y[9] A[10]=$procmux$404_Y[10] A[11]=$procmux$404_Y[11] A[12]=$procmux$404_Y[12] A[13]=$procmux$404_Y[13] A[14]=$procmux$404_Y[14] A[15]=$procmux$404_Y[15] A[16]=$procmux$404_Y[16] A[17]=$procmux$404_Y[17] A[18]=$procmux$404_Y[18] A[19]=$procmux$404_Y[19] A[20]=$procmux$404_Y[20] A[21]=$procmux$404_Y[21] A[22]=$procmux$404_Y[22] A[23]=$procmux$404_Y[23] A[24]=$procmux$404_Y[24] A[25]=$procmux$404_Y[25] A[26]=$procmux$404_Y[26] A[27]=$procmux$404_Y[27] A[28]=$procmux$404_Y[28] A[29]=$procmux$404_Y[29] A[30]=$procmux$404_Y[30] A[31]=$procmux$404_Y[31] B[0]=$false B[1]=$false B[2]=$false B[3]=$false B[4]=$false B[5]=$false B[6]=$false B[7]=$false B[8]=$false B[9]=$false B[10]=$false B[11]=$false B[12]=$false B[13]=$false B[14]=$false B[15]=$false B[16]=$false B[17]=$false B[18]=$false B[19]=$false B[20]=$false B[21]=$false B[22]=$false B[23]=$false B[24]=$false B[25]=$false B[26]=$false B[27]=$false B[28]=$false B[29]=$false B[30]=$false B[31]=$false S=$procmux$472_CMP Y[0]=$procmux$471_Y[0] Y[1]=$procmux$471_Y[1] Y[2]=$procmux$471_Y[2] Y[3]=$procmux$471_Y[3] Y[4]=$procmux$471_Y[4] Y[5]=$procmux$471_Y[5] Y[6]=$procmux$471_Y[6] Y[7]=$procmux$471_Y[7] Y[8]=$procmux$471_Y[8] Y[9]=$procmux$471_Y[9] Y[10]=$procmux$471_Y[10] Y[11]=$procmux$471_Y[11] Y[12]=$procmux$471_Y[12] Y[13]=$procmux$471_Y[13] Y[14]=$procmux$471_Y[14] Y[15]=$procmux$471_Y[15] Y[16]=$procmux$471_Y[16] Y[17]=$procmux$471_Y[17] Y[18]=$procmux$471_Y[18] Y[19]=$procmux$471_Y[19] Y[20]=$procmux$471_Y[20] Y[21]=$procmux$471_Y[21] Y[22]=$procmux$471_Y[22] Y[23]=$procmux$471_Y[23] Y[24]=$procmux$471_Y[24] Y[25]=$procmux$471_Y[25] Y[26]=$procmux$471_Y[26] Y[27]=$procmux$471_Y[27] Y[28]=$procmux$471_Y[28] Y[29]=$procmux$471_Y[29] Y[30]=$procmux$471_Y[30] Y[31]=$procmux$471_Y[31]
|
||
|
|
.cname $procmux$471
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:150"
|
||
|
|
.param WIDTH 00000000000000000000000000100000
|
||
|
|
.subckt $pmux A[0]=W11[0] A[1]=W11[1] A[2]=W11[2] A[3]=W11[3] A[4]=W11[4] A[5]=W11[5] A[6]=W11[6] A[7]=W11[7] A[8]=W11[8] A[9]=W11[9] A[10]=W11[10] A[11]=W11[11] A[12]=W11[12] A[13]=W11[13] A[14]=W11[14] A[15]=W11[15] A[16]=W11[16] A[17]=W11[17] A[18]=W11[18] A[19]=W11[19] A[20]=W11[20] A[21]=W11[21] A[22]=W11[22] A[23]=W11[23] A[24]=W11[24] A[25]=W11[25] A[26]=W11[26] A[27]=W11[27] A[28]=W11[28] A[29]=W11[29] A[30]=W11[30] A[31]=W11[31] B[0]=W12[0] B[1]=W12[1] B[2]=W12[2] B[3]=W12[3] B[4]=W12[4] B[5]=W12[5] B[6]=W12[6] B[7]=W12[7] B[8]=W12[8] B[9]=W12[9] B[10]=W12[10] B[11]=W12[11] B[12]=W12[12] B[13]=W12[13] B[14]=W12[14] B[15]=W12[15] B[16]=W12[16] B[17]=W12[17] B[18]=W12[18] B[19]=W12[19] B[20]=W12[20] B[21]=W12[21] B[22]=W12[22] B[23]=W12[23] B[24]=W12[24] B[25]=W12[25] B[26]=W12[26] B[27]=W12[27] B[28]=W12[28] B[29]=W12[29] B[30]=W12[30] B[31]=W12[31] B[32]=W12[0] B[33]=W12[1] B[34]=W12[2] B[35]=W12[3] B[36]=W12[4] B[37]=W12[5] B[38]=W12[6] B[39]=W12[7] B[40]=W12[8] B[41]=W12[9] B[42]=W12[10] B[43]=W12[11] B[44]=W12[12] B[45]=W12[13] B[46]=W12[14] B[47]=W12[15] B[48]=W12[16] B[49]=W12[17] B[50]=W12[18] B[51]=W12[19] B[52]=W12[20] B[53]=W12[21] B[54]=W12[22] B[55]=W12[23] B[56]=W12[24] B[57]=W12[25] B[58]=W12[26] B[59]=W12[27] B[60]=W12[28] B[61]=W12[29] B[62]=W12[30] B[63]=W12[31] B[64]=W12[0] B[65]=W12[1] B[66]=W12[2] B[67]=W12[3] B[68]=W12[4] B[69]=W12[5] B[70]=W12[6] B[71]=W12[7] B[72]=W12[8] B[73]=W12[9] B[74]=W12[10] B[75]=W12[11] B[76]=W12[12] B[77]=W12[13] B[78]=W12[14] B[79]=W12[15] B[80]=W12[16] B[81]=W12[17] B[82]=W12[18] B[83]=W12[19] B[84]=W12[20] B[85]=W12[21] B[86]=W12[22] B[87]=W12[23] B[88]=W12[24] B[89]=W12[25] B[90]=W12[26] B[91]=W12[27] B[92]=W12[28] B[93]=W12[29] B[94]=W12[30] B[95]=W12[31] B[96]=W12[0] B[97]=W12[1] B[98]=W12[2] B[99]=W12[3] B[100]=W12[4] B[101]=W12[5] B[102]=W12[6] B[103]=W12[7] B[104]=W12[8] B[105]=W12[9] B[106]=W12[10] B[107]=W12[11] B[108]=W12[12] B[109]=W12[13] B[110]=W12[14] B[111]=W12[15] B[112]=W12[16] B[113]=W12[17] B[114]=W12[18] B[115]=W12[19] B[116]=W12[20] B[117]=W12[21] B[118]=W12[22] B[119]=W12[23] B[120]=W12[24] B[121]=W12[25] B[122]=W12[26] B[123]=W12[27] B[124]=W12[28] B[125]=W12[29] B[126]=W12[30] B[127]=W12[31] B[128]=W12[0] B[129]=W12[1] B[130]=W12[2] B[131]=W12[3] B[132]=W12[4] B[133]=W12[5] B[134]=W12[6] B[135]=W12[7] B[136]=W12[8] B[137]=W12[9] B[138]=W12[10] B[139]=W12[11] B[140]=W12[12] B[141]=W12[13] B[142]=W12[14] B[143]=W12[15] B[144]=W12[16] B[145]=W12[17] B[146]=W12[18] B[147]=W12[19] B[148]=W12[20] B[149]=W12[21] B[150]=W12[22] B[151]=W12[23] B[152]=W12[24] B[153]=W12[25] B[154]=W12[26] B[155]=W12[27] B[156]=W12[28] B[157]=W12[29] B[158]=W12[30] B[159]=W12[31] B[160]=W12[0] B[161]=W12[1] B[162]=W12[2] B[163]=W12[3] B[164]=W12[4] B[165]=W12[5] B[166]=W12[6] B[167]=W12[7] B[168]=W12[8] B[169]=W12[9] B[170]=W12[10] B[171]=W12[11] B[172]=W12[12] B[173]=W12[13] B[174]=W12[14] B[175]=W12[15] B[176]=W12[16] B[177]=W12[17] B[178]=W12[18] B[179]=W12[19] B[180]=W12[20] B[181]=W12[21] B[182]=W12[22] B[183]=W12[23] B[184]=W12[24] B[185]=W12[25] B[186]=W12[26] B[187]=W12[27] B[188]=W12[28] B[189]=W12[29] B[190]=W12[30] B[191]=W12[31] B[192]=W12[0] B[193]=W12[1] B[194]=W12[2] B[195]=W12[3] B[196]=W12[4] B[197]=W12[5] B[198]=W12[6] B[199]=W12[7] B[200]=W12[8] B[201]=W12[9] B[202]=W12[10] B[203]=W12[11] B[204]=W12[12] B[205]=W12[13] B[206]=W12[14] B[207]=W12[15] B[208]=W12[16] B[209]=W12[17] B[210]=W12[18] B[211]=W12[19] B[212]=W12[20] B[213]=W12[21] B[214]=W12[22] B[215]=W12[23] B[216]=W12[24] B[217]=W12[25] B[218]=W12[26] B[219]=W12[27] B[220]=W12[28] B[221]=W12[29] B[222]=W12[30] B[223]=W12[31] B[224]=W12[0] B[225]=W12[1] B[226]=W12[2] B[227]=W12[3] B[228]=W12[4] B[229]=W12[5] B[230]=W12[6] B[231]=W12[7] B[232]=W12[8] B[233]=W12[9] B[234]=W12[10] B[235]=W12[11] B[236]=W12[12] B[237]=W12[13] B[238]=W12[14] B[239]=W12[15] B[240]=W12[16] B[241]=W12[17] B[242]=W12[18] B[243]=W12[19] B[244]=W12[20] B[245]=W12[21] B[246]=W12[22] B[247]=W12[23] B[248]=W12[24] B[249]=W12[25] B[250]=W12[26] B[251]=W12[27] B[252]=W12[28] B[253]=W12[29] B[254]=W12[30] B[255]=W12[31] B[2
|
||
|
|
.cname $procmux$475
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param S_WIDTH 00000000000000000000000001000001
|
||
|
|
.param WIDTH 00000000000000000000000000100000
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$true B[1]=$true B[2]=$true B[3]=$true B[4]=$false B[5]=$false B[6]=$true Y=$procmux$476_CMP
|
||
|
|
.cname $procmux$476_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$false B[1]=$true B[2]=$true B[3]=$true B[4]=$false B[5]=$false B[6]=$true Y=$procmux$477_CMP
|
||
|
|
.cname $procmux$477_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$true B[1]=$false B[2]=$true B[3]=$true B[4]=$false B[5]=$false B[6]=$true Y=$procmux$478_CMP
|
||
|
|
.cname $procmux$478_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$false B[1]=$false B[2]=$true B[3]=$true B[4]=$false B[5]=$false B[6]=$true Y=$procmux$479_CMP
|
||
|
|
.cname $procmux$479_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$true B[1]=$true B[2]=$false B[3]=$true B[4]=$false B[5]=$false B[6]=$true Y=$procmux$480_CMP
|
||
|
|
.cname $procmux$480_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$false B[1]=$true B[2]=$false B[3]=$true B[4]=$false B[5]=$false B[6]=$true Y=$procmux$481_CMP
|
||
|
|
.cname $procmux$481_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$true B[1]=$false B[2]=$false B[3]=$true B[4]=$false B[5]=$false B[6]=$true Y=$procmux$482_CMP
|
||
|
|
.cname $procmux$482_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$false B[1]=$false B[2]=$false B[3]=$true B[4]=$false B[5]=$false B[6]=$true Y=$procmux$483_CMP
|
||
|
|
.cname $procmux$483_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$true B[1]=$true B[2]=$true B[3]=$false B[4]=$false B[5]=$false B[6]=$true Y=$procmux$484_CMP
|
||
|
|
.cname $procmux$484_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$false B[1]=$true B[2]=$true B[3]=$false B[4]=$false B[5]=$false B[6]=$true Y=$procmux$485_CMP
|
||
|
|
.cname $procmux$485_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$true B[1]=$false B[2]=$true B[3]=$false B[4]=$false B[5]=$false B[6]=$true Y=$procmux$486_CMP
|
||
|
|
.cname $procmux$486_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$false B[1]=$false B[2]=$true B[3]=$false B[4]=$false B[5]=$false B[6]=$true Y=$procmux$487_CMP
|
||
|
|
.cname $procmux$487_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$true B[1]=$true B[2]=$false B[3]=$false B[4]=$false B[5]=$false B[6]=$true Y=$procmux$488_CMP
|
||
|
|
.cname $procmux$488_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$false B[1]=$true B[2]=$false B[3]=$false B[4]=$false B[5]=$false B[6]=$true Y=$procmux$489_CMP
|
||
|
|
.cname $procmux$489_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $mux A[0]=$procmux$46_Y[0] A[1]=$procmux$46_Y[1] A[2]=$procmux$46_Y[2] B[0]=$false B[1]=$false B[2]=$true S=$procmux$50_CMP Y[0]=$procmux$49_Y[0] Y[1]=$procmux$49_Y[1] Y[2]=$procmux$49_Y[2]
|
||
|
|
.cname $procmux$49
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:2143"
|
||
|
|
.param WIDTH 00000000000000000000000000000011
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$true B[1]=$false B[2]=$false B[3]=$false B[4]=$false B[5]=$false B[6]=$true Y=$procmux$490_CMP
|
||
|
|
.cname $procmux$490_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$false B[1]=$false B[2]=$false B[3]=$false B[4]=$false B[5]=$false B[6]=$true Y=$procmux$491_CMP
|
||
|
|
.cname $procmux$491_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$true B[1]=$true B[2]=$true B[3]=$true B[4]=$true B[5]=$true B[6]=$false Y=$procmux$492_CMP
|
||
|
|
.cname $procmux$492_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$false B[1]=$true B[2]=$true B[3]=$true B[4]=$true B[5]=$true B[6]=$false Y=$procmux$493_CMP
|
||
|
|
.cname $procmux$493_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$true B[1]=$false B[2]=$true B[3]=$true B[4]=$true B[5]=$true B[6]=$false Y=$procmux$494_CMP
|
||
|
|
.cname $procmux$494_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$false B[1]=$false B[2]=$true B[3]=$true B[4]=$true B[5]=$true B[6]=$false Y=$procmux$495_CMP
|
||
|
|
.cname $procmux$495_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$true B[1]=$true B[2]=$false B[3]=$true B[4]=$true B[5]=$true B[6]=$false Y=$procmux$496_CMP
|
||
|
|
.cname $procmux$496_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$false B[1]=$true B[2]=$false B[3]=$true B[4]=$true B[5]=$true B[6]=$false Y=$procmux$497_CMP
|
||
|
|
.cname $procmux$497_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$true B[1]=$false B[2]=$false B[3]=$true B[4]=$true B[5]=$true B[6]=$false Y=$procmux$498_CMP
|
||
|
|
.cname $procmux$498_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$false B[1]=$false B[2]=$false B[3]=$true B[4]=$true B[5]=$true B[6]=$false Y=$procmux$499_CMP
|
||
|
|
.cname $procmux$499_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$true B[1]=$true B[2]=$true B[3]=$false B[4]=$true B[5]=$true B[6]=$false Y=$procmux$500_CMP
|
||
|
|
.cname $procmux$500_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$false B[1]=$true B[2]=$true B[3]=$false B[4]=$true B[5]=$true B[6]=$false Y=$procmux$501_CMP
|
||
|
|
.cname $procmux$501_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$true B[1]=$false B[2]=$true B[3]=$false B[4]=$true B[5]=$true B[6]=$false Y=$procmux$502_CMP
|
||
|
|
.cname $procmux$502_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$false B[1]=$false B[2]=$true B[3]=$false B[4]=$true B[5]=$true B[6]=$false Y=$procmux$503_CMP
|
||
|
|
.cname $procmux$503_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$true B[1]=$true B[2]=$false B[3]=$false B[4]=$true B[5]=$true B[6]=$false Y=$procmux$504_CMP
|
||
|
|
.cname $procmux$504_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$false B[1]=$true B[2]=$false B[3]=$false B[4]=$true B[5]=$true B[6]=$false Y=$procmux$505_CMP
|
||
|
|
.cname $procmux$505_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$true B[1]=$false B[2]=$false B[3]=$false B[4]=$true B[5]=$true B[6]=$false Y=$procmux$506_CMP
|
||
|
|
.cname $procmux$506_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$false B[1]=$false B[2]=$false B[3]=$false B[4]=$true B[5]=$true B[6]=$false Y=$procmux$507_CMP
|
||
|
|
.cname $procmux$507_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$true B[1]=$true B[2]=$true B[3]=$true B[4]=$false B[5]=$true B[6]=$false Y=$procmux$508_CMP
|
||
|
|
.cname $procmux$508_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$false B[1]=$true B[2]=$true B[3]=$true B[4]=$false B[5]=$true B[6]=$false Y=$procmux$509_CMP
|
||
|
|
.cname $procmux$509_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$true B[1]=$false B[2]=$true B[3]=$true B[4]=$false B[5]=$true B[6]=$false Y=$procmux$510_CMP
|
||
|
|
.cname $procmux$510_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$false B[1]=$false B[2]=$true B[3]=$true B[4]=$false B[5]=$true B[6]=$false Y=$procmux$511_CMP
|
||
|
|
.cname $procmux$511_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$true B[1]=$true B[2]=$false B[3]=$true B[4]=$false B[5]=$true B[6]=$false Y=$procmux$512_CMP
|
||
|
|
.cname $procmux$512_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$false B[1]=$true B[2]=$false B[3]=$true B[4]=$false B[5]=$true B[6]=$false Y=$procmux$513_CMP
|
||
|
|
.cname $procmux$513_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$true B[1]=$false B[2]=$false B[3]=$true B[4]=$false B[5]=$true B[6]=$false Y=$procmux$514_CMP
|
||
|
|
.cname $procmux$514_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$false B[1]=$false B[2]=$false B[3]=$true B[4]=$false B[5]=$true B[6]=$false Y=$procmux$515_CMP
|
||
|
|
.cname $procmux$515_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$true B[1]=$true B[2]=$true B[3]=$false B[4]=$false B[5]=$true B[6]=$false Y=$procmux$516_CMP
|
||
|
|
.cname $procmux$516_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$false B[1]=$true B[2]=$true B[3]=$false B[4]=$false B[5]=$true B[6]=$false Y=$procmux$517_CMP
|
||
|
|
.cname $procmux$517_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$true B[1]=$false B[2]=$true B[3]=$false B[4]=$false B[5]=$true B[6]=$false Y=$procmux$518_CMP
|
||
|
|
.cname $procmux$518_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$false B[1]=$false B[2]=$true B[3]=$false B[4]=$false B[5]=$true B[6]=$false Y=$procmux$519_CMP
|
||
|
|
.cname $procmux$519_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $mux A[0]=$procmux$49_Y[0] A[1]=$procmux$49_Y[1] A[2]=$procmux$49_Y[2] B[0]=$false B[1]=$false B[2]=$false S=$procmux$53_CMP Y[0]=$procmux$52_Y[0] Y[1]=$procmux$52_Y[1] Y[2]=$procmux$52_Y[2]
|
||
|
|
.cname $procmux$52
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:2136"
|
||
|
|
.param WIDTH 00000000000000000000000000000011
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$true B[1]=$true B[2]=$false B[3]=$false B[4]=$false B[5]=$true B[6]=$false Y=$procmux$520_CMP
|
||
|
|
.cname $procmux$520_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$false B[1]=$true B[2]=$false B[3]=$false B[4]=$false B[5]=$true B[6]=$false Y=$procmux$521_CMP
|
||
|
|
.cname $procmux$521_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$true B[1]=$false B[2]=$false B[3]=$false B[4]=$false B[5]=$true B[6]=$false Y=$procmux$522_CMP
|
||
|
|
.cname $procmux$522_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$false B[1]=$false B[2]=$false B[3]=$false B[4]=$false B[5]=$true B[6]=$false Y=$procmux$523_CMP
|
||
|
|
.cname $procmux$523_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$true B[1]=$true B[2]=$true B[3]=$true B[4]=$true B[5]=$false B[6]=$false Y=$procmux$524_CMP
|
||
|
|
.cname $procmux$524_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$false B[1]=$true B[2]=$true B[3]=$true B[4]=$true B[5]=$false B[6]=$false Y=$procmux$525_CMP
|
||
|
|
.cname $procmux$525_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$true B[1]=$false B[2]=$true B[3]=$true B[4]=$true B[5]=$false B[6]=$false Y=$procmux$526_CMP
|
||
|
|
.cname $procmux$526_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$false B[1]=$false B[2]=$true B[3]=$true B[4]=$true B[5]=$false B[6]=$false Y=$procmux$527_CMP
|
||
|
|
.cname $procmux$527_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$true B[1]=$true B[2]=$false B[3]=$true B[4]=$true B[5]=$false B[6]=$false Y=$procmux$528_CMP
|
||
|
|
.cname $procmux$528_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$false B[1]=$true B[2]=$false B[3]=$true B[4]=$true B[5]=$false B[6]=$false Y=$procmux$529_CMP
|
||
|
|
.cname $procmux$529_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$true B[1]=$false B[2]=$false B[3]=$true B[4]=$true B[5]=$false B[6]=$false Y=$procmux$530_CMP
|
||
|
|
.cname $procmux$530_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$false B[1]=$false B[2]=$false B[3]=$true B[4]=$true B[5]=$false B[6]=$false Y=$procmux$531_CMP
|
||
|
|
.cname $procmux$531_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$true B[1]=$true B[2]=$true B[3]=$false B[4]=$true B[5]=$false B[6]=$false Y=$procmux$532_CMP
|
||
|
|
.cname $procmux$532_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$false B[1]=$true B[2]=$true B[3]=$false B[4]=$true B[5]=$false B[6]=$false Y=$procmux$533_CMP
|
||
|
|
.cname $procmux$533_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$true B[1]=$false B[2]=$true B[3]=$false B[4]=$true B[5]=$false B[6]=$false Y=$procmux$534_CMP
|
||
|
|
.cname $procmux$534_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$false B[1]=$false B[2]=$true B[3]=$false B[4]=$true B[5]=$false B[6]=$false Y=$procmux$535_CMP
|
||
|
|
.cname $procmux$535_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$true B[1]=$true B[2]=$false B[3]=$false B[4]=$true B[5]=$false B[6]=$false Y=$procmux$536_CMP
|
||
|
|
.cname $procmux$536_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$false B[1]=$true B[2]=$false B[3]=$false B[4]=$true B[5]=$false B[6]=$false Y=$procmux$537_CMP
|
||
|
|
.cname $procmux$537_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$true B[1]=$false B[2]=$false B[3]=$false B[4]=$true B[5]=$false B[6]=$false Y=$procmux$538_CMP
|
||
|
|
.cname $procmux$538_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$false B[1]=$false B[2]=$false B[3]=$false B[4]=$true B[5]=$false B[6]=$false Y=$procmux$539_CMP
|
||
|
|
.cname $procmux$539_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$true B[1]=$true B[2]=$false B[3]=$true B[4]=$false B[5]=$false B[6]=$false Y=$procmux$540_CMP
|
||
|
|
.cname $procmux$540_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $mux A[0]=$procmux$475_Y[0] A[1]=$procmux$475_Y[1] A[2]=$procmux$475_Y[2] A[3]=$procmux$475_Y[3] A[4]=$procmux$475_Y[4] A[5]=$procmux$475_Y[5] A[6]=$procmux$475_Y[6] A[7]=$procmux$475_Y[7] A[8]=$procmux$475_Y[8] A[9]=$procmux$475_Y[9] A[10]=$procmux$475_Y[10] A[11]=$procmux$475_Y[11] A[12]=$procmux$475_Y[12] A[13]=$procmux$475_Y[13] A[14]=$procmux$475_Y[14] A[15]=$procmux$475_Y[15] A[16]=$procmux$475_Y[16] A[17]=$procmux$475_Y[17] A[18]=$procmux$475_Y[18] A[19]=$procmux$475_Y[19] A[20]=$procmux$475_Y[20] A[21]=$procmux$475_Y[21] A[22]=$procmux$475_Y[22] A[23]=$procmux$475_Y[23] A[24]=$procmux$475_Y[24] A[25]=$procmux$475_Y[25] A[26]=$procmux$475_Y[26] A[27]=$procmux$475_Y[27] A[28]=$procmux$475_Y[28] A[29]=$procmux$475_Y[29] A[30]=$procmux$475_Y[30] A[31]=$procmux$475_Y[31] B[0]=$false B[1]=$false B[2]=$false B[3]=$false B[4]=$false B[5]=$false B[6]=$false B[7]=$false B[8]=$false B[9]=$false B[10]=$false B[11]=$false B[12]=$false B[13]=$false B[14]=$false B[15]=$false B[16]=$false B[17]=$false B[18]=$false B[19]=$false B[20]=$false B[21]=$false B[22]=$false B[23]=$false B[24]=$false B[25]=$false B[26]=$false B[27]=$false B[28]=$false B[29]=$false B[30]=$false B[31]=$false S=$procmux$543_CMP Y[0]=$procmux$542_Y[0] Y[1]=$procmux$542_Y[1] Y[2]=$procmux$542_Y[2] Y[3]=$procmux$542_Y[3] Y[4]=$procmux$542_Y[4] Y[5]=$procmux$542_Y[5] Y[6]=$procmux$542_Y[6] Y[7]=$procmux$542_Y[7] Y[8]=$procmux$542_Y[8] Y[9]=$procmux$542_Y[9] Y[10]=$procmux$542_Y[10] Y[11]=$procmux$542_Y[11] Y[12]=$procmux$542_Y[12] Y[13]=$procmux$542_Y[13] Y[14]=$procmux$542_Y[14] Y[15]=$procmux$542_Y[15] Y[16]=$procmux$542_Y[16] Y[17]=$procmux$542_Y[17] Y[18]=$procmux$542_Y[18] Y[19]=$procmux$542_Y[19] Y[20]=$procmux$542_Y[20] Y[21]=$procmux$542_Y[21] Y[22]=$procmux$542_Y[22] Y[23]=$procmux$542_Y[23] Y[24]=$procmux$542_Y[24] Y[25]=$procmux$542_Y[25] Y[26]=$procmux$542_Y[26] Y[27]=$procmux$542_Y[27] Y[28]=$procmux$542_Y[28] Y[29]=$procmux$542_Y[29] Y[30]=$procmux$542_Y[30] Y[31]=$procmux$542_Y[31]
|
||
|
|
.cname $procmux$542
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:150"
|
||
|
|
.param WIDTH 00000000000000000000000000100000
|
||
|
|
.subckt $pmux A[0]=W10[0] A[1]=W10[1] A[2]=W10[2] A[3]=W10[3] A[4]=W10[4] A[5]=W10[5] A[6]=W10[6] A[7]=W10[7] A[8]=W10[8] A[9]=W10[9] A[10]=W10[10] A[11]=W10[11] A[12]=W10[12] A[13]=W10[13] A[14]=W10[14] A[15]=W10[15] A[16]=W10[16] A[17]=W10[17] A[18]=W10[18] A[19]=W10[19] A[20]=W10[20] A[21]=W10[21] A[22]=W10[22] A[23]=W10[23] A[24]=W10[24] A[25]=W10[25] A[26]=W10[26] A[27]=W10[27] A[28]=W10[28] A[29]=W10[29] A[30]=W10[30] A[31]=W10[31] B[0]=W11[0] B[1]=W11[1] B[2]=W11[2] B[3]=W11[3] B[4]=W11[4] B[5]=W11[5] B[6]=W11[6] B[7]=W11[7] B[8]=W11[8] B[9]=W11[9] B[10]=W11[10] B[11]=W11[11] B[12]=W11[12] B[13]=W11[13] B[14]=W11[14] B[15]=W11[15] B[16]=W11[16] B[17]=W11[17] B[18]=W11[18] B[19]=W11[19] B[20]=W11[20] B[21]=W11[21] B[22]=W11[22] B[23]=W11[23] B[24]=W11[24] B[25]=W11[25] B[26]=W11[26] B[27]=W11[27] B[28]=W11[28] B[29]=W11[29] B[30]=W11[30] B[31]=W11[31] B[32]=W11[0] B[33]=W11[1] B[34]=W11[2] B[35]=W11[3] B[36]=W11[4] B[37]=W11[5] B[38]=W11[6] B[39]=W11[7] B[40]=W11[8] B[41]=W11[9] B[42]=W11[10] B[43]=W11[11] B[44]=W11[12] B[45]=W11[13] B[46]=W11[14] B[47]=W11[15] B[48]=W11[16] B[49]=W11[17] B[50]=W11[18] B[51]=W11[19] B[52]=W11[20] B[53]=W11[21] B[54]=W11[22] B[55]=W11[23] B[56]=W11[24] B[57]=W11[25] B[58]=W11[26] B[59]=W11[27] B[60]=W11[28] B[61]=W11[29] B[62]=W11[30] B[63]=W11[31] B[64]=W11[0] B[65]=W11[1] B[66]=W11[2] B[67]=W11[3] B[68]=W11[4] B[69]=W11[5] B[70]=W11[6] B[71]=W11[7] B[72]=W11[8] B[73]=W11[9] B[74]=W11[10] B[75]=W11[11] B[76]=W11[12] B[77]=W11[13] B[78]=W11[14] B[79]=W11[15] B[80]=W11[16] B[81]=W11[17] B[82]=W11[18] B[83]=W11[19] B[84]=W11[20] B[85]=W11[21] B[86]=W11[22] B[87]=W11[23] B[88]=W11[24] B[89]=W11[25] B[90]=W11[26] B[91]=W11[27] B[92]=W11[28] B[93]=W11[29] B[94]=W11[30] B[95]=W11[31] B[96]=W11[0] B[97]=W11[1] B[98]=W11[2] B[99]=W11[3] B[100]=W11[4] B[101]=W11[5] B[102]=W11[6] B[103]=W11[7] B[104]=W11[8] B[105]=W11[9] B[106]=W11[10] B[107]=W11[11] B[108]=W11[12] B[109]=W11[13] B[110]=W11[14] B[111]=W11[15] B[112]=W11[16] B[113]=W11[17] B[114]=W11[18] B[115]=W11[19] B[116]=W11[20] B[117]=W11[21] B[118]=W11[22] B[119]=W11[23] B[120]=W11[24] B[121]=W11[25] B[122]=W11[26] B[123]=W11[27] B[124]=W11[28] B[125]=W11[29] B[126]=W11[30] B[127]=W11[31] B[128]=W11[0] B[129]=W11[1] B[130]=W11[2] B[131]=W11[3] B[132]=W11[4] B[133]=W11[5] B[134]=W11[6] B[135]=W11[7] B[136]=W11[8] B[137]=W11[9] B[138]=W11[10] B[139]=W11[11] B[140]=W11[12] B[141]=W11[13] B[142]=W11[14] B[143]=W11[15] B[144]=W11[16] B[145]=W11[17] B[146]=W11[18] B[147]=W11[19] B[148]=W11[20] B[149]=W11[21] B[150]=W11[22] B[151]=W11[23] B[152]=W11[24] B[153]=W11[25] B[154]=W11[26] B[155]=W11[27] B[156]=W11[28] B[157]=W11[29] B[158]=W11[30] B[159]=W11[31] B[160]=W11[0] B[161]=W11[1] B[162]=W11[2] B[163]=W11[3] B[164]=W11[4] B[165]=W11[5] B[166]=W11[6] B[167]=W11[7] B[168]=W11[8] B[169]=W11[9] B[170]=W11[10] B[171]=W11[11] B[172]=W11[12] B[173]=W11[13] B[174]=W11[14] B[175]=W11[15] B[176]=W11[16] B[177]=W11[17] B[178]=W11[18] B[179]=W11[19] B[180]=W11[20] B[181]=W11[21] B[182]=W11[22] B[183]=W11[23] B[184]=W11[24] B[185]=W11[25] B[186]=W11[26] B[187]=W11[27] B[188]=W11[28] B[189]=W11[29] B[190]=W11[30] B[191]=W11[31] B[192]=W11[0] B[193]=W11[1] B[194]=W11[2] B[195]=W11[3] B[196]=W11[4] B[197]=W11[5] B[198]=W11[6] B[199]=W11[7] B[200]=W11[8] B[201]=W11[9] B[202]=W11[10] B[203]=W11[11] B[204]=W11[12] B[205]=W11[13] B[206]=W11[14] B[207]=W11[15] B[208]=W11[16] B[209]=W11[17] B[210]=W11[18] B[211]=W11[19] B[212]=W11[20] B[213]=W11[21] B[214]=W11[22] B[215]=W11[23] B[216]=W11[24] B[217]=W11[25] B[218]=W11[26] B[219]=W11[27] B[220]=W11[28] B[221]=W11[29] B[222]=W11[30] B[223]=W11[31] B[224]=W11[0] B[225]=W11[1] B[226]=W11[2] B[227]=W11[3] B[228]=W11[4] B[229]=W11[5] B[230]=W11[6] B[231]=W11[7] B[232]=W11[8] B[233]=W11[9] B[234]=W11[10] B[235]=W11[11] B[236]=W11[12] B[237]=W11[13] B[238]=W11[14] B[239]=W11[15] B[240]=W11[16] B[241]=W11[17] B[242]=W11[18] B[243]=W11[19] B[244]=W11[20] B[245]=W11[21] B[246]=W11[22] B[247]=W11[23] B[248]=W11[24] B[249]=W11[25] B[250]=W11[26] B[251]=W11[27] B[252]=W11[28] B[253]=W11[29] B[254]=W11[30] B[255]=W11[31] B[2
|
||
|
|
.cname $procmux$546
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param S_WIDTH 00000000000000000000000001000001
|
||
|
|
.param WIDTH 00000000000000000000000000100000
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$true B[1]=$true B[2]=$true B[3]=$true B[4]=$false B[5]=$false B[6]=$true Y=$procmux$547_CMP
|
||
|
|
.cname $procmux$547_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$false B[1]=$true B[2]=$true B[3]=$true B[4]=$false B[5]=$false B[6]=$true Y=$procmux$548_CMP
|
||
|
|
.cname $procmux$548_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$true B[1]=$false B[2]=$true B[3]=$true B[4]=$false B[5]=$false B[6]=$true Y=$procmux$549_CMP
|
||
|
|
.cname $procmux$549_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$false B[1]=$false B[2]=$true B[3]=$true B[4]=$false B[5]=$false B[6]=$true Y=$procmux$550_CMP
|
||
|
|
.cname $procmux$550_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$true B[1]=$true B[2]=$false B[3]=$true B[4]=$false B[5]=$false B[6]=$true Y=$procmux$551_CMP
|
||
|
|
.cname $procmux$551_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$false B[1]=$true B[2]=$false B[3]=$true B[4]=$false B[5]=$false B[6]=$true Y=$procmux$552_CMP
|
||
|
|
.cname $procmux$552_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$true B[1]=$false B[2]=$false B[3]=$true B[4]=$false B[5]=$false B[6]=$true Y=$procmux$553_CMP
|
||
|
|
.cname $procmux$553_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$false B[1]=$false B[2]=$false B[3]=$true B[4]=$false B[5]=$false B[6]=$true Y=$procmux$554_CMP
|
||
|
|
.cname $procmux$554_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$true B[1]=$true B[2]=$true B[3]=$false B[4]=$false B[5]=$false B[6]=$true Y=$procmux$555_CMP
|
||
|
|
.cname $procmux$555_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$false B[1]=$true B[2]=$true B[3]=$false B[4]=$false B[5]=$false B[6]=$true Y=$procmux$556_CMP
|
||
|
|
.cname $procmux$556_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$true B[1]=$false B[2]=$true B[3]=$false B[4]=$false B[5]=$false B[6]=$true Y=$procmux$557_CMP
|
||
|
|
.cname $procmux$557_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$false B[1]=$false B[2]=$true B[3]=$false B[4]=$false B[5]=$false B[6]=$true Y=$procmux$558_CMP
|
||
|
|
.cname $procmux$558_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$true B[1]=$true B[2]=$false B[3]=$false B[4]=$false B[5]=$false B[6]=$true Y=$procmux$559_CMP
|
||
|
|
.cname $procmux$559_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $pmux A[0]=$false A[1]=$false A[2]=$false A[3]=$false A[4]=$false A[5]=$false A[6]=$false A[7]=$false A[8]=$false A[9]=$false A[10]=$false A[11]=$false A[12]=$false A[13]=$false A[14]=$false A[15]=$false A[16]=$false A[17]=$false A[18]=$false A[19]=$false A[20]=$false A[21]=$false A[22]=$false A[23]=$false A[24]=$false A[25]=$false A[26]=$false A[27]=$false A[28]=$false A[29]=$false A[30]=$false A[31]=$false B[0]=SHA1_result[0] B[1]=SHA1_result[1] B[2]=SHA1_result[2] B[3]=SHA1_result[3] B[4]=SHA1_result[4] B[5]=SHA1_result[5] B[6]=SHA1_result[6] B[7]=SHA1_result[7] B[8]=SHA1_result[8] B[9]=SHA1_result[9] B[10]=SHA1_result[10] B[11]=SHA1_result[11] B[12]=SHA1_result[12] B[13]=SHA1_result[13] B[14]=SHA1_result[14] B[15]=SHA1_result[15] B[16]=SHA1_result[16] B[17]=SHA1_result[17] B[18]=SHA1_result[18] B[19]=SHA1_result[19] B[20]=SHA1_result[20] B[21]=SHA1_result[21] B[22]=SHA1_result[22] B[23]=SHA1_result[23] B[24]=SHA1_result[24] B[25]=SHA1_result[25] B[26]=SHA1_result[26] B[27]=SHA1_result[27] B[28]=SHA1_result[28] B[29]=SHA1_result[29] B[30]=SHA1_result[30] B[31]=SHA1_result[31] B[32]=SHA1_result[32] B[33]=SHA1_result[33] B[34]=SHA1_result[34] B[35]=SHA1_result[35] B[36]=SHA1_result[36] B[37]=SHA1_result[37] B[38]=SHA1_result[38] B[39]=SHA1_result[39] B[40]=SHA1_result[40] B[41]=SHA1_result[41] B[42]=SHA1_result[42] B[43]=SHA1_result[43] B[44]=SHA1_result[44] B[45]=SHA1_result[45] B[46]=SHA1_result[46] B[47]=SHA1_result[47] B[48]=SHA1_result[48] B[49]=SHA1_result[49] B[50]=SHA1_result[50] B[51]=SHA1_result[51] B[52]=SHA1_result[52] B[53]=SHA1_result[53] B[54]=SHA1_result[54] B[55]=SHA1_result[55] B[56]=SHA1_result[56] B[57]=SHA1_result[57] B[58]=SHA1_result[58] B[59]=SHA1_result[59] B[60]=SHA1_result[60] B[61]=SHA1_result[61] B[62]=SHA1_result[62] B[63]=SHA1_result[63] B[64]=SHA1_result[64] B[65]=SHA1_result[65] B[66]=SHA1_result[66] B[67]=SHA1_result[67] B[68]=SHA1_result[68] B[69]=SHA1_result[69] B[70]=SHA1_result[70] B[71]=SHA1_result[71] B[72]=SHA1_result[72] B[73]=SHA1_result[73] B[74]=SHA1_result[74] B[75]=SHA1_result[75] B[76]=SHA1_result[76] B[77]=SHA1_result[77] B[78]=SHA1_result[78] B[79]=SHA1_result[79] B[80]=SHA1_result[80] B[81]=SHA1_result[81] B[82]=SHA1_result[82] B[83]=SHA1_result[83] B[84]=SHA1_result[84] B[85]=SHA1_result[85] B[86]=SHA1_result[86] B[87]=SHA1_result[87] B[88]=SHA1_result[88] B[89]=SHA1_result[89] B[90]=SHA1_result[90] B[91]=SHA1_result[91] B[92]=SHA1_result[92] B[93]=SHA1_result[93] B[94]=SHA1_result[94] B[95]=SHA1_result[95] B[96]=SHA1_result[96] B[97]=SHA1_result[97] B[98]=SHA1_result[98] B[99]=SHA1_result[99] B[100]=SHA1_result[100] B[101]=SHA1_result[101] B[102]=SHA1_result[102] B[103]=SHA1_result[103] B[104]=SHA1_result[104] B[105]=SHA1_result[105] B[106]=SHA1_result[106] B[107]=SHA1_result[107] B[108]=SHA1_result[108] B[109]=SHA1_result[109] B[110]=SHA1_result[110] B[111]=SHA1_result[111] B[112]=SHA1_result[112] B[113]=SHA1_result[113] B[114]=SHA1_result[114] B[115]=SHA1_result[115] B[116]=SHA1_result[116] B[117]=SHA1_result[117] B[118]=SHA1_result[118] B[119]=SHA1_result[119] B[120]=SHA1_result[120] B[121]=SHA1_result[121] B[122]=SHA1_result[122] B[123]=SHA1_result[123] B[124]=SHA1_result[124] B[125]=SHA1_result[125] B[126]=SHA1_result[126] B[127]=SHA1_result[127] B[128]=SHA1_result[128] B[129]=SHA1_result[129] B[130]=SHA1_result[130] B[131]=SHA1_result[131] B[132]=SHA1_result[132] B[133]=SHA1_result[133] B[134]=SHA1_result[134] B[135]=SHA1_result[135] B[136]=SHA1_result[136] B[137]=SHA1_result[137] B[138]=SHA1_result[138] B[139]=SHA1_result[139] B[140]=SHA1_result[140] B[141]=SHA1_result[141] B[142]=SHA1_result[142] B[143]=SHA1_result[143] B[144]=SHA1_result[144] B[145]=SHA1_result[145] B[146]=SHA1_result[146] B[147]=SHA1_result[147] B[148]=SHA1_result[148] B[149]=SHA1_result[149] B[150]=SHA1_result[150] B[151]=SHA1_result[151] B[152]=SHA1_result[152] B[153]=SHA1_result[153] B[154]=SHA1_result[154] B[155]=SHA1_result[155] B[156]=SHA1_result[156] B[157]=SHA1_result[157] B[158]=SHA1_result[158] B[159]=SHA1_result[159] S[0]=$procmux$57_CMP S[1]=$procmux$58_CMP S[2]=$procmux
|
||
|
|
.cname $procmux$56
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:2151"
|
||
|
|
.param S_WIDTH 00000000000000000000000000000101
|
||
|
|
.param WIDTH 00000000000000000000000000100000
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$false B[1]=$true B[2]=$false B[3]=$false B[4]=$false B[5]=$false B[6]=$true Y=$procmux$560_CMP
|
||
|
|
.cname $procmux$560_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$true B[1]=$false B[2]=$false B[3]=$false B[4]=$false B[5]=$false B[6]=$true Y=$procmux$561_CMP
|
||
|
|
.cname $procmux$561_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$false B[1]=$false B[2]=$false B[3]=$false B[4]=$false B[5]=$false B[6]=$true Y=$procmux$562_CMP
|
||
|
|
.cname $procmux$562_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$true B[1]=$true B[2]=$true B[3]=$true B[4]=$true B[5]=$true B[6]=$false Y=$procmux$563_CMP
|
||
|
|
.cname $procmux$563_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$false B[1]=$true B[2]=$true B[3]=$true B[4]=$true B[5]=$true B[6]=$false Y=$procmux$564_CMP
|
||
|
|
.cname $procmux$564_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$true B[1]=$false B[2]=$true B[3]=$true B[4]=$true B[5]=$true B[6]=$false Y=$procmux$565_CMP
|
||
|
|
.cname $procmux$565_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$false B[1]=$false B[2]=$true B[3]=$true B[4]=$true B[5]=$true B[6]=$false Y=$procmux$566_CMP
|
||
|
|
.cname $procmux$566_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$true B[1]=$true B[2]=$false B[3]=$true B[4]=$true B[5]=$true B[6]=$false Y=$procmux$567_CMP
|
||
|
|
.cname $procmux$567_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$false B[1]=$true B[2]=$false B[3]=$true B[4]=$true B[5]=$true B[6]=$false Y=$procmux$568_CMP
|
||
|
|
.cname $procmux$568_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$true B[1]=$false B[2]=$false B[3]=$true B[4]=$true B[5]=$true B[6]=$false Y=$procmux$569_CMP
|
||
|
|
.cname $procmux$569_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$false B[1]=$false B[2]=$false B[3]=$true B[4]=$true B[5]=$true B[6]=$false Y=$procmux$570_CMP
|
||
|
|
.cname $procmux$570_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$true B[1]=$true B[2]=$true B[3]=$false B[4]=$true B[5]=$true B[6]=$false Y=$procmux$571_CMP
|
||
|
|
.cname $procmux$571_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$false B[1]=$true B[2]=$true B[3]=$false B[4]=$true B[5]=$true B[6]=$false Y=$procmux$572_CMP
|
||
|
|
.cname $procmux$572_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$true B[1]=$false B[2]=$true B[3]=$false B[4]=$true B[5]=$true B[6]=$false Y=$procmux$573_CMP
|
||
|
|
.cname $procmux$573_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$false B[1]=$false B[2]=$true B[3]=$false B[4]=$true B[5]=$true B[6]=$false Y=$procmux$574_CMP
|
||
|
|
.cname $procmux$574_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$true B[1]=$true B[2]=$false B[3]=$false B[4]=$true B[5]=$true B[6]=$false Y=$procmux$575_CMP
|
||
|
|
.cname $procmux$575_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$false B[1]=$true B[2]=$false B[3]=$false B[4]=$true B[5]=$true B[6]=$false Y=$procmux$576_CMP
|
||
|
|
.cname $procmux$576_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$true B[1]=$false B[2]=$false B[3]=$false B[4]=$true B[5]=$true B[6]=$false Y=$procmux$577_CMP
|
||
|
|
.cname $procmux$577_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$false B[1]=$false B[2]=$false B[3]=$false B[4]=$true B[5]=$true B[6]=$false Y=$procmux$578_CMP
|
||
|
|
.cname $procmux$578_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$true B[1]=$true B[2]=$true B[3]=$true B[4]=$false B[5]=$true B[6]=$false Y=$procmux$579_CMP
|
||
|
|
.cname $procmux$579_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=read_counter[0] A[1]=read_counter[1] A[2]=read_counter[2] B[0]=$false B[1]=$false B[2]=$false Y=$procmux$57_CMP
|
||
|
|
.cname $procmux$57_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:2151"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000011
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000011
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$false B[1]=$true B[2]=$true B[3]=$true B[4]=$false B[5]=$true B[6]=$false Y=$procmux$580_CMP
|
||
|
|
.cname $procmux$580_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$true B[1]=$false B[2]=$true B[3]=$true B[4]=$false B[5]=$true B[6]=$false Y=$procmux$581_CMP
|
||
|
|
.cname $procmux$581_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$false B[1]=$false B[2]=$true B[3]=$true B[4]=$false B[5]=$true B[6]=$false Y=$procmux$582_CMP
|
||
|
|
.cname $procmux$582_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$true B[1]=$true B[2]=$false B[3]=$true B[4]=$false B[5]=$true B[6]=$false Y=$procmux$583_CMP
|
||
|
|
.cname $procmux$583_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$false B[1]=$true B[2]=$false B[3]=$true B[4]=$false B[5]=$true B[6]=$false Y=$procmux$584_CMP
|
||
|
|
.cname $procmux$584_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$true B[1]=$false B[2]=$false B[3]=$true B[4]=$false B[5]=$true B[6]=$false Y=$procmux$585_CMP
|
||
|
|
.cname $procmux$585_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$false B[1]=$false B[2]=$false B[3]=$true B[4]=$false B[5]=$true B[6]=$false Y=$procmux$586_CMP
|
||
|
|
.cname $procmux$586_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$true B[1]=$true B[2]=$true B[3]=$false B[4]=$false B[5]=$true B[6]=$false Y=$procmux$587_CMP
|
||
|
|
.cname $procmux$587_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$false B[1]=$true B[2]=$true B[3]=$false B[4]=$false B[5]=$true B[6]=$false Y=$procmux$588_CMP
|
||
|
|
.cname $procmux$588_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$true B[1]=$false B[2]=$true B[3]=$false B[4]=$false B[5]=$true B[6]=$false Y=$procmux$589_CMP
|
||
|
|
.cname $procmux$589_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=read_counter[0] A[1]=read_counter[1] A[2]=read_counter[2] B[0]=$true B[1]=$false B[2]=$false Y=$procmux$58_CMP
|
||
|
|
.cname $procmux$58_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:2151"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000011
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000011
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$false B[1]=$false B[2]=$true B[3]=$false B[4]=$false B[5]=$true B[6]=$false Y=$procmux$590_CMP
|
||
|
|
.cname $procmux$590_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$true B[1]=$true B[2]=$false B[3]=$false B[4]=$false B[5]=$true B[6]=$false Y=$procmux$591_CMP
|
||
|
|
.cname $procmux$591_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$false B[1]=$true B[2]=$false B[3]=$false B[4]=$false B[5]=$true B[6]=$false Y=$procmux$592_CMP
|
||
|
|
.cname $procmux$592_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$true B[1]=$false B[2]=$false B[3]=$false B[4]=$false B[5]=$true B[6]=$false Y=$procmux$593_CMP
|
||
|
|
.cname $procmux$593_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$false B[1]=$false B[2]=$false B[3]=$false B[4]=$false B[5]=$true B[6]=$false Y=$procmux$594_CMP
|
||
|
|
.cname $procmux$594_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$true B[1]=$true B[2]=$true B[3]=$true B[4]=$true B[5]=$false B[6]=$false Y=$procmux$595_CMP
|
||
|
|
.cname $procmux$595_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$false B[1]=$true B[2]=$true B[3]=$true B[4]=$true B[5]=$false B[6]=$false Y=$procmux$596_CMP
|
||
|
|
.cname $procmux$596_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$true B[1]=$false B[2]=$true B[3]=$true B[4]=$true B[5]=$false B[6]=$false Y=$procmux$597_CMP
|
||
|
|
.cname $procmux$597_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$false B[1]=$false B[2]=$true B[3]=$true B[4]=$true B[5]=$false B[6]=$false Y=$procmux$598_CMP
|
||
|
|
.cname $procmux$598_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$true B[1]=$true B[2]=$false B[3]=$true B[4]=$true B[5]=$false B[6]=$false Y=$procmux$599_CMP
|
||
|
|
.cname $procmux$599_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=read_counter[0] A[1]=read_counter[1] A[2]=read_counter[2] B[0]=$false B[1]=$true B[2]=$false Y=$procmux$59_CMP
|
||
|
|
.cname $procmux$59_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:2151"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000011
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000011
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$false B[1]=$true B[2]=$false B[3]=$true B[4]=$true B[5]=$false B[6]=$false Y=$procmux$600_CMP
|
||
|
|
.cname $procmux$600_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$true B[1]=$false B[2]=$false B[3]=$true B[4]=$true B[5]=$false B[6]=$false Y=$procmux$601_CMP
|
||
|
|
.cname $procmux$601_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$false B[1]=$false B[2]=$false B[3]=$true B[4]=$true B[5]=$false B[6]=$false Y=$procmux$602_CMP
|
||
|
|
.cname $procmux$602_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$true B[1]=$true B[2]=$true B[3]=$false B[4]=$true B[5]=$false B[6]=$false Y=$procmux$603_CMP
|
||
|
|
.cname $procmux$603_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$false B[1]=$true B[2]=$true B[3]=$false B[4]=$true B[5]=$false B[6]=$false Y=$procmux$604_CMP
|
||
|
|
.cname $procmux$604_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$true B[1]=$false B[2]=$true B[3]=$false B[4]=$true B[5]=$false B[6]=$false Y=$procmux$605_CMP
|
||
|
|
.cname $procmux$605_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$false B[1]=$false B[2]=$true B[3]=$false B[4]=$true B[5]=$false B[6]=$false Y=$procmux$606_CMP
|
||
|
|
.cname $procmux$606_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$true B[1]=$true B[2]=$false B[3]=$false B[4]=$true B[5]=$false B[6]=$false Y=$procmux$607_CMP
|
||
|
|
.cname $procmux$607_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$false B[1]=$true B[2]=$false B[3]=$false B[4]=$true B[5]=$false B[6]=$false Y=$procmux$608_CMP
|
||
|
|
.cname $procmux$608_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$true B[1]=$false B[2]=$false B[3]=$false B[4]=$true B[5]=$false B[6]=$false Y=$procmux$609_CMP
|
||
|
|
.cname $procmux$609_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=read_counter[0] A[1]=read_counter[1] A[2]=read_counter[2] B[0]=$true B[1]=$true B[2]=$false Y=$procmux$60_CMP
|
||
|
|
.cname $procmux$60_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:2151"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000011
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000011
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$false B[1]=$false B[2]=$false B[3]=$false B[4]=$true B[5]=$false B[6]=$false Y=$procmux$610_CMP
|
||
|
|
.cname $procmux$610_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$false B[1]=$true B[2]=$false B[3]=$true B[4]=$false B[5]=$false B[6]=$false Y=$procmux$611_CMP
|
||
|
|
.cname $procmux$611_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $mux A[0]=$procmux$546_Y[0] A[1]=$procmux$546_Y[1] A[2]=$procmux$546_Y[2] A[3]=$procmux$546_Y[3] A[4]=$procmux$546_Y[4] A[5]=$procmux$546_Y[5] A[6]=$procmux$546_Y[6] A[7]=$procmux$546_Y[7] A[8]=$procmux$546_Y[8] A[9]=$procmux$546_Y[9] A[10]=$procmux$546_Y[10] A[11]=$procmux$546_Y[11] A[12]=$procmux$546_Y[12] A[13]=$procmux$546_Y[13] A[14]=$procmux$546_Y[14] A[15]=$procmux$546_Y[15] A[16]=$procmux$546_Y[16] A[17]=$procmux$546_Y[17] A[18]=$procmux$546_Y[18] A[19]=$procmux$546_Y[19] A[20]=$procmux$546_Y[20] A[21]=$procmux$546_Y[21] A[22]=$procmux$546_Y[22] A[23]=$procmux$546_Y[23] A[24]=$procmux$546_Y[24] A[25]=$procmux$546_Y[25] A[26]=$procmux$546_Y[26] A[27]=$procmux$546_Y[27] A[28]=$procmux$546_Y[28] A[29]=$procmux$546_Y[29] A[30]=$procmux$546_Y[30] A[31]=$procmux$546_Y[31] B[0]=$false B[1]=$false B[2]=$false B[3]=$false B[4]=$false B[5]=$false B[6]=$false B[7]=$false B[8]=$false B[9]=$false B[10]=$false B[11]=$false B[12]=$false B[13]=$false B[14]=$false B[15]=$false B[16]=$false B[17]=$false B[18]=$false B[19]=$false B[20]=$false B[21]=$false B[22]=$false B[23]=$false B[24]=$false B[25]=$false B[26]=$false B[27]=$false B[28]=$false B[29]=$false B[30]=$false B[31]=$false S=$procmux$614_CMP Y[0]=$procmux$613_Y[0] Y[1]=$procmux$613_Y[1] Y[2]=$procmux$613_Y[2] Y[3]=$procmux$613_Y[3] Y[4]=$procmux$613_Y[4] Y[5]=$procmux$613_Y[5] Y[6]=$procmux$613_Y[6] Y[7]=$procmux$613_Y[7] Y[8]=$procmux$613_Y[8] Y[9]=$procmux$613_Y[9] Y[10]=$procmux$613_Y[10] Y[11]=$procmux$613_Y[11] Y[12]=$procmux$613_Y[12] Y[13]=$procmux$613_Y[13] Y[14]=$procmux$613_Y[14] Y[15]=$procmux$613_Y[15] Y[16]=$procmux$613_Y[16] Y[17]=$procmux$613_Y[17] Y[18]=$procmux$613_Y[18] Y[19]=$procmux$613_Y[19] Y[20]=$procmux$613_Y[20] Y[21]=$procmux$613_Y[21] Y[22]=$procmux$613_Y[22] Y[23]=$procmux$613_Y[23] Y[24]=$procmux$613_Y[24] Y[25]=$procmux$613_Y[25] Y[26]=$procmux$613_Y[26] Y[27]=$procmux$613_Y[27] Y[28]=$procmux$613_Y[28] Y[29]=$procmux$613_Y[29] Y[30]=$procmux$613_Y[30] Y[31]=$procmux$613_Y[31]
|
||
|
|
.cname $procmux$613
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:150"
|
||
|
|
.param WIDTH 00000000000000000000000000100000
|
||
|
|
.subckt $pmux A[0]=W9[0] A[1]=W9[1] A[2]=W9[2] A[3]=W9[3] A[4]=W9[4] A[5]=W9[5] A[6]=W9[6] A[7]=W9[7] A[8]=W9[8] A[9]=W9[9] A[10]=W9[10] A[11]=W9[11] A[12]=W9[12] A[13]=W9[13] A[14]=W9[14] A[15]=W9[15] A[16]=W9[16] A[17]=W9[17] A[18]=W9[18] A[19]=W9[19] A[20]=W9[20] A[21]=W9[21] A[22]=W9[22] A[23]=W9[23] A[24]=W9[24] A[25]=W9[25] A[26]=W9[26] A[27]=W9[27] A[28]=W9[28] A[29]=W9[29] A[30]=W9[30] A[31]=W9[31] B[0]=W10[0] B[1]=W10[1] B[2]=W10[2] B[3]=W10[3] B[4]=W10[4] B[5]=W10[5] B[6]=W10[6] B[7]=W10[7] B[8]=W10[8] B[9]=W10[9] B[10]=W10[10] B[11]=W10[11] B[12]=W10[12] B[13]=W10[13] B[14]=W10[14] B[15]=W10[15] B[16]=W10[16] B[17]=W10[17] B[18]=W10[18] B[19]=W10[19] B[20]=W10[20] B[21]=W10[21] B[22]=W10[22] B[23]=W10[23] B[24]=W10[24] B[25]=W10[25] B[26]=W10[26] B[27]=W10[27] B[28]=W10[28] B[29]=W10[29] B[30]=W10[30] B[31]=W10[31] B[32]=W10[0] B[33]=W10[1] B[34]=W10[2] B[35]=W10[3] B[36]=W10[4] B[37]=W10[5] B[38]=W10[6] B[39]=W10[7] B[40]=W10[8] B[41]=W10[9] B[42]=W10[10] B[43]=W10[11] B[44]=W10[12] B[45]=W10[13] B[46]=W10[14] B[47]=W10[15] B[48]=W10[16] B[49]=W10[17] B[50]=W10[18] B[51]=W10[19] B[52]=W10[20] B[53]=W10[21] B[54]=W10[22] B[55]=W10[23] B[56]=W10[24] B[57]=W10[25] B[58]=W10[26] B[59]=W10[27] B[60]=W10[28] B[61]=W10[29] B[62]=W10[30] B[63]=W10[31] B[64]=W10[0] B[65]=W10[1] B[66]=W10[2] B[67]=W10[3] B[68]=W10[4] B[69]=W10[5] B[70]=W10[6] B[71]=W10[7] B[72]=W10[8] B[73]=W10[9] B[74]=W10[10] B[75]=W10[11] B[76]=W10[12] B[77]=W10[13] B[78]=W10[14] B[79]=W10[15] B[80]=W10[16] B[81]=W10[17] B[82]=W10[18] B[83]=W10[19] B[84]=W10[20] B[85]=W10[21] B[86]=W10[22] B[87]=W10[23] B[88]=W10[24] B[89]=W10[25] B[90]=W10[26] B[91]=W10[27] B[92]=W10[28] B[93]=W10[29] B[94]=W10[30] B[95]=W10[31] B[96]=W10[0] B[97]=W10[1] B[98]=W10[2] B[99]=W10[3] B[100]=W10[4] B[101]=W10[5] B[102]=W10[6] B[103]=W10[7] B[104]=W10[8] B[105]=W10[9] B[106]=W10[10] B[107]=W10[11] B[108]=W10[12] B[109]=W10[13] B[110]=W10[14] B[111]=W10[15] B[112]=W10[16] B[113]=W10[17] B[114]=W10[18] B[115]=W10[19] B[116]=W10[20] B[117]=W10[21] B[118]=W10[22] B[119]=W10[23] B[120]=W10[24] B[121]=W10[25] B[122]=W10[26] B[123]=W10[27] B[124]=W10[28] B[125]=W10[29] B[126]=W10[30] B[127]=W10[31] B[128]=W10[0] B[129]=W10[1] B[130]=W10[2] B[131]=W10[3] B[132]=W10[4] B[133]=W10[5] B[134]=W10[6] B[135]=W10[7] B[136]=W10[8] B[137]=W10[9] B[138]=W10[10] B[139]=W10[11] B[140]=W10[12] B[141]=W10[13] B[142]=W10[14] B[143]=W10[15] B[144]=W10[16] B[145]=W10[17] B[146]=W10[18] B[147]=W10[19] B[148]=W10[20] B[149]=W10[21] B[150]=W10[22] B[151]=W10[23] B[152]=W10[24] B[153]=W10[25] B[154]=W10[26] B[155]=W10[27] B[156]=W10[28] B[157]=W10[29] B[158]=W10[30] B[159]=W10[31] B[160]=W10[0] B[161]=W10[1] B[162]=W10[2] B[163]=W10[3] B[164]=W10[4] B[165]=W10[5] B[166]=W10[6] B[167]=W10[7] B[168]=W10[8] B[169]=W10[9] B[170]=W10[10] B[171]=W10[11] B[172]=W10[12] B[173]=W10[13] B[174]=W10[14] B[175]=W10[15] B[176]=W10[16] B[177]=W10[17] B[178]=W10[18] B[179]=W10[19] B[180]=W10[20] B[181]=W10[21] B[182]=W10[22] B[183]=W10[23] B[184]=W10[24] B[185]=W10[25] B[186]=W10[26] B[187]=W10[27] B[188]=W10[28] B[189]=W10[29] B[190]=W10[30] B[191]=W10[31] B[192]=W10[0] B[193]=W10[1] B[194]=W10[2] B[195]=W10[3] B[196]=W10[4] B[197]=W10[5] B[198]=W10[6] B[199]=W10[7] B[200]=W10[8] B[201]=W10[9] B[202]=W10[10] B[203]=W10[11] B[204]=W10[12] B[205]=W10[13] B[206]=W10[14] B[207]=W10[15] B[208]=W10[16] B[209]=W10[17] B[210]=W10[18] B[211]=W10[19] B[212]=W10[20] B[213]=W10[21] B[214]=W10[22] B[215]=W10[23] B[216]=W10[24] B[217]=W10[25] B[218]=W10[26] B[219]=W10[27] B[220]=W10[28] B[221]=W10[29] B[222]=W10[30] B[223]=W10[31] B[224]=W10[0] B[225]=W10[1] B[226]=W10[2] B[227]=W10[3] B[228]=W10[4] B[229]=W10[5] B[230]=W10[6] B[231]=W10[7] B[232]=W10[8] B[233]=W10[9] B[234]=W10[10] B[235]=W10[11] B[236]=W10[12] B[237]=W10[13] B[238]=W10[14] B[239]=W10[15] B[240]=W10[16] B[241]=W10[17] B[242]=W10[18] B[243]=W10[19] B[244]=W10[20] B[245]=W10[21] B[246]=W10[22] B[247]=W10[23] B[248]=W10[24] B[249]=W10[25] B[250]=W10[26] B[251]=W10[27] B[252]=W10[28] B[253]=W10[29] B[254]=W10[30] B[255]=W10[31] B[256]=W10[0] B[257]=W10[1] B[258]=
|
||
|
|
.cname $procmux$617
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param S_WIDTH 00000000000000000000000001000001
|
||
|
|
.param WIDTH 00000000000000000000000000100000
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$true B[1]=$true B[2]=$true B[3]=$true B[4]=$false B[5]=$false B[6]=$true Y=$procmux$618_CMP
|
||
|
|
.cname $procmux$618_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$false B[1]=$true B[2]=$true B[3]=$true B[4]=$false B[5]=$false B[6]=$true Y=$procmux$619_CMP
|
||
|
|
.cname $procmux$619_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=read_counter[0] A[1]=read_counter[1] A[2]=read_counter[2] B[0]=$false B[1]=$false B[2]=$true Y=$procmux$61_CMP
|
||
|
|
.cname $procmux$61_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:2151"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000011
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000011
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $mux A[0]=$false A[1]=$false A[2]=$false A[3]=$false A[4]=$false A[5]=$false A[6]=$false A[7]=$false A[8]=$false A[9]=$false A[10]=$false A[11]=$false A[12]=$false A[13]=$false A[14]=$false A[15]=$false A[16]=$false A[17]=$false A[18]=$false A[19]=$false A[20]=$false A[21]=$false A[22]=$false A[23]=$false A[24]=$false A[25]=$false A[26]=$false A[27]=$false A[28]=$false A[29]=$false A[30]=$false A[31]=$false B[0]=$procmux$56_Y[0] B[1]=$procmux$56_Y[1] B[2]=$procmux$56_Y[2] B[3]=$procmux$56_Y[3] B[4]=$procmux$56_Y[4] B[5]=$procmux$56_Y[5] B[6]=$procmux$56_Y[6] B[7]=$procmux$56_Y[7] B[8]=$procmux$56_Y[8] B[9]=$procmux$56_Y[9] B[10]=$procmux$56_Y[10] B[11]=$procmux$56_Y[11] B[12]=$procmux$56_Y[12] B[13]=$procmux$56_Y[13] B[14]=$procmux$56_Y[14] B[15]=$procmux$56_Y[15] B[16]=$procmux$56_Y[16] B[17]=$procmux$56_Y[17] B[18]=$procmux$56_Y[18] B[19]=$procmux$56_Y[19] B[20]=$procmux$56_Y[20] B[21]=$procmux$56_Y[21] B[22]=$procmux$56_Y[22] B[23]=$procmux$56_Y[23] B[24]=$procmux$56_Y[24] B[25]=$procmux$56_Y[25] B[26]=$procmux$56_Y[26] B[27]=$procmux$56_Y[27] B[28]=$procmux$56_Y[28] B[29]=$procmux$56_Y[29] B[30]=$procmux$56_Y[30] B[31]=$procmux$56_Y[31] S=$procmux$63_CMP Y[0]=$procmux$62_Y[0] Y[1]=$procmux$62_Y[1] Y[2]=$procmux$62_Y[2] Y[3]=$procmux$62_Y[3] Y[4]=$procmux$62_Y[4] Y[5]=$procmux$62_Y[5] Y[6]=$procmux$62_Y[6] Y[7]=$procmux$62_Y[7] Y[8]=$procmux$62_Y[8] Y[9]=$procmux$62_Y[9] Y[10]=$procmux$62_Y[10] Y[11]=$procmux$62_Y[11] Y[12]=$procmux$62_Y[12] Y[13]=$procmux$62_Y[13] Y[14]=$procmux$62_Y[14] Y[15]=$procmux$62_Y[15] Y[16]=$procmux$62_Y[16] Y[17]=$procmux$62_Y[17] Y[18]=$procmux$62_Y[18] Y[19]=$procmux$62_Y[19] Y[20]=$procmux$62_Y[20] Y[21]=$procmux$62_Y[21] Y[22]=$procmux$62_Y[22] Y[23]=$procmux$62_Y[23] Y[24]=$procmux$62_Y[24] Y[25]=$procmux$62_Y[25] Y[26]=$procmux$62_Y[26] Y[27]=$procmux$62_Y[27] Y[28]=$procmux$62_Y[28] Y[29]=$procmux$62_Y[29] Y[30]=$procmux$62_Y[30] Y[31]=$procmux$62_Y[31]
|
||
|
|
.cname $procmux$62
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:2149"
|
||
|
|
.param WIDTH 00000000000000000000000000100000
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$true B[1]=$false B[2]=$true B[3]=$true B[4]=$false B[5]=$false B[6]=$true Y=$procmux$620_CMP
|
||
|
|
.cname $procmux$620_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$false B[1]=$false B[2]=$true B[3]=$true B[4]=$false B[5]=$false B[6]=$true Y=$procmux$621_CMP
|
||
|
|
.cname $procmux$621_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$true B[1]=$true B[2]=$false B[3]=$true B[4]=$false B[5]=$false B[6]=$true Y=$procmux$622_CMP
|
||
|
|
.cname $procmux$622_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$false B[1]=$true B[2]=$false B[3]=$true B[4]=$false B[5]=$false B[6]=$true Y=$procmux$623_CMP
|
||
|
|
.cname $procmux$623_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$true B[1]=$false B[2]=$false B[3]=$true B[4]=$false B[5]=$false B[6]=$true Y=$procmux$624_CMP
|
||
|
|
.cname $procmux$624_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$false B[1]=$false B[2]=$false B[3]=$true B[4]=$false B[5]=$false B[6]=$true Y=$procmux$625_CMP
|
||
|
|
.cname $procmux$625_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$true B[1]=$true B[2]=$true B[3]=$false B[4]=$false B[5]=$false B[6]=$true Y=$procmux$626_CMP
|
||
|
|
.cname $procmux$626_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$false B[1]=$true B[2]=$true B[3]=$false B[4]=$false B[5]=$false B[6]=$true Y=$procmux$627_CMP
|
||
|
|
.cname $procmux$627_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$true B[1]=$false B[2]=$true B[3]=$false B[4]=$false B[5]=$false B[6]=$true Y=$procmux$628_CMP
|
||
|
|
.cname $procmux$628_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$false B[1]=$false B[2]=$true B[3]=$false B[4]=$false B[5]=$false B[6]=$true Y=$procmux$629_CMP
|
||
|
|
.cname $procmux$629_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$true B[1]=$true B[2]=$false B[3]=$false B[4]=$false B[5]=$false B[6]=$true Y=$procmux$630_CMP
|
||
|
|
.cname $procmux$630_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$false B[1]=$true B[2]=$false B[3]=$false B[4]=$false B[5]=$false B[6]=$true Y=$procmux$631_CMP
|
||
|
|
.cname $procmux$631_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$true B[1]=$false B[2]=$false B[3]=$false B[4]=$false B[5]=$false B[6]=$true Y=$procmux$632_CMP
|
||
|
|
.cname $procmux$632_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$false B[1]=$false B[2]=$false B[3]=$false B[4]=$false B[5]=$false B[6]=$true Y=$procmux$633_CMP
|
||
|
|
.cname $procmux$633_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$true B[1]=$true B[2]=$true B[3]=$true B[4]=$true B[5]=$true B[6]=$false Y=$procmux$634_CMP
|
||
|
|
.cname $procmux$634_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$false B[1]=$true B[2]=$true B[3]=$true B[4]=$true B[5]=$true B[6]=$false Y=$procmux$635_CMP
|
||
|
|
.cname $procmux$635_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$true B[1]=$false B[2]=$true B[3]=$true B[4]=$true B[5]=$true B[6]=$false Y=$procmux$636_CMP
|
||
|
|
.cname $procmux$636_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$false B[1]=$false B[2]=$true B[3]=$true B[4]=$true B[5]=$true B[6]=$false Y=$procmux$637_CMP
|
||
|
|
.cname $procmux$637_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$true B[1]=$true B[2]=$false B[3]=$true B[4]=$true B[5]=$true B[6]=$false Y=$procmux$638_CMP
|
||
|
|
.cname $procmux$638_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$false B[1]=$true B[2]=$false B[3]=$true B[4]=$true B[5]=$true B[6]=$false Y=$procmux$639_CMP
|
||
|
|
.cname $procmux$639_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$true B[1]=$false B[2]=$false B[3]=$true B[4]=$true B[5]=$true B[6]=$false Y=$procmux$640_CMP
|
||
|
|
.cname $procmux$640_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$false B[1]=$false B[2]=$false B[3]=$true B[4]=$true B[5]=$true B[6]=$false Y=$procmux$641_CMP
|
||
|
|
.cname $procmux$641_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$true B[1]=$true B[2]=$true B[3]=$false B[4]=$true B[5]=$true B[6]=$false Y=$procmux$642_CMP
|
||
|
|
.cname $procmux$642_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$false B[1]=$true B[2]=$true B[3]=$false B[4]=$true B[5]=$true B[6]=$false Y=$procmux$643_CMP
|
||
|
|
.cname $procmux$643_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$true B[1]=$false B[2]=$true B[3]=$false B[4]=$true B[5]=$true B[6]=$false Y=$procmux$644_CMP
|
||
|
|
.cname $procmux$644_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$false B[1]=$false B[2]=$true B[3]=$false B[4]=$true B[5]=$true B[6]=$false Y=$procmux$645_CMP
|
||
|
|
.cname $procmux$645_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$true B[1]=$true B[2]=$false B[3]=$false B[4]=$true B[5]=$true B[6]=$false Y=$procmux$646_CMP
|
||
|
|
.cname $procmux$646_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$false B[1]=$true B[2]=$false B[3]=$false B[4]=$true B[5]=$true B[6]=$false Y=$procmux$647_CMP
|
||
|
|
.cname $procmux$647_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$true B[1]=$false B[2]=$false B[3]=$false B[4]=$true B[5]=$true B[6]=$false Y=$procmux$648_CMP
|
||
|
|
.cname $procmux$648_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$false B[1]=$false B[2]=$false B[3]=$false B[4]=$true B[5]=$true B[6]=$false Y=$procmux$649_CMP
|
||
|
|
.cname $procmux$649_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $mux A[0]=$procmux$62_Y[0] A[1]=$procmux$62_Y[1] A[2]=$procmux$62_Y[2] A[3]=$procmux$62_Y[3] A[4]=$procmux$62_Y[4] A[5]=$procmux$62_Y[5] A[6]=$procmux$62_Y[6] A[7]=$procmux$62_Y[7] A[8]=$procmux$62_Y[8] A[9]=$procmux$62_Y[9] A[10]=$procmux$62_Y[10] A[11]=$procmux$62_Y[11] A[12]=$procmux$62_Y[12] A[13]=$procmux$62_Y[13] A[14]=$procmux$62_Y[14] A[15]=$procmux$62_Y[15] A[16]=$procmux$62_Y[16] A[17]=$procmux$62_Y[17] A[18]=$procmux$62_Y[18] A[19]=$procmux$62_Y[19] A[20]=$procmux$62_Y[20] A[21]=$procmux$62_Y[21] A[22]=$procmux$62_Y[22] A[23]=$procmux$62_Y[23] A[24]=$procmux$62_Y[24] A[25]=$procmux$62_Y[25] A[26]=$procmux$62_Y[26] A[27]=$procmux$62_Y[27] A[28]=$procmux$62_Y[28] A[29]=$procmux$62_Y[29] A[30]=$procmux$62_Y[30] A[31]=$procmux$62_Y[31] B[0]=text_o[0] B[1]=text_o[1] B[2]=text_o[2] B[3]=text_o[3] B[4]=text_o[4] B[5]=text_o[5] B[6]=text_o[6] B[7]=text_o[7] B[8]=text_o[8] B[9]=text_o[9] B[10]=text_o[10] B[11]=text_o[11] B[12]=text_o[12] B[13]=text_o[13] B[14]=text_o[14] B[15]=text_o[15] B[16]=text_o[16] B[17]=text_o[17] B[18]=text_o[18] B[19]=text_o[19] B[20]=text_o[20] B[21]=text_o[21] B[22]=text_o[22] B[23]=text_o[23] B[24]=text_o[24] B[25]=text_o[25] B[26]=text_o[26] B[27]=text_o[27] B[28]=text_o[28] B[29]=text_o[29] B[30]=text_o[30] B[31]=text_o[31] S=$procmux$66_CMP Y[0]=$procmux$65_Y[0] Y[1]=$procmux$65_Y[1] Y[2]=$procmux$65_Y[2] Y[3]=$procmux$65_Y[3] Y[4]=$procmux$65_Y[4] Y[5]=$procmux$65_Y[5] Y[6]=$procmux$65_Y[6] Y[7]=$procmux$65_Y[7] Y[8]=$procmux$65_Y[8] Y[9]=$procmux$65_Y[9] Y[10]=$procmux$65_Y[10] Y[11]=$procmux$65_Y[11] Y[12]=$procmux$65_Y[12] Y[13]=$procmux$65_Y[13] Y[14]=$procmux$65_Y[14] Y[15]=$procmux$65_Y[15] Y[16]=$procmux$65_Y[16] Y[17]=$procmux$65_Y[17] Y[18]=$procmux$65_Y[18] Y[19]=$procmux$65_Y[19] Y[20]=$procmux$65_Y[20] Y[21]=$procmux$65_Y[21] Y[22]=$procmux$65_Y[22] Y[23]=$procmux$65_Y[23] Y[24]=$procmux$65_Y[24] Y[25]=$procmux$65_Y[25] Y[26]=$procmux$65_Y[26] Y[27]=$procmux$65_Y[27] Y[28]=$procmux$65_Y[28] Y[29]=$procmux$65_Y[29] Y[30]=$procmux$65_Y[30] Y[31]=$procmux$65_Y[31]
|
||
|
|
.cname $procmux$65
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:2143"
|
||
|
|
.param WIDTH 00000000000000000000000000100000
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$true B[1]=$true B[2]=$true B[3]=$true B[4]=$false B[5]=$true B[6]=$false Y=$procmux$650_CMP
|
||
|
|
.cname $procmux$650_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$false B[1]=$true B[2]=$true B[3]=$true B[4]=$false B[5]=$true B[6]=$false Y=$procmux$651_CMP
|
||
|
|
.cname $procmux$651_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$true B[1]=$false B[2]=$true B[3]=$true B[4]=$false B[5]=$true B[6]=$false Y=$procmux$652_CMP
|
||
|
|
.cname $procmux$652_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$false B[1]=$false B[2]=$true B[3]=$true B[4]=$false B[5]=$true B[6]=$false Y=$procmux$653_CMP
|
||
|
|
.cname $procmux$653_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$true B[1]=$true B[2]=$false B[3]=$true B[4]=$false B[5]=$true B[6]=$false Y=$procmux$654_CMP
|
||
|
|
.cname $procmux$654_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$false B[1]=$true B[2]=$false B[3]=$true B[4]=$false B[5]=$true B[6]=$false Y=$procmux$655_CMP
|
||
|
|
.cname $procmux$655_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$true B[1]=$false B[2]=$false B[3]=$true B[4]=$false B[5]=$true B[6]=$false Y=$procmux$656_CMP
|
||
|
|
.cname $procmux$656_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$false B[1]=$false B[2]=$false B[3]=$true B[4]=$false B[5]=$true B[6]=$false Y=$procmux$657_CMP
|
||
|
|
.cname $procmux$657_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$true B[1]=$true B[2]=$true B[3]=$false B[4]=$false B[5]=$true B[6]=$false Y=$procmux$658_CMP
|
||
|
|
.cname $procmux$658_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$false B[1]=$true B[2]=$true B[3]=$false B[4]=$false B[5]=$true B[6]=$false Y=$procmux$659_CMP
|
||
|
|
.cname $procmux$659_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$true B[1]=$false B[2]=$true B[3]=$false B[4]=$false B[5]=$true B[6]=$false Y=$procmux$660_CMP
|
||
|
|
.cname $procmux$660_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$false B[1]=$false B[2]=$true B[3]=$false B[4]=$false B[5]=$true B[6]=$false Y=$procmux$661_CMP
|
||
|
|
.cname $procmux$661_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$true B[1]=$true B[2]=$false B[3]=$false B[4]=$false B[5]=$true B[6]=$false Y=$procmux$662_CMP
|
||
|
|
.cname $procmux$662_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$false B[1]=$true B[2]=$false B[3]=$false B[4]=$false B[5]=$true B[6]=$false Y=$procmux$663_CMP
|
||
|
|
.cname $procmux$663_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$true B[1]=$false B[2]=$false B[3]=$false B[4]=$false B[5]=$true B[6]=$false Y=$procmux$664_CMP
|
||
|
|
.cname $procmux$664_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$false B[1]=$false B[2]=$false B[3]=$false B[4]=$false B[5]=$true B[6]=$false Y=$procmux$665_CMP
|
||
|
|
.cname $procmux$665_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$true B[1]=$true B[2]=$true B[3]=$true B[4]=$true B[5]=$false B[6]=$false Y=$procmux$666_CMP
|
||
|
|
.cname $procmux$666_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$false B[1]=$true B[2]=$true B[3]=$true B[4]=$true B[5]=$false B[6]=$false Y=$procmux$667_CMP
|
||
|
|
.cname $procmux$667_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$true B[1]=$false B[2]=$true B[3]=$true B[4]=$true B[5]=$false B[6]=$false Y=$procmux$668_CMP
|
||
|
|
.cname $procmux$668_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$false B[1]=$false B[2]=$true B[3]=$true B[4]=$true B[5]=$false B[6]=$false Y=$procmux$669_CMP
|
||
|
|
.cname $procmux$669_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$true B[1]=$true B[2]=$false B[3]=$true B[4]=$true B[5]=$false B[6]=$false Y=$procmux$670_CMP
|
||
|
|
.cname $procmux$670_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$false B[1]=$true B[2]=$false B[3]=$true B[4]=$true B[5]=$false B[6]=$false Y=$procmux$671_CMP
|
||
|
|
.cname $procmux$671_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$true B[1]=$false B[2]=$false B[3]=$true B[4]=$true B[5]=$false B[6]=$false Y=$procmux$672_CMP
|
||
|
|
.cname $procmux$672_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$false B[1]=$false B[2]=$false B[3]=$true B[4]=$true B[5]=$false B[6]=$false Y=$procmux$673_CMP
|
||
|
|
.cname $procmux$673_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$true B[1]=$true B[2]=$true B[3]=$false B[4]=$true B[5]=$false B[6]=$false Y=$procmux$674_CMP
|
||
|
|
.cname $procmux$674_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$false B[1]=$true B[2]=$true B[3]=$false B[4]=$true B[5]=$false B[6]=$false Y=$procmux$675_CMP
|
||
|
|
.cname $procmux$675_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$true B[1]=$false B[2]=$true B[3]=$false B[4]=$true B[5]=$false B[6]=$false Y=$procmux$676_CMP
|
||
|
|
.cname $procmux$676_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$false B[1]=$false B[2]=$true B[3]=$false B[4]=$true B[5]=$false B[6]=$false Y=$procmux$677_CMP
|
||
|
|
.cname $procmux$677_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$true B[1]=$true B[2]=$false B[3]=$false B[4]=$true B[5]=$false B[6]=$false Y=$procmux$678_CMP
|
||
|
|
.cname $procmux$678_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$false B[1]=$true B[2]=$false B[3]=$false B[4]=$true B[5]=$false B[6]=$false Y=$procmux$679_CMP
|
||
|
|
.cname $procmux$679_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $mux A[0]=$procmux$65_Y[0] A[1]=$procmux$65_Y[1] A[2]=$procmux$65_Y[2] A[3]=$procmux$65_Y[3] A[4]=$procmux$65_Y[4] A[5]=$procmux$65_Y[5] A[6]=$procmux$65_Y[6] A[7]=$procmux$65_Y[7] A[8]=$procmux$65_Y[8] A[9]=$procmux$65_Y[9] A[10]=$procmux$65_Y[10] A[11]=$procmux$65_Y[11] A[12]=$procmux$65_Y[12] A[13]=$procmux$65_Y[13] A[14]=$procmux$65_Y[14] A[15]=$procmux$65_Y[15] A[16]=$procmux$65_Y[16] A[17]=$procmux$65_Y[17] A[18]=$procmux$65_Y[18] A[19]=$procmux$65_Y[19] A[20]=$procmux$65_Y[20] A[21]=$procmux$65_Y[21] A[22]=$procmux$65_Y[22] A[23]=$procmux$65_Y[23] A[24]=$procmux$65_Y[24] A[25]=$procmux$65_Y[25] A[26]=$procmux$65_Y[26] A[27]=$procmux$65_Y[27] A[28]=$procmux$65_Y[28] A[29]=$procmux$65_Y[29] A[30]=$procmux$65_Y[30] A[31]=$procmux$65_Y[31] B[0]=$false B[1]=$false B[2]=$false B[3]=$false B[4]=$false B[5]=$false B[6]=$false B[7]=$false B[8]=$false B[9]=$false B[10]=$false B[11]=$false B[12]=$false B[13]=$false B[14]=$false B[15]=$false B[16]=$false B[17]=$false B[18]=$false B[19]=$false B[20]=$false B[21]=$false B[22]=$false B[23]=$false B[24]=$false B[25]=$false B[26]=$false B[27]=$false B[28]=$false B[29]=$false B[30]=$false B[31]=$false S=$procmux$69_CMP Y[0]=$procmux$68_Y[0] Y[1]=$procmux$68_Y[1] Y[2]=$procmux$68_Y[2] Y[3]=$procmux$68_Y[3] Y[4]=$procmux$68_Y[4] Y[5]=$procmux$68_Y[5] Y[6]=$procmux$68_Y[6] Y[7]=$procmux$68_Y[7] Y[8]=$procmux$68_Y[8] Y[9]=$procmux$68_Y[9] Y[10]=$procmux$68_Y[10] Y[11]=$procmux$68_Y[11] Y[12]=$procmux$68_Y[12] Y[13]=$procmux$68_Y[13] Y[14]=$procmux$68_Y[14] Y[15]=$procmux$68_Y[15] Y[16]=$procmux$68_Y[16] Y[17]=$procmux$68_Y[17] Y[18]=$procmux$68_Y[18] Y[19]=$procmux$68_Y[19] Y[20]=$procmux$68_Y[20] Y[21]=$procmux$68_Y[21] Y[22]=$procmux$68_Y[22] Y[23]=$procmux$68_Y[23] Y[24]=$procmux$68_Y[24] Y[25]=$procmux$68_Y[25] Y[26]=$procmux$68_Y[26] Y[27]=$procmux$68_Y[27] Y[28]=$procmux$68_Y[28] Y[29]=$procmux$68_Y[29] Y[30]=$procmux$68_Y[30] Y[31]=$procmux$68_Y[31]
|
||
|
|
.cname $procmux$68
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:2136"
|
||
|
|
.param WIDTH 00000000000000000000000000100000
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$true B[1]=$false B[2]=$false B[3]=$false B[4]=$true B[5]=$false B[6]=$false Y=$procmux$680_CMP
|
||
|
|
.cname $procmux$680_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$false B[1]=$false B[2]=$false B[3]=$false B[4]=$true B[5]=$false B[6]=$false Y=$procmux$681_CMP
|
||
|
|
.cname $procmux$681_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$true B[1]=$false B[2]=$false B[3]=$true B[4]=$false B[5]=$false B[6]=$false Y=$procmux$682_CMP
|
||
|
|
.cname $procmux$682_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $mux A[0]=$procmux$617_Y[0] A[1]=$procmux$617_Y[1] A[2]=$procmux$617_Y[2] A[3]=$procmux$617_Y[3] A[4]=$procmux$617_Y[4] A[5]=$procmux$617_Y[5] A[6]=$procmux$617_Y[6] A[7]=$procmux$617_Y[7] A[8]=$procmux$617_Y[8] A[9]=$procmux$617_Y[9] A[10]=$procmux$617_Y[10] A[11]=$procmux$617_Y[11] A[12]=$procmux$617_Y[12] A[13]=$procmux$617_Y[13] A[14]=$procmux$617_Y[14] A[15]=$procmux$617_Y[15] A[16]=$procmux$617_Y[16] A[17]=$procmux$617_Y[17] A[18]=$procmux$617_Y[18] A[19]=$procmux$617_Y[19] A[20]=$procmux$617_Y[20] A[21]=$procmux$617_Y[21] A[22]=$procmux$617_Y[22] A[23]=$procmux$617_Y[23] A[24]=$procmux$617_Y[24] A[25]=$procmux$617_Y[25] A[26]=$procmux$617_Y[26] A[27]=$procmux$617_Y[27] A[28]=$procmux$617_Y[28] A[29]=$procmux$617_Y[29] A[30]=$procmux$617_Y[30] A[31]=$procmux$617_Y[31] B[0]=$false B[1]=$false B[2]=$false B[3]=$false B[4]=$false B[5]=$false B[6]=$false B[7]=$false B[8]=$false B[9]=$false B[10]=$false B[11]=$false B[12]=$false B[13]=$false B[14]=$false B[15]=$false B[16]=$false B[17]=$false B[18]=$false B[19]=$false B[20]=$false B[21]=$false B[22]=$false B[23]=$false B[24]=$false B[25]=$false B[26]=$false B[27]=$false B[28]=$false B[29]=$false B[30]=$false B[31]=$false S=$procmux$685_CMP Y[0]=$procmux$684_Y[0] Y[1]=$procmux$684_Y[1] Y[2]=$procmux$684_Y[2] Y[3]=$procmux$684_Y[3] Y[4]=$procmux$684_Y[4] Y[5]=$procmux$684_Y[5] Y[6]=$procmux$684_Y[6] Y[7]=$procmux$684_Y[7] Y[8]=$procmux$684_Y[8] Y[9]=$procmux$684_Y[9] Y[10]=$procmux$684_Y[10] Y[11]=$procmux$684_Y[11] Y[12]=$procmux$684_Y[12] Y[13]=$procmux$684_Y[13] Y[14]=$procmux$684_Y[14] Y[15]=$procmux$684_Y[15] Y[16]=$procmux$684_Y[16] Y[17]=$procmux$684_Y[17] Y[18]=$procmux$684_Y[18] Y[19]=$procmux$684_Y[19] Y[20]=$procmux$684_Y[20] Y[21]=$procmux$684_Y[21] Y[22]=$procmux$684_Y[22] Y[23]=$procmux$684_Y[23] Y[24]=$procmux$684_Y[24] Y[25]=$procmux$684_Y[25] Y[26]=$procmux$684_Y[26] Y[27]=$procmux$684_Y[27] Y[28]=$procmux$684_Y[28] Y[29]=$procmux$684_Y[29] Y[30]=$procmux$684_Y[30] Y[31]=$procmux$684_Y[31]
|
||
|
|
.cname $procmux$684
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:150"
|
||
|
|
.param WIDTH 00000000000000000000000000100000
|
||
|
|
.subckt $pmux A[0]=W8[0] A[1]=W8[1] A[2]=W8[2] A[3]=W8[3] A[4]=W8[4] A[5]=W8[5] A[6]=W8[6] A[7]=W8[7] A[8]=W8[8] A[9]=W8[9] A[10]=W8[10] A[11]=W8[11] A[12]=W8[12] A[13]=W8[13] A[14]=W8[14] A[15]=W8[15] A[16]=W8[16] A[17]=W8[17] A[18]=W8[18] A[19]=W8[19] A[20]=W8[20] A[21]=W8[21] A[22]=W8[22] A[23]=W8[23] A[24]=W8[24] A[25]=W8[25] A[26]=W8[26] A[27]=W8[27] A[28]=W8[28] A[29]=W8[29] A[30]=W8[30] A[31]=W8[31] B[0]=W9[0] B[1]=W9[1] B[2]=W9[2] B[3]=W9[3] B[4]=W9[4] B[5]=W9[5] B[6]=W9[6] B[7]=W9[7] B[8]=W9[8] B[9]=W9[9] B[10]=W9[10] B[11]=W9[11] B[12]=W9[12] B[13]=W9[13] B[14]=W9[14] B[15]=W9[15] B[16]=W9[16] B[17]=W9[17] B[18]=W9[18] B[19]=W9[19] B[20]=W9[20] B[21]=W9[21] B[22]=W9[22] B[23]=W9[23] B[24]=W9[24] B[25]=W9[25] B[26]=W9[26] B[27]=W9[27] B[28]=W9[28] B[29]=W9[29] B[30]=W9[30] B[31]=W9[31] B[32]=W9[0] B[33]=W9[1] B[34]=W9[2] B[35]=W9[3] B[36]=W9[4] B[37]=W9[5] B[38]=W9[6] B[39]=W9[7] B[40]=W9[8] B[41]=W9[9] B[42]=W9[10] B[43]=W9[11] B[44]=W9[12] B[45]=W9[13] B[46]=W9[14] B[47]=W9[15] B[48]=W9[16] B[49]=W9[17] B[50]=W9[18] B[51]=W9[19] B[52]=W9[20] B[53]=W9[21] B[54]=W9[22] B[55]=W9[23] B[56]=W9[24] B[57]=W9[25] B[58]=W9[26] B[59]=W9[27] B[60]=W9[28] B[61]=W9[29] B[62]=W9[30] B[63]=W9[31] B[64]=W9[0] B[65]=W9[1] B[66]=W9[2] B[67]=W9[3] B[68]=W9[4] B[69]=W9[5] B[70]=W9[6] B[71]=W9[7] B[72]=W9[8] B[73]=W9[9] B[74]=W9[10] B[75]=W9[11] B[76]=W9[12] B[77]=W9[13] B[78]=W9[14] B[79]=W9[15] B[80]=W9[16] B[81]=W9[17] B[82]=W9[18] B[83]=W9[19] B[84]=W9[20] B[85]=W9[21] B[86]=W9[22] B[87]=W9[23] B[88]=W9[24] B[89]=W9[25] B[90]=W9[26] B[91]=W9[27] B[92]=W9[28] B[93]=W9[29] B[94]=W9[30] B[95]=W9[31] B[96]=W9[0] B[97]=W9[1] B[98]=W9[2] B[99]=W9[3] B[100]=W9[4] B[101]=W9[5] B[102]=W9[6] B[103]=W9[7] B[104]=W9[8] B[105]=W9[9] B[106]=W9[10] B[107]=W9[11] B[108]=W9[12] B[109]=W9[13] B[110]=W9[14] B[111]=W9[15] B[112]=W9[16] B[113]=W9[17] B[114]=W9[18] B[115]=W9[19] B[116]=W9[20] B[117]=W9[21] B[118]=W9[22] B[119]=W9[23] B[120]=W9[24] B[121]=W9[25] B[122]=W9[26] B[123]=W9[27] B[124]=W9[28] B[125]=W9[29] B[126]=W9[30] B[127]=W9[31] B[128]=W9[0] B[129]=W9[1] B[130]=W9[2] B[131]=W9[3] B[132]=W9[4] B[133]=W9[5] B[134]=W9[6] B[135]=W9[7] B[136]=W9[8] B[137]=W9[9] B[138]=W9[10] B[139]=W9[11] B[140]=W9[12] B[141]=W9[13] B[142]=W9[14] B[143]=W9[15] B[144]=W9[16] B[145]=W9[17] B[146]=W9[18] B[147]=W9[19] B[148]=W9[20] B[149]=W9[21] B[150]=W9[22] B[151]=W9[23] B[152]=W9[24] B[153]=W9[25] B[154]=W9[26] B[155]=W9[27] B[156]=W9[28] B[157]=W9[29] B[158]=W9[30] B[159]=W9[31] B[160]=W9[0] B[161]=W9[1] B[162]=W9[2] B[163]=W9[3] B[164]=W9[4] B[165]=W9[5] B[166]=W9[6] B[167]=W9[7] B[168]=W9[8] B[169]=W9[9] B[170]=W9[10] B[171]=W9[11] B[172]=W9[12] B[173]=W9[13] B[174]=W9[14] B[175]=W9[15] B[176]=W9[16] B[177]=W9[17] B[178]=W9[18] B[179]=W9[19] B[180]=W9[20] B[181]=W9[21] B[182]=W9[22] B[183]=W9[23] B[184]=W9[24] B[185]=W9[25] B[186]=W9[26] B[187]=W9[27] B[188]=W9[28] B[189]=W9[29] B[190]=W9[30] B[191]=W9[31] B[192]=W9[0] B[193]=W9[1] B[194]=W9[2] B[195]=W9[3] B[196]=W9[4] B[197]=W9[5] B[198]=W9[6] B[199]=W9[7] B[200]=W9[8] B[201]=W9[9] B[202]=W9[10] B[203]=W9[11] B[204]=W9[12] B[205]=W9[13] B[206]=W9[14] B[207]=W9[15] B[208]=W9[16] B[209]=W9[17] B[210]=W9[18] B[211]=W9[19] B[212]=W9[20] B[213]=W9[21] B[214]=W9[22] B[215]=W9[23] B[216]=W9[24] B[217]=W9[25] B[218]=W9[26] B[219]=W9[27] B[220]=W9[28] B[221]=W9[29] B[222]=W9[30] B[223]=W9[31] B[224]=W9[0] B[225]=W9[1] B[226]=W9[2] B[227]=W9[3] B[228]=W9[4] B[229]=W9[5] B[230]=W9[6] B[231]=W9[7] B[232]=W9[8] B[233]=W9[9] B[234]=W9[10] B[235]=W9[11] B[236]=W9[12] B[237]=W9[13] B[238]=W9[14] B[239]=W9[15] B[240]=W9[16] B[241]=W9[17] B[242]=W9[18] B[243]=W9[19] B[244]=W9[20] B[245]=W9[21] B[246]=W9[22] B[247]=W9[23] B[248]=W9[24] B[249]=W9[25] B[250]=W9[26] B[251]=W9[27] B[252]=W9[28] B[253]=W9[29] B[254]=W9[30] B[255]=W9[31] B[256]=W9[0] B[257]=W9[1] B[258]=W9[2] B[259]=W9[3] B[260]=W9[4] B[261]=W9[5] B[262]=W9[6] B[263]=W9[7] B[264]=W9[8] B[265]=W9[9] B[266]=W9[10] B[267]=W9[11] B[268]=W9[12] B[269]=W9[13] B[270]=W9[14] B[271]=W9[15] B[272]=W9[16] B[273]=W9[17] B[274]=W9[18] B[275]=W9[19] B[276]=W9[20] B[277]=
|
||
|
|
.cname $procmux$688
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param S_WIDTH 00000000000000000000000001000001
|
||
|
|
.param WIDTH 00000000000000000000000000100000
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$true B[1]=$true B[2]=$true B[3]=$true B[4]=$false B[5]=$false B[6]=$true Y=$procmux$689_CMP
|
||
|
|
.cname $procmux$689_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$false B[1]=$true B[2]=$true B[3]=$true B[4]=$false B[5]=$false B[6]=$true Y=$procmux$690_CMP
|
||
|
|
.cname $procmux$690_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$true B[1]=$false B[2]=$true B[3]=$true B[4]=$false B[5]=$false B[6]=$true Y=$procmux$691_CMP
|
||
|
|
.cname $procmux$691_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$false B[1]=$false B[2]=$true B[3]=$true B[4]=$false B[5]=$false B[6]=$true Y=$procmux$692_CMP
|
||
|
|
.cname $procmux$692_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$true B[1]=$true B[2]=$false B[3]=$true B[4]=$false B[5]=$false B[6]=$true Y=$procmux$693_CMP
|
||
|
|
.cname $procmux$693_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$false B[1]=$true B[2]=$false B[3]=$true B[4]=$false B[5]=$false B[6]=$true Y=$procmux$694_CMP
|
||
|
|
.cname $procmux$694_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$true B[1]=$false B[2]=$false B[3]=$true B[4]=$false B[5]=$false B[6]=$true Y=$procmux$695_CMP
|
||
|
|
.cname $procmux$695_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$false B[1]=$false B[2]=$false B[3]=$true B[4]=$false B[5]=$false B[6]=$true Y=$procmux$696_CMP
|
||
|
|
.cname $procmux$696_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$true B[1]=$true B[2]=$true B[3]=$false B[4]=$false B[5]=$false B[6]=$true Y=$procmux$697_CMP
|
||
|
|
.cname $procmux$697_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$false B[1]=$true B[2]=$true B[3]=$false B[4]=$false B[5]=$false B[6]=$true Y=$procmux$698_CMP
|
||
|
|
.cname $procmux$698_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$true B[1]=$false B[2]=$true B[3]=$false B[4]=$false B[5]=$false B[6]=$true Y=$procmux$699_CMP
|
||
|
|
.cname $procmux$699_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$false B[1]=$false B[2]=$true B[3]=$false B[4]=$false B[5]=$false B[6]=$true Y=$procmux$700_CMP
|
||
|
|
.cname $procmux$700_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$true B[1]=$true B[2]=$false B[3]=$false B[4]=$false B[5]=$false B[6]=$true Y=$procmux$701_CMP
|
||
|
|
.cname $procmux$701_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$false B[1]=$true B[2]=$false B[3]=$false B[4]=$false B[5]=$false B[6]=$true Y=$procmux$702_CMP
|
||
|
|
.cname $procmux$702_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$true B[1]=$false B[2]=$false B[3]=$false B[4]=$false B[5]=$false B[6]=$true Y=$procmux$703_CMP
|
||
|
|
.cname $procmux$703_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$false B[1]=$false B[2]=$false B[3]=$false B[4]=$false B[5]=$false B[6]=$true Y=$procmux$704_CMP
|
||
|
|
.cname $procmux$704_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$true B[1]=$true B[2]=$true B[3]=$true B[4]=$true B[5]=$true B[6]=$false Y=$procmux$705_CMP
|
||
|
|
.cname $procmux$705_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$false B[1]=$true B[2]=$true B[3]=$true B[4]=$true B[5]=$true B[6]=$false Y=$procmux$706_CMP
|
||
|
|
.cname $procmux$706_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$true B[1]=$false B[2]=$true B[3]=$true B[4]=$true B[5]=$true B[6]=$false Y=$procmux$707_CMP
|
||
|
|
.cname $procmux$707_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$false B[1]=$false B[2]=$true B[3]=$true B[4]=$true B[5]=$true B[6]=$false Y=$procmux$708_CMP
|
||
|
|
.cname $procmux$708_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$true B[1]=$true B[2]=$false B[3]=$true B[4]=$true B[5]=$true B[6]=$false Y=$procmux$709_CMP
|
||
|
|
.cname $procmux$709_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $mux A[0]=$false A[1]=$true A[2]=$true A[3]=$false A[4]=$true A[5]=$false A[6]=$true A[7]=$true A[8]=$true A[9]=$false A[10]=$false A[11]=$false A[12]=$false A[13]=$false A[14]=$true A[15]=$true A[16]=$false A[17]=$true A[18]=$false A[19]=$false A[20]=$false A[21]=$true A[22]=$true A[23]=$false A[24]=$false A[25]=$true A[26]=$false A[27]=$true A[28]=$false A[29]=$false A[30]=$true A[31]=$true B[0]=$false B[1]=$false B[2]=$true B[3]=$true B[4]=$true B[5]=$false B[6]=$true B[7]=$true B[8]=$false B[9]=$false B[10]=$true B[11]=$true B[12]=$true B[13]=$true B[14]=$false B[15]=$true B[16]=$true B[17]=$true B[18]=$false B[19]=$true B[20]=$true B[21]=$false B[22]=$false B[23]=$false B[24]=$true B[25]=$true B[26]=$true B[27]=$true B[28]=$false B[29]=$false B[30]=$false B[31]=$true S=$procmux$72_CMP Y[0]=$procmux$71_Y[0] Y[1]=$procmux$71_Y[1] Y[2]=$procmux$71_Y[2] Y[3]=$procmux$71_Y[3] Y[4]=$procmux$71_Y[4] Y[5]=$procmux$71_Y[5] Y[6]=$procmux$71_Y[6] Y[7]=$procmux$71_Y[7] Y[8]=$procmux$71_Y[8] Y[9]=$procmux$71_Y[9] Y[10]=$procmux$71_Y[10] Y[11]=$procmux$71_Y[11] Y[12]=$procmux$71_Y[12] Y[13]=$procmux$71_Y[13] Y[14]=$procmux$71_Y[14] Y[15]=$procmux$71_Y[15] Y[16]=$procmux$71_Y[16] Y[17]=$procmux$71_Y[17] Y[18]=$procmux$71_Y[18] Y[19]=$procmux$71_Y[19] Y[20]=$procmux$71_Y[20] Y[21]=$procmux$71_Y[21] Y[22]=$procmux$71_Y[22] Y[23]=$procmux$71_Y[23] Y[24]=$procmux$71_Y[24] Y[25]=$procmux$71_Y[25] Y[26]=$procmux$71_Y[26] Y[27]=$procmux$71_Y[27] Y[28]=$procmux$71_Y[28] Y[29]=$procmux$71_Y[29] Y[30]=$procmux$71_Y[30] Y[31]=$procmux$71_Y[31]
|
||
|
|
.cname $procmux$71
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:2124"
|
||
|
|
.param WIDTH 00000000000000000000000000100000
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$false B[1]=$true B[2]=$false B[3]=$true B[4]=$true B[5]=$true B[6]=$false Y=$procmux$710_CMP
|
||
|
|
.cname $procmux$710_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$true B[1]=$false B[2]=$false B[3]=$true B[4]=$true B[5]=$true B[6]=$false Y=$procmux$711_CMP
|
||
|
|
.cname $procmux$711_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$false B[1]=$false B[2]=$false B[3]=$true B[4]=$true B[5]=$true B[6]=$false Y=$procmux$712_CMP
|
||
|
|
.cname $procmux$712_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$true B[1]=$true B[2]=$true B[3]=$false B[4]=$true B[5]=$true B[6]=$false Y=$procmux$713_CMP
|
||
|
|
.cname $procmux$713_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$false B[1]=$true B[2]=$true B[3]=$false B[4]=$true B[5]=$true B[6]=$false Y=$procmux$714_CMP
|
||
|
|
.cname $procmux$714_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$true B[1]=$false B[2]=$true B[3]=$false B[4]=$true B[5]=$true B[6]=$false Y=$procmux$715_CMP
|
||
|
|
.cname $procmux$715_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$false B[1]=$false B[2]=$true B[3]=$false B[4]=$true B[5]=$true B[6]=$false Y=$procmux$716_CMP
|
||
|
|
.cname $procmux$716_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$true B[1]=$true B[2]=$false B[3]=$false B[4]=$true B[5]=$true B[6]=$false Y=$procmux$717_CMP
|
||
|
|
.cname $procmux$717_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$false B[1]=$true B[2]=$false B[3]=$false B[4]=$true B[5]=$true B[6]=$false Y=$procmux$718_CMP
|
||
|
|
.cname $procmux$718_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$true B[1]=$false B[2]=$false B[3]=$false B[4]=$true B[5]=$true B[6]=$false Y=$procmux$719_CMP
|
||
|
|
.cname $procmux$719_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$false B[1]=$false B[2]=$false B[3]=$false B[4]=$true B[5]=$true B[6]=$false Y=$procmux$720_CMP
|
||
|
|
.cname $procmux$720_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$true B[1]=$true B[2]=$true B[3]=$true B[4]=$false B[5]=$true B[6]=$false Y=$procmux$721_CMP
|
||
|
|
.cname $procmux$721_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$false B[1]=$true B[2]=$true B[3]=$true B[4]=$false B[5]=$true B[6]=$false Y=$procmux$722_CMP
|
||
|
|
.cname $procmux$722_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$true B[1]=$false B[2]=$true B[3]=$true B[4]=$false B[5]=$true B[6]=$false Y=$procmux$723_CMP
|
||
|
|
.cname $procmux$723_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$false B[1]=$false B[2]=$true B[3]=$true B[4]=$false B[5]=$true B[6]=$false Y=$procmux$724_CMP
|
||
|
|
.cname $procmux$724_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$true B[1]=$true B[2]=$false B[3]=$true B[4]=$false B[5]=$true B[6]=$false Y=$procmux$725_CMP
|
||
|
|
.cname $procmux$725_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$false B[1]=$true B[2]=$false B[3]=$true B[4]=$false B[5]=$true B[6]=$false Y=$procmux$726_CMP
|
||
|
|
.cname $procmux$726_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$true B[1]=$false B[2]=$false B[3]=$true B[4]=$false B[5]=$true B[6]=$false Y=$procmux$727_CMP
|
||
|
|
.cname $procmux$727_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$false B[1]=$false B[2]=$false B[3]=$true B[4]=$false B[5]=$true B[6]=$false Y=$procmux$728_CMP
|
||
|
|
.cname $procmux$728_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$true B[1]=$true B[2]=$true B[3]=$false B[4]=$false B[5]=$true B[6]=$false Y=$procmux$729_CMP
|
||
|
|
.cname $procmux$729_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$false B[1]=$true B[2]=$true B[3]=$false B[4]=$false B[5]=$true B[6]=$false Y=$procmux$730_CMP
|
||
|
|
.cname $procmux$730_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$true B[1]=$false B[2]=$true B[3]=$false B[4]=$false B[5]=$true B[6]=$false Y=$procmux$731_CMP
|
||
|
|
.cname $procmux$731_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$false B[1]=$false B[2]=$true B[3]=$false B[4]=$false B[5]=$true B[6]=$false Y=$procmux$732_CMP
|
||
|
|
.cname $procmux$732_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$true B[1]=$true B[2]=$false B[3]=$false B[4]=$false B[5]=$true B[6]=$false Y=$procmux$733_CMP
|
||
|
|
.cname $procmux$733_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$false B[1]=$true B[2]=$false B[3]=$false B[4]=$false B[5]=$true B[6]=$false Y=$procmux$734_CMP
|
||
|
|
.cname $procmux$734_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$true B[1]=$false B[2]=$false B[3]=$false B[4]=$false B[5]=$true B[6]=$false Y=$procmux$735_CMP
|
||
|
|
.cname $procmux$735_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$false B[1]=$false B[2]=$false B[3]=$false B[4]=$false B[5]=$true B[6]=$false Y=$procmux$736_CMP
|
||
|
|
.cname $procmux$736_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$true B[1]=$true B[2]=$true B[3]=$true B[4]=$true B[5]=$false B[6]=$false Y=$procmux$737_CMP
|
||
|
|
.cname $procmux$737_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$false B[1]=$true B[2]=$true B[3]=$true B[4]=$true B[5]=$false B[6]=$false Y=$procmux$738_CMP
|
||
|
|
.cname $procmux$738_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$true B[1]=$false B[2]=$true B[3]=$true B[4]=$true B[5]=$false B[6]=$false Y=$procmux$739_CMP
|
||
|
|
.cname $procmux$739_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $mux A[0]=$procmux$71_Y[0] A[1]=$procmux$71_Y[1] A[2]=$procmux$71_Y[2] A[3]=$procmux$71_Y[3] A[4]=$procmux$71_Y[4] A[5]=$procmux$71_Y[5] A[6]=$procmux$71_Y[6] A[7]=$procmux$71_Y[7] A[8]=$procmux$71_Y[8] A[9]=$procmux$71_Y[9] A[10]=$procmux$71_Y[10] A[11]=$procmux$71_Y[11] A[12]=$procmux$71_Y[12] A[13]=$procmux$71_Y[13] A[14]=$procmux$71_Y[14] A[15]=$procmux$71_Y[15] A[16]=$procmux$71_Y[16] A[17]=$procmux$71_Y[17] A[18]=$procmux$71_Y[18] A[19]=$procmux$71_Y[19] A[20]=$procmux$71_Y[20] A[21]=$procmux$71_Y[21] A[22]=$procmux$71_Y[22] A[23]=$procmux$71_Y[23] A[24]=$procmux$71_Y[24] A[25]=$procmux$71_Y[25] A[26]=$procmux$71_Y[26] A[27]=$procmux$71_Y[27] A[28]=$procmux$71_Y[28] A[29]=$procmux$71_Y[29] A[30]=$procmux$71_Y[30] A[31]=$procmux$71_Y[31] B[0]=$true B[1]=$false B[2]=$false B[3]=$false B[4]=$false B[5]=$true B[6]=$false B[7]=$true B[8]=$true B[9]=$true B[10]=$false B[11]=$true B[12]=$false B[13]=$true B[14]=$true B[15]=$true B[16]=$true B[17]=$false B[18]=$false B[19]=$true B[20]=$true B[21]=$false B[22]=$true B[23]=$true B[24]=$false B[25]=$true B[26]=$true B[27]=$true B[28]=$false B[29]=$true B[30]=$true B[31]=$false S=$procmux$75_CMP Y[0]=$procmux$74_Y[0] Y[1]=$procmux$74_Y[1] Y[2]=$procmux$74_Y[2] Y[3]=$procmux$74_Y[3] Y[4]=$procmux$74_Y[4] Y[5]=$procmux$74_Y[5] Y[6]=$procmux$74_Y[6] Y[7]=$procmux$74_Y[7] Y[8]=$procmux$74_Y[8] Y[9]=$procmux$74_Y[9] Y[10]=$procmux$74_Y[10] Y[11]=$procmux$74_Y[11] Y[12]=$procmux$74_Y[12] Y[13]=$procmux$74_Y[13] Y[14]=$procmux$74_Y[14] Y[15]=$procmux$74_Y[15] Y[16]=$procmux$74_Y[16] Y[17]=$procmux$74_Y[17] Y[18]=$procmux$74_Y[18] Y[19]=$procmux$74_Y[19] Y[20]=$procmux$74_Y[20] Y[21]=$procmux$74_Y[21] Y[22]=$procmux$74_Y[22] Y[23]=$procmux$74_Y[23] Y[24]=$procmux$74_Y[24] Y[25]=$procmux$74_Y[25] Y[26]=$procmux$74_Y[26] Y[27]=$procmux$74_Y[27] Y[28]=$procmux$74_Y[28] Y[29]=$procmux$74_Y[29] Y[30]=$procmux$74_Y[30] Y[31]=$procmux$74_Y[31]
|
||
|
|
.cname $procmux$74
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:2121"
|
||
|
|
.param WIDTH 00000000000000000000000000100000
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$false B[1]=$false B[2]=$true B[3]=$true B[4]=$true B[5]=$false B[6]=$false Y=$procmux$740_CMP
|
||
|
|
.cname $procmux$740_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$true B[1]=$true B[2]=$false B[3]=$true B[4]=$true B[5]=$false B[6]=$false Y=$procmux$741_CMP
|
||
|
|
.cname $procmux$741_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$false B[1]=$true B[2]=$false B[3]=$true B[4]=$true B[5]=$false B[6]=$false Y=$procmux$742_CMP
|
||
|
|
.cname $procmux$742_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$true B[1]=$false B[2]=$false B[3]=$true B[4]=$true B[5]=$false B[6]=$false Y=$procmux$743_CMP
|
||
|
|
.cname $procmux$743_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$false B[1]=$false B[2]=$false B[3]=$true B[4]=$true B[5]=$false B[6]=$false Y=$procmux$744_CMP
|
||
|
|
.cname $procmux$744_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$true B[1]=$true B[2]=$true B[3]=$false B[4]=$true B[5]=$false B[6]=$false Y=$procmux$745_CMP
|
||
|
|
.cname $procmux$745_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$false B[1]=$true B[2]=$true B[3]=$false B[4]=$true B[5]=$false B[6]=$false Y=$procmux$746_CMP
|
||
|
|
.cname $procmux$746_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$true B[1]=$false B[2]=$true B[3]=$false B[4]=$true B[5]=$false B[6]=$false Y=$procmux$747_CMP
|
||
|
|
.cname $procmux$747_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$false B[1]=$false B[2]=$true B[3]=$false B[4]=$true B[5]=$false B[6]=$false Y=$procmux$748_CMP
|
||
|
|
.cname $procmux$748_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$true B[1]=$true B[2]=$false B[3]=$false B[4]=$true B[5]=$false B[6]=$false Y=$procmux$749_CMP
|
||
|
|
.cname $procmux$749_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$false B[1]=$true B[2]=$false B[3]=$false B[4]=$true B[5]=$false B[6]=$false Y=$procmux$750_CMP
|
||
|
|
.cname $procmux$750_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$true B[1]=$false B[2]=$false B[3]=$false B[4]=$true B[5]=$false B[6]=$false Y=$procmux$751_CMP
|
||
|
|
.cname $procmux$751_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$false B[1]=$false B[2]=$false B[3]=$false B[4]=$true B[5]=$false B[6]=$false Y=$procmux$752_CMP
|
||
|
|
.cname $procmux$752_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$false B[1]=$false B[2]=$false B[3]=$true B[4]=$false B[5]=$false B[6]=$false Y=$procmux$753_CMP
|
||
|
|
.cname $procmux$753_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $mux A[0]=$procmux$688_Y[0] A[1]=$procmux$688_Y[1] A[2]=$procmux$688_Y[2] A[3]=$procmux$688_Y[3] A[4]=$procmux$688_Y[4] A[5]=$procmux$688_Y[5] A[6]=$procmux$688_Y[6] A[7]=$procmux$688_Y[7] A[8]=$procmux$688_Y[8] A[9]=$procmux$688_Y[9] A[10]=$procmux$688_Y[10] A[11]=$procmux$688_Y[11] A[12]=$procmux$688_Y[12] A[13]=$procmux$688_Y[13] A[14]=$procmux$688_Y[14] A[15]=$procmux$688_Y[15] A[16]=$procmux$688_Y[16] A[17]=$procmux$688_Y[17] A[18]=$procmux$688_Y[18] A[19]=$procmux$688_Y[19] A[20]=$procmux$688_Y[20] A[21]=$procmux$688_Y[21] A[22]=$procmux$688_Y[22] A[23]=$procmux$688_Y[23] A[24]=$procmux$688_Y[24] A[25]=$procmux$688_Y[25] A[26]=$procmux$688_Y[26] A[27]=$procmux$688_Y[27] A[28]=$procmux$688_Y[28] A[29]=$procmux$688_Y[29] A[30]=$procmux$688_Y[30] A[31]=$procmux$688_Y[31] B[0]=$false B[1]=$false B[2]=$false B[3]=$false B[4]=$false B[5]=$false B[6]=$false B[7]=$false B[8]=$false B[9]=$false B[10]=$false B[11]=$false B[12]=$false B[13]=$false B[14]=$false B[15]=$false B[16]=$false B[17]=$false B[18]=$false B[19]=$false B[20]=$false B[21]=$false B[22]=$false B[23]=$false B[24]=$false B[25]=$false B[26]=$false B[27]=$false B[28]=$false B[29]=$false B[30]=$false B[31]=$false S=$procmux$756_CMP Y[0]=$procmux$755_Y[0] Y[1]=$procmux$755_Y[1] Y[2]=$procmux$755_Y[2] Y[3]=$procmux$755_Y[3] Y[4]=$procmux$755_Y[4] Y[5]=$procmux$755_Y[5] Y[6]=$procmux$755_Y[6] Y[7]=$procmux$755_Y[7] Y[8]=$procmux$755_Y[8] Y[9]=$procmux$755_Y[9] Y[10]=$procmux$755_Y[10] Y[11]=$procmux$755_Y[11] Y[12]=$procmux$755_Y[12] Y[13]=$procmux$755_Y[13] Y[14]=$procmux$755_Y[14] Y[15]=$procmux$755_Y[15] Y[16]=$procmux$755_Y[16] Y[17]=$procmux$755_Y[17] Y[18]=$procmux$755_Y[18] Y[19]=$procmux$755_Y[19] Y[20]=$procmux$755_Y[20] Y[21]=$procmux$755_Y[21] Y[22]=$procmux$755_Y[22] Y[23]=$procmux$755_Y[23] Y[24]=$procmux$755_Y[24] Y[25]=$procmux$755_Y[25] Y[26]=$procmux$755_Y[26] Y[27]=$procmux$755_Y[27] Y[28]=$procmux$755_Y[28] Y[29]=$procmux$755_Y[29] Y[30]=$procmux$755_Y[30] Y[31]=$procmux$755_Y[31]
|
||
|
|
.cname $procmux$755
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:150"
|
||
|
|
.param WIDTH 00000000000000000000000000100000
|
||
|
|
.subckt $pmux A[0]=W7[0] A[1]=W7[1] A[2]=W7[2] A[3]=W7[3] A[4]=W7[4] A[5]=W7[5] A[6]=W7[6] A[7]=W7[7] A[8]=W7[8] A[9]=W7[9] A[10]=W7[10] A[11]=W7[11] A[12]=W7[12] A[13]=W7[13] A[14]=W7[14] A[15]=W7[15] A[16]=W7[16] A[17]=W7[17] A[18]=W7[18] A[19]=W7[19] A[20]=W7[20] A[21]=W7[21] A[22]=W7[22] A[23]=W7[23] A[24]=W7[24] A[25]=W7[25] A[26]=W7[26] A[27]=W7[27] A[28]=W7[28] A[29]=W7[29] A[30]=W7[30] A[31]=W7[31] B[0]=W8[0] B[1]=W8[1] B[2]=W8[2] B[3]=W8[3] B[4]=W8[4] B[5]=W8[5] B[6]=W8[6] B[7]=W8[7] B[8]=W8[8] B[9]=W8[9] B[10]=W8[10] B[11]=W8[11] B[12]=W8[12] B[13]=W8[13] B[14]=W8[14] B[15]=W8[15] B[16]=W8[16] B[17]=W8[17] B[18]=W8[18] B[19]=W8[19] B[20]=W8[20] B[21]=W8[21] B[22]=W8[22] B[23]=W8[23] B[24]=W8[24] B[25]=W8[25] B[26]=W8[26] B[27]=W8[27] B[28]=W8[28] B[29]=W8[29] B[30]=W8[30] B[31]=W8[31] B[32]=W8[0] B[33]=W8[1] B[34]=W8[2] B[35]=W8[3] B[36]=W8[4] B[37]=W8[5] B[38]=W8[6] B[39]=W8[7] B[40]=W8[8] B[41]=W8[9] B[42]=W8[10] B[43]=W8[11] B[44]=W8[12] B[45]=W8[13] B[46]=W8[14] B[47]=W8[15] B[48]=W8[16] B[49]=W8[17] B[50]=W8[18] B[51]=W8[19] B[52]=W8[20] B[53]=W8[21] B[54]=W8[22] B[55]=W8[23] B[56]=W8[24] B[57]=W8[25] B[58]=W8[26] B[59]=W8[27] B[60]=W8[28] B[61]=W8[29] B[62]=W8[30] B[63]=W8[31] B[64]=W8[0] B[65]=W8[1] B[66]=W8[2] B[67]=W8[3] B[68]=W8[4] B[69]=W8[5] B[70]=W8[6] B[71]=W8[7] B[72]=W8[8] B[73]=W8[9] B[74]=W8[10] B[75]=W8[11] B[76]=W8[12] B[77]=W8[13] B[78]=W8[14] B[79]=W8[15] B[80]=W8[16] B[81]=W8[17] B[82]=W8[18] B[83]=W8[19] B[84]=W8[20] B[85]=W8[21] B[86]=W8[22] B[87]=W8[23] B[88]=W8[24] B[89]=W8[25] B[90]=W8[26] B[91]=W8[27] B[92]=W8[28] B[93]=W8[29] B[94]=W8[30] B[95]=W8[31] B[96]=W8[0] B[97]=W8[1] B[98]=W8[2] B[99]=W8[3] B[100]=W8[4] B[101]=W8[5] B[102]=W8[6] B[103]=W8[7] B[104]=W8[8] B[105]=W8[9] B[106]=W8[10] B[107]=W8[11] B[108]=W8[12] B[109]=W8[13] B[110]=W8[14] B[111]=W8[15] B[112]=W8[16] B[113]=W8[17] B[114]=W8[18] B[115]=W8[19] B[116]=W8[20] B[117]=W8[21] B[118]=W8[22] B[119]=W8[23] B[120]=W8[24] B[121]=W8[25] B[122]=W8[26] B[123]=W8[27] B[124]=W8[28] B[125]=W8[29] B[126]=W8[30] B[127]=W8[31] B[128]=W8[0] B[129]=W8[1] B[130]=W8[2] B[131]=W8[3] B[132]=W8[4] B[133]=W8[5] B[134]=W8[6] B[135]=W8[7] B[136]=W8[8] B[137]=W8[9] B[138]=W8[10] B[139]=W8[11] B[140]=W8[12] B[141]=W8[13] B[142]=W8[14] B[143]=W8[15] B[144]=W8[16] B[145]=W8[17] B[146]=W8[18] B[147]=W8[19] B[148]=W8[20] B[149]=W8[21] B[150]=W8[22] B[151]=W8[23] B[152]=W8[24] B[153]=W8[25] B[154]=W8[26] B[155]=W8[27] B[156]=W8[28] B[157]=W8[29] B[158]=W8[30] B[159]=W8[31] B[160]=W8[0] B[161]=W8[1] B[162]=W8[2] B[163]=W8[3] B[164]=W8[4] B[165]=W8[5] B[166]=W8[6] B[167]=W8[7] B[168]=W8[8] B[169]=W8[9] B[170]=W8[10] B[171]=W8[11] B[172]=W8[12] B[173]=W8[13] B[174]=W8[14] B[175]=W8[15] B[176]=W8[16] B[177]=W8[17] B[178]=W8[18] B[179]=W8[19] B[180]=W8[20] B[181]=W8[21] B[182]=W8[22] B[183]=W8[23] B[184]=W8[24] B[185]=W8[25] B[186]=W8[26] B[187]=W8[27] B[188]=W8[28] B[189]=W8[29] B[190]=W8[30] B[191]=W8[31] B[192]=W8[0] B[193]=W8[1] B[194]=W8[2] B[195]=W8[3] B[196]=W8[4] B[197]=W8[5] B[198]=W8[6] B[199]=W8[7] B[200]=W8[8] B[201]=W8[9] B[202]=W8[10] B[203]=W8[11] B[204]=W8[12] B[205]=W8[13] B[206]=W8[14] B[207]=W8[15] B[208]=W8[16] B[209]=W8[17] B[210]=W8[18] B[211]=W8[19] B[212]=W8[20] B[213]=W8[21] B[214]=W8[22] B[215]=W8[23] B[216]=W8[24] B[217]=W8[25] B[218]=W8[26] B[219]=W8[27] B[220]=W8[28] B[221]=W8[29] B[222]=W8[30] B[223]=W8[31] B[224]=W8[0] B[225]=W8[1] B[226]=W8[2] B[227]=W8[3] B[228]=W8[4] B[229]=W8[5] B[230]=W8[6] B[231]=W8[7] B[232]=W8[8] B[233]=W8[9] B[234]=W8[10] B[235]=W8[11] B[236]=W8[12] B[237]=W8[13] B[238]=W8[14] B[239]=W8[15] B[240]=W8[16] B[241]=W8[17] B[242]=W8[18] B[243]=W8[19] B[244]=W8[20] B[245]=W8[21] B[246]=W8[22] B[247]=W8[23] B[248]=W8[24] B[249]=W8[25] B[250]=W8[26] B[251]=W8[27] B[252]=W8[28] B[253]=W8[29] B[254]=W8[30] B[255]=W8[31] B[256]=W8[0] B[257]=W8[1] B[258]=W8[2] B[259]=W8[3] B[260]=W8[4] B[261]=W8[5] B[262]=W8[6] B[263]=W8[7] B[264]=W8[8] B[265]=W8[9] B[266]=W8[10] B[267]=W8[11] B[268]=W8[12] B[269]=W8[13] B[270]=W8[14] B[271]=W8[15] B[272]=W8[16] B[273]=W8[17] B[274]=W8[18] B[275]=W8[19] B[276]=W8[20] B[277]=
|
||
|
|
.cname $procmux$759
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param S_WIDTH 00000000000000000000000001000001
|
||
|
|
.param WIDTH 00000000000000000000000000100000
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$true B[1]=$true B[2]=$true B[3]=$true B[4]=$false B[5]=$false B[6]=$true Y=$procmux$760_CMP
|
||
|
|
.cname $procmux$760_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$false B[1]=$true B[2]=$true B[3]=$true B[4]=$false B[5]=$false B[6]=$true Y=$procmux$761_CMP
|
||
|
|
.cname $procmux$761_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$true B[1]=$false B[2]=$true B[3]=$true B[4]=$false B[5]=$false B[6]=$true Y=$procmux$762_CMP
|
||
|
|
.cname $procmux$762_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$false B[1]=$false B[2]=$true B[3]=$true B[4]=$false B[5]=$false B[6]=$true Y=$procmux$763_CMP
|
||
|
|
.cname $procmux$763_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$true B[1]=$true B[2]=$false B[3]=$true B[4]=$false B[5]=$false B[6]=$true Y=$procmux$764_CMP
|
||
|
|
.cname $procmux$764_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$false B[1]=$true B[2]=$false B[3]=$true B[4]=$false B[5]=$false B[6]=$true Y=$procmux$765_CMP
|
||
|
|
.cname $procmux$765_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$true B[1]=$false B[2]=$false B[3]=$true B[4]=$false B[5]=$false B[6]=$true Y=$procmux$766_CMP
|
||
|
|
.cname $procmux$766_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$false B[1]=$false B[2]=$false B[3]=$true B[4]=$false B[5]=$false B[6]=$true Y=$procmux$767_CMP
|
||
|
|
.cname $procmux$767_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$true B[1]=$true B[2]=$true B[3]=$false B[4]=$false B[5]=$false B[6]=$true Y=$procmux$768_CMP
|
||
|
|
.cname $procmux$768_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$false B[1]=$true B[2]=$true B[3]=$false B[4]=$false B[5]=$false B[6]=$true Y=$procmux$769_CMP
|
||
|
|
.cname $procmux$769_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $mux A[0]=$procmux$74_Y[0] A[1]=$procmux$74_Y[1] A[2]=$procmux$74_Y[2] A[3]=$procmux$74_Y[3] A[4]=$procmux$74_Y[4] A[5]=$procmux$74_Y[5] A[6]=$procmux$74_Y[6] A[7]=$procmux$74_Y[7] A[8]=$procmux$74_Y[8] A[9]=$procmux$74_Y[9] A[10]=$procmux$74_Y[10] A[11]=$procmux$74_Y[11] A[12]=$procmux$74_Y[12] A[13]=$procmux$74_Y[13] A[14]=$procmux$74_Y[14] A[15]=$procmux$74_Y[15] A[16]=$procmux$74_Y[16] A[17]=$procmux$74_Y[17] A[18]=$procmux$74_Y[18] A[19]=$procmux$74_Y[19] A[20]=$procmux$74_Y[20] A[21]=$procmux$74_Y[21] A[22]=$procmux$74_Y[22] A[23]=$procmux$74_Y[23] A[24]=$procmux$74_Y[24] A[25]=$procmux$74_Y[25] A[26]=$procmux$74_Y[26] A[27]=$procmux$74_Y[27] A[28]=$procmux$74_Y[28] A[29]=$procmux$74_Y[29] A[30]=$procmux$74_Y[30] A[31]=$procmux$74_Y[31] B[0]=$true B[1]=$false B[2]=$false B[3]=$true B[4]=$true B[5]=$false B[6]=$false B[7]=$true B[8]=$true B[9]=$false B[10]=$false B[11]=$true B[12]=$true B[13]=$true B[14]=$true B[15]=$false B[16]=$false B[17]=$true B[18]=$false B[19]=$false B[20]=$false B[21]=$false B[22]=$false B[23]=$true B[24]=$false B[25]=$true B[26]=$false B[27]=$true B[28]=$true B[29]=$false B[30]=$true B[31]=$false S=$procmux$78_CMP Y[0]=$procmux$77_Y[0] Y[1]=$procmux$77_Y[1] Y[2]=$procmux$77_Y[2] Y[3]=$procmux$77_Y[3] Y[4]=$procmux$77_Y[4] Y[5]=$procmux$77_Y[5] Y[6]=$procmux$77_Y[6] Y[7]=$procmux$77_Y[7] Y[8]=$procmux$77_Y[8] Y[9]=$procmux$77_Y[9] Y[10]=$procmux$77_Y[10] Y[11]=$procmux$77_Y[11] Y[12]=$procmux$77_Y[12] Y[13]=$procmux$77_Y[13] Y[14]=$procmux$77_Y[14] Y[15]=$procmux$77_Y[15] Y[16]=$procmux$77_Y[16] Y[17]=$procmux$77_Y[17] Y[18]=$procmux$77_Y[18] Y[19]=$procmux$77_Y[19] Y[20]=$procmux$77_Y[20] Y[21]=$procmux$77_Y[21] Y[22]=$procmux$77_Y[22] Y[23]=$procmux$77_Y[23] Y[24]=$procmux$77_Y[24] Y[25]=$procmux$77_Y[25] Y[26]=$procmux$77_Y[26] Y[27]=$procmux$77_Y[27] Y[28]=$procmux$77_Y[28] Y[29]=$procmux$77_Y[29] Y[30]=$procmux$77_Y[30] Y[31]=$procmux$77_Y[31]
|
||
|
|
.cname $procmux$77
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:2118"
|
||
|
|
.param WIDTH 00000000000000000000000000100000
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$true B[1]=$false B[2]=$true B[3]=$false B[4]=$false B[5]=$false B[6]=$true Y=$procmux$770_CMP
|
||
|
|
.cname $procmux$770_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$false B[1]=$false B[2]=$true B[3]=$false B[4]=$false B[5]=$false B[6]=$true Y=$procmux$771_CMP
|
||
|
|
.cname $procmux$771_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$true B[1]=$true B[2]=$false B[3]=$false B[4]=$false B[5]=$false B[6]=$true Y=$procmux$772_CMP
|
||
|
|
.cname $procmux$772_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$false B[1]=$true B[2]=$false B[3]=$false B[4]=$false B[5]=$false B[6]=$true Y=$procmux$773_CMP
|
||
|
|
.cname $procmux$773_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$true B[1]=$false B[2]=$false B[3]=$false B[4]=$false B[5]=$false B[6]=$true Y=$procmux$774_CMP
|
||
|
|
.cname $procmux$774_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$false B[1]=$false B[2]=$false B[3]=$false B[4]=$false B[5]=$false B[6]=$true Y=$procmux$775_CMP
|
||
|
|
.cname $procmux$775_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$true B[1]=$true B[2]=$true B[3]=$true B[4]=$true B[5]=$true B[6]=$false Y=$procmux$776_CMP
|
||
|
|
.cname $procmux$776_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$false B[1]=$true B[2]=$true B[3]=$true B[4]=$true B[5]=$true B[6]=$false Y=$procmux$777_CMP
|
||
|
|
.cname $procmux$777_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$true B[1]=$false B[2]=$true B[3]=$true B[4]=$true B[5]=$true B[6]=$false Y=$procmux$778_CMP
|
||
|
|
.cname $procmux$778_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$false B[1]=$false B[2]=$true B[3]=$true B[4]=$true B[5]=$true B[6]=$false Y=$procmux$779_CMP
|
||
|
|
.cname $procmux$779_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$true B[1]=$true B[2]=$false B[3]=$true B[4]=$true B[5]=$true B[6]=$false Y=$procmux$780_CMP
|
||
|
|
.cname $procmux$780_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$false B[1]=$true B[2]=$false B[3]=$true B[4]=$true B[5]=$true B[6]=$false Y=$procmux$781_CMP
|
||
|
|
.cname $procmux$781_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$true B[1]=$false B[2]=$false B[3]=$true B[4]=$true B[5]=$true B[6]=$false Y=$procmux$782_CMP
|
||
|
|
.cname $procmux$782_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$false B[1]=$false B[2]=$false B[3]=$true B[4]=$true B[5]=$true B[6]=$false Y=$procmux$783_CMP
|
||
|
|
.cname $procmux$783_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$true B[1]=$true B[2]=$true B[3]=$false B[4]=$true B[5]=$true B[6]=$false Y=$procmux$784_CMP
|
||
|
|
.cname $procmux$784_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$false B[1]=$true B[2]=$true B[3]=$false B[4]=$true B[5]=$true B[6]=$false Y=$procmux$785_CMP
|
||
|
|
.cname $procmux$785_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$true B[1]=$false B[2]=$true B[3]=$false B[4]=$true B[5]=$true B[6]=$false Y=$procmux$786_CMP
|
||
|
|
.cname $procmux$786_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$false B[1]=$false B[2]=$true B[3]=$false B[4]=$true B[5]=$true B[6]=$false Y=$procmux$787_CMP
|
||
|
|
.cname $procmux$787_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$true B[1]=$true B[2]=$false B[3]=$false B[4]=$true B[5]=$true B[6]=$false Y=$procmux$788_CMP
|
||
|
|
.cname $procmux$788_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$false B[1]=$true B[2]=$false B[3]=$false B[4]=$true B[5]=$true B[6]=$false Y=$procmux$789_CMP
|
||
|
|
.cname $procmux$789_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$true B[1]=$false B[2]=$false B[3]=$false B[4]=$true B[5]=$true B[6]=$false Y=$procmux$790_CMP
|
||
|
|
.cname $procmux$790_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$false B[1]=$false B[2]=$false B[3]=$false B[4]=$true B[5]=$true B[6]=$false Y=$procmux$791_CMP
|
||
|
|
.cname $procmux$791_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$true B[1]=$true B[2]=$true B[3]=$true B[4]=$false B[5]=$true B[6]=$false Y=$procmux$792_CMP
|
||
|
|
.cname $procmux$792_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$false B[1]=$true B[2]=$true B[3]=$true B[4]=$false B[5]=$true B[6]=$false Y=$procmux$793_CMP
|
||
|
|
.cname $procmux$793_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$true B[1]=$false B[2]=$true B[3]=$true B[4]=$false B[5]=$true B[6]=$false Y=$procmux$794_CMP
|
||
|
|
.cname $procmux$794_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$false B[1]=$false B[2]=$true B[3]=$true B[4]=$false B[5]=$true B[6]=$false Y=$procmux$795_CMP
|
||
|
|
.cname $procmux$795_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$true B[1]=$true B[2]=$false B[3]=$true B[4]=$false B[5]=$true B[6]=$false Y=$procmux$796_CMP
|
||
|
|
.cname $procmux$796_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$false B[1]=$true B[2]=$false B[3]=$true B[4]=$false B[5]=$true B[6]=$false Y=$procmux$797_CMP
|
||
|
|
.cname $procmux$797_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$true B[1]=$false B[2]=$false B[3]=$true B[4]=$false B[5]=$true B[6]=$false Y=$procmux$798_CMP
|
||
|
|
.cname $procmux$798_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$false B[1]=$false B[2]=$false B[3]=$true B[4]=$false B[5]=$true B[6]=$false Y=$procmux$799_CMP
|
||
|
|
.cname $procmux$799_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $mux A[0]=$procmux$77_Y[0] A[1]=$procmux$77_Y[1] A[2]=$procmux$77_Y[2] A[3]=$procmux$77_Y[3] A[4]=$procmux$77_Y[4] A[5]=$procmux$77_Y[5] A[6]=$procmux$77_Y[6] A[7]=$procmux$77_Y[7] A[8]=$procmux$77_Y[8] A[9]=$procmux$77_Y[9] A[10]=$procmux$77_Y[10] A[11]=$procmux$77_Y[11] A[12]=$procmux$77_Y[12] A[13]=$procmux$77_Y[13] A[14]=$procmux$77_Y[14] A[15]=$procmux$77_Y[15] A[16]=$procmux$77_Y[16] A[17]=$procmux$77_Y[17] A[18]=$procmux$77_Y[18] A[19]=$procmux$77_Y[19] A[20]=$procmux$77_Y[20] A[21]=$procmux$77_Y[21] A[22]=$procmux$77_Y[22] A[23]=$procmux$77_Y[23] A[24]=$procmux$77_Y[24] A[25]=$procmux$77_Y[25] A[26]=$procmux$77_Y[26] A[27]=$procmux$77_Y[27] A[28]=$procmux$77_Y[28] A[29]=$procmux$77_Y[29] A[30]=$procmux$77_Y[30] A[31]=$procmux$77_Y[31] B[0]=$false B[1]=$false B[2]=$false B[3]=$false B[4]=$false B[5]=$false B[6]=$false B[7]=$false B[8]=$false B[9]=$false B[10]=$false B[11]=$false B[12]=$false B[13]=$false B[14]=$false B[15]=$false B[16]=$false B[17]=$false B[18]=$false B[19]=$false B[20]=$false B[21]=$false B[22]=$false B[23]=$false B[24]=$false B[25]=$false B[26]=$false B[27]=$false B[28]=$false B[29]=$false B[30]=$false B[31]=$false S=$procmux$81_CMP Y[0]=$procmux$80_Y[0] Y[1]=$procmux$80_Y[1] Y[2]=$procmux$80_Y[2] Y[3]=$procmux$80_Y[3] Y[4]=$procmux$80_Y[4] Y[5]=$procmux$80_Y[5] Y[6]=$procmux$80_Y[6] Y[7]=$procmux$80_Y[7] Y[8]=$procmux$80_Y[8] Y[9]=$procmux$80_Y[9] Y[10]=$procmux$80_Y[10] Y[11]=$procmux$80_Y[11] Y[12]=$procmux$80_Y[12] Y[13]=$procmux$80_Y[13] Y[14]=$procmux$80_Y[14] Y[15]=$procmux$80_Y[15] Y[16]=$procmux$80_Y[16] Y[17]=$procmux$80_Y[17] Y[18]=$procmux$80_Y[18] Y[19]=$procmux$80_Y[19] Y[20]=$procmux$80_Y[20] Y[21]=$procmux$80_Y[21] Y[22]=$procmux$80_Y[22] Y[23]=$procmux$80_Y[23] Y[24]=$procmux$80_Y[24] Y[25]=$procmux$80_Y[25] Y[26]=$procmux$80_Y[26] Y[27]=$procmux$80_Y[27] Y[28]=$procmux$80_Y[28] Y[29]=$procmux$80_Y[29] Y[30]=$procmux$80_Y[30] Y[31]=$procmux$80_Y[31]
|
||
|
|
.cname $procmux$80
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:2112"
|
||
|
|
.param WIDTH 00000000000000000000000000100000
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$true B[1]=$true B[2]=$true B[3]=$false B[4]=$false B[5]=$true B[6]=$false Y=$procmux$800_CMP
|
||
|
|
.cname $procmux$800_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$false B[1]=$true B[2]=$true B[3]=$false B[4]=$false B[5]=$true B[6]=$false Y=$procmux$801_CMP
|
||
|
|
.cname $procmux$801_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$true B[1]=$false B[2]=$true B[3]=$false B[4]=$false B[5]=$true B[6]=$false Y=$procmux$802_CMP
|
||
|
|
.cname $procmux$802_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$false B[1]=$false B[2]=$true B[3]=$false B[4]=$false B[5]=$true B[6]=$false Y=$procmux$803_CMP
|
||
|
|
.cname $procmux$803_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$true B[1]=$true B[2]=$false B[3]=$false B[4]=$false B[5]=$true B[6]=$false Y=$procmux$804_CMP
|
||
|
|
.cname $procmux$804_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$false B[1]=$true B[2]=$false B[3]=$false B[4]=$false B[5]=$true B[6]=$false Y=$procmux$805_CMP
|
||
|
|
.cname $procmux$805_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$true B[1]=$false B[2]=$false B[3]=$false B[4]=$false B[5]=$true B[6]=$false Y=$procmux$806_CMP
|
||
|
|
.cname $procmux$806_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$false B[1]=$false B[2]=$false B[3]=$false B[4]=$false B[5]=$true B[6]=$false Y=$procmux$807_CMP
|
||
|
|
.cname $procmux$807_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$true B[1]=$true B[2]=$true B[3]=$true B[4]=$true B[5]=$false B[6]=$false Y=$procmux$808_CMP
|
||
|
|
.cname $procmux$808_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$false B[1]=$true B[2]=$true B[3]=$true B[4]=$true B[5]=$false B[6]=$false Y=$procmux$809_CMP
|
||
|
|
.cname $procmux$809_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$true B[1]=$false B[2]=$true B[3]=$true B[4]=$true B[5]=$false B[6]=$false Y=$procmux$810_CMP
|
||
|
|
.cname $procmux$810_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$false B[1]=$false B[2]=$true B[3]=$true B[4]=$true B[5]=$false B[6]=$false Y=$procmux$811_CMP
|
||
|
|
.cname $procmux$811_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$true B[1]=$true B[2]=$false B[3]=$true B[4]=$true B[5]=$false B[6]=$false Y=$procmux$812_CMP
|
||
|
|
.cname $procmux$812_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$false B[1]=$true B[2]=$false B[3]=$true B[4]=$true B[5]=$false B[6]=$false Y=$procmux$813_CMP
|
||
|
|
.cname $procmux$813_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$true B[1]=$false B[2]=$false B[3]=$true B[4]=$true B[5]=$false B[6]=$false Y=$procmux$814_CMP
|
||
|
|
.cname $procmux$814_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$false B[1]=$false B[2]=$false B[3]=$true B[4]=$true B[5]=$false B[6]=$false Y=$procmux$815_CMP
|
||
|
|
.cname $procmux$815_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$true B[1]=$true B[2]=$true B[3]=$false B[4]=$true B[5]=$false B[6]=$false Y=$procmux$816_CMP
|
||
|
|
.cname $procmux$816_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$false B[1]=$true B[2]=$true B[3]=$false B[4]=$true B[5]=$false B[6]=$false Y=$procmux$817_CMP
|
||
|
|
.cname $procmux$817_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$true B[1]=$false B[2]=$true B[3]=$false B[4]=$true B[5]=$false B[6]=$false Y=$procmux$818_CMP
|
||
|
|
.cname $procmux$818_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$false B[1]=$false B[2]=$true B[3]=$false B[4]=$true B[5]=$false B[6]=$false Y=$procmux$819_CMP
|
||
|
|
.cname $procmux$819_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$true B[1]=$true B[2]=$false B[3]=$false B[4]=$true B[5]=$false B[6]=$false Y=$procmux$820_CMP
|
||
|
|
.cname $procmux$820_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$false B[1]=$true B[2]=$false B[3]=$false B[4]=$true B[5]=$false B[6]=$false Y=$procmux$821_CMP
|
||
|
|
.cname $procmux$821_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$true B[1]=$false B[2]=$false B[3]=$false B[4]=$true B[5]=$false B[6]=$false Y=$procmux$822_CMP
|
||
|
|
.cname $procmux$822_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$false B[1]=$false B[2]=$false B[3]=$false B[4]=$true B[5]=$false B[6]=$false Y=$procmux$823_CMP
|
||
|
|
.cname $procmux$823_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$true B[1]=$true B[2]=$true B[3]=$false B[4]=$false B[5]=$false B[6]=$false Y=$procmux$824_CMP
|
||
|
|
.cname $procmux$824_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $mux A[0]=$procmux$759_Y[0] A[1]=$procmux$759_Y[1] A[2]=$procmux$759_Y[2] A[3]=$procmux$759_Y[3] A[4]=$procmux$759_Y[4] A[5]=$procmux$759_Y[5] A[6]=$procmux$759_Y[6] A[7]=$procmux$759_Y[7] A[8]=$procmux$759_Y[8] A[9]=$procmux$759_Y[9] A[10]=$procmux$759_Y[10] A[11]=$procmux$759_Y[11] A[12]=$procmux$759_Y[12] A[13]=$procmux$759_Y[13] A[14]=$procmux$759_Y[14] A[15]=$procmux$759_Y[15] A[16]=$procmux$759_Y[16] A[17]=$procmux$759_Y[17] A[18]=$procmux$759_Y[18] A[19]=$procmux$759_Y[19] A[20]=$procmux$759_Y[20] A[21]=$procmux$759_Y[21] A[22]=$procmux$759_Y[22] A[23]=$procmux$759_Y[23] A[24]=$procmux$759_Y[24] A[25]=$procmux$759_Y[25] A[26]=$procmux$759_Y[26] A[27]=$procmux$759_Y[27] A[28]=$procmux$759_Y[28] A[29]=$procmux$759_Y[29] A[30]=$procmux$759_Y[30] A[31]=$procmux$759_Y[31] B[0]=$false B[1]=$false B[2]=$false B[3]=$false B[4]=$false B[5]=$false B[6]=$false B[7]=$false B[8]=$false B[9]=$false B[10]=$false B[11]=$false B[12]=$false B[13]=$false B[14]=$false B[15]=$false B[16]=$false B[17]=$false B[18]=$false B[19]=$false B[20]=$false B[21]=$false B[22]=$false B[23]=$false B[24]=$false B[25]=$false B[26]=$false B[27]=$false B[28]=$false B[29]=$false B[30]=$false B[31]=$false S=$procmux$827_CMP Y[0]=$procmux$826_Y[0] Y[1]=$procmux$826_Y[1] Y[2]=$procmux$826_Y[2] Y[3]=$procmux$826_Y[3] Y[4]=$procmux$826_Y[4] Y[5]=$procmux$826_Y[5] Y[6]=$procmux$826_Y[6] Y[7]=$procmux$826_Y[7] Y[8]=$procmux$826_Y[8] Y[9]=$procmux$826_Y[9] Y[10]=$procmux$826_Y[10] Y[11]=$procmux$826_Y[11] Y[12]=$procmux$826_Y[12] Y[13]=$procmux$826_Y[13] Y[14]=$procmux$826_Y[14] Y[15]=$procmux$826_Y[15] Y[16]=$procmux$826_Y[16] Y[17]=$procmux$826_Y[17] Y[18]=$procmux$826_Y[18] Y[19]=$procmux$826_Y[19] Y[20]=$procmux$826_Y[20] Y[21]=$procmux$826_Y[21] Y[22]=$procmux$826_Y[22] Y[23]=$procmux$826_Y[23] Y[24]=$procmux$826_Y[24] Y[25]=$procmux$826_Y[25] Y[26]=$procmux$826_Y[26] Y[27]=$procmux$826_Y[27] Y[28]=$procmux$826_Y[28] Y[29]=$procmux$826_Y[29] Y[30]=$procmux$826_Y[30] Y[31]=$procmux$826_Y[31]
|
||
|
|
.cname $procmux$826
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:150"
|
||
|
|
.param WIDTH 00000000000000000000000000100000
|
||
|
|
.subckt $pmux A[0]=W6[0] A[1]=W6[1] A[2]=W6[2] A[3]=W6[3] A[4]=W6[4] A[5]=W6[5] A[6]=W6[6] A[7]=W6[7] A[8]=W6[8] A[9]=W6[9] A[10]=W6[10] A[11]=W6[11] A[12]=W6[12] A[13]=W6[13] A[14]=W6[14] A[15]=W6[15] A[16]=W6[16] A[17]=W6[17] A[18]=W6[18] A[19]=W6[19] A[20]=W6[20] A[21]=W6[21] A[22]=W6[22] A[23]=W6[23] A[24]=W6[24] A[25]=W6[25] A[26]=W6[26] A[27]=W6[27] A[28]=W6[28] A[29]=W6[29] A[30]=W6[30] A[31]=W6[31] B[0]=W7[0] B[1]=W7[1] B[2]=W7[2] B[3]=W7[3] B[4]=W7[4] B[5]=W7[5] B[6]=W7[6] B[7]=W7[7] B[8]=W7[8] B[9]=W7[9] B[10]=W7[10] B[11]=W7[11] B[12]=W7[12] B[13]=W7[13] B[14]=W7[14] B[15]=W7[15] B[16]=W7[16] B[17]=W7[17] B[18]=W7[18] B[19]=W7[19] B[20]=W7[20] B[21]=W7[21] B[22]=W7[22] B[23]=W7[23] B[24]=W7[24] B[25]=W7[25] B[26]=W7[26] B[27]=W7[27] B[28]=W7[28] B[29]=W7[29] B[30]=W7[30] B[31]=W7[31] B[32]=W7[0] B[33]=W7[1] B[34]=W7[2] B[35]=W7[3] B[36]=W7[4] B[37]=W7[5] B[38]=W7[6] B[39]=W7[7] B[40]=W7[8] B[41]=W7[9] B[42]=W7[10] B[43]=W7[11] B[44]=W7[12] B[45]=W7[13] B[46]=W7[14] B[47]=W7[15] B[48]=W7[16] B[49]=W7[17] B[50]=W7[18] B[51]=W7[19] B[52]=W7[20] B[53]=W7[21] B[54]=W7[22] B[55]=W7[23] B[56]=W7[24] B[57]=W7[25] B[58]=W7[26] B[59]=W7[27] B[60]=W7[28] B[61]=W7[29] B[62]=W7[30] B[63]=W7[31] B[64]=W7[0] B[65]=W7[1] B[66]=W7[2] B[67]=W7[3] B[68]=W7[4] B[69]=W7[5] B[70]=W7[6] B[71]=W7[7] B[72]=W7[8] B[73]=W7[9] B[74]=W7[10] B[75]=W7[11] B[76]=W7[12] B[77]=W7[13] B[78]=W7[14] B[79]=W7[15] B[80]=W7[16] B[81]=W7[17] B[82]=W7[18] B[83]=W7[19] B[84]=W7[20] B[85]=W7[21] B[86]=W7[22] B[87]=W7[23] B[88]=W7[24] B[89]=W7[25] B[90]=W7[26] B[91]=W7[27] B[92]=W7[28] B[93]=W7[29] B[94]=W7[30] B[95]=W7[31] B[96]=W7[0] B[97]=W7[1] B[98]=W7[2] B[99]=W7[3] B[100]=W7[4] B[101]=W7[5] B[102]=W7[6] B[103]=W7[7] B[104]=W7[8] B[105]=W7[9] B[106]=W7[10] B[107]=W7[11] B[108]=W7[12] B[109]=W7[13] B[110]=W7[14] B[111]=W7[15] B[112]=W7[16] B[113]=W7[17] B[114]=W7[18] B[115]=W7[19] B[116]=W7[20] B[117]=W7[21] B[118]=W7[22] B[119]=W7[23] B[120]=W7[24] B[121]=W7[25] B[122]=W7[26] B[123]=W7[27] B[124]=W7[28] B[125]=W7[29] B[126]=W7[30] B[127]=W7[31] B[128]=W7[0] B[129]=W7[1] B[130]=W7[2] B[131]=W7[3] B[132]=W7[4] B[133]=W7[5] B[134]=W7[6] B[135]=W7[7] B[136]=W7[8] B[137]=W7[9] B[138]=W7[10] B[139]=W7[11] B[140]=W7[12] B[141]=W7[13] B[142]=W7[14] B[143]=W7[15] B[144]=W7[16] B[145]=W7[17] B[146]=W7[18] B[147]=W7[19] B[148]=W7[20] B[149]=W7[21] B[150]=W7[22] B[151]=W7[23] B[152]=W7[24] B[153]=W7[25] B[154]=W7[26] B[155]=W7[27] B[156]=W7[28] B[157]=W7[29] B[158]=W7[30] B[159]=W7[31] B[160]=W7[0] B[161]=W7[1] B[162]=W7[2] B[163]=W7[3] B[164]=W7[4] B[165]=W7[5] B[166]=W7[6] B[167]=W7[7] B[168]=W7[8] B[169]=W7[9] B[170]=W7[10] B[171]=W7[11] B[172]=W7[12] B[173]=W7[13] B[174]=W7[14] B[175]=W7[15] B[176]=W7[16] B[177]=W7[17] B[178]=W7[18] B[179]=W7[19] B[180]=W7[20] B[181]=W7[21] B[182]=W7[22] B[183]=W7[23] B[184]=W7[24] B[185]=W7[25] B[186]=W7[26] B[187]=W7[27] B[188]=W7[28] B[189]=W7[29] B[190]=W7[30] B[191]=W7[31] B[192]=W7[0] B[193]=W7[1] B[194]=W7[2] B[195]=W7[3] B[196]=W7[4] B[197]=W7[5] B[198]=W7[6] B[199]=W7[7] B[200]=W7[8] B[201]=W7[9] B[202]=W7[10] B[203]=W7[11] B[204]=W7[12] B[205]=W7[13] B[206]=W7[14] B[207]=W7[15] B[208]=W7[16] B[209]=W7[17] B[210]=W7[18] B[211]=W7[19] B[212]=W7[20] B[213]=W7[21] B[214]=W7[22] B[215]=W7[23] B[216]=W7[24] B[217]=W7[25] B[218]=W7[26] B[219]=W7[27] B[220]=W7[28] B[221]=W7[29] B[222]=W7[30] B[223]=W7[31] B[224]=W7[0] B[225]=W7[1] B[226]=W7[2] B[227]=W7[3] B[228]=W7[4] B[229]=W7[5] B[230]=W7[6] B[231]=W7[7] B[232]=W7[8] B[233]=W7[9] B[234]=W7[10] B[235]=W7[11] B[236]=W7[12] B[237]=W7[13] B[238]=W7[14] B[239]=W7[15] B[240]=W7[16] B[241]=W7[17] B[242]=W7[18] B[243]=W7[19] B[244]=W7[20] B[245]=W7[21] B[246]=W7[22] B[247]=W7[23] B[248]=W7[24] B[249]=W7[25] B[250]=W7[26] B[251]=W7[27] B[252]=W7[28] B[253]=W7[29] B[254]=W7[30] B[255]=W7[31] B[256]=W7[0] B[257]=W7[1] B[258]=W7[2] B[259]=W7[3] B[260]=W7[4] B[261]=W7[5] B[262]=W7[6] B[263]=W7[7] B[264]=W7[8] B[265]=W7[9] B[266]=W7[10] B[267]=W7[11] B[268]=W7[12] B[269]=W7[13] B[270]=W7[14] B[271]=W7[15] B[272]=W7[16] B[273]=W7[17] B[274]=W7[18] B[275]=W7[19] B[276]=W7[20] B[277]=
|
||
|
|
.cname $procmux$830
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param S_WIDTH 00000000000000000000000001000001
|
||
|
|
.param WIDTH 00000000000000000000000000100000
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$true B[1]=$true B[2]=$true B[3]=$true B[4]=$false B[5]=$false B[6]=$true Y=$procmux$831_CMP
|
||
|
|
.cname $procmux$831_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$false B[1]=$true B[2]=$true B[3]=$true B[4]=$false B[5]=$false B[6]=$true Y=$procmux$832_CMP
|
||
|
|
.cname $procmux$832_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$true B[1]=$false B[2]=$true B[3]=$true B[4]=$false B[5]=$false B[6]=$true Y=$procmux$833_CMP
|
||
|
|
.cname $procmux$833_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$false B[1]=$false B[2]=$true B[3]=$true B[4]=$false B[5]=$false B[6]=$true Y=$procmux$834_CMP
|
||
|
|
.cname $procmux$834_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$true B[1]=$true B[2]=$false B[3]=$true B[4]=$false B[5]=$false B[6]=$true Y=$procmux$835_CMP
|
||
|
|
.cname $procmux$835_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$false B[1]=$true B[2]=$false B[3]=$true B[4]=$false B[5]=$false B[6]=$true Y=$procmux$836_CMP
|
||
|
|
.cname $procmux$836_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$true B[1]=$false B[2]=$false B[3]=$true B[4]=$false B[5]=$false B[6]=$true Y=$procmux$837_CMP
|
||
|
|
.cname $procmux$837_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$false B[1]=$false B[2]=$false B[3]=$true B[4]=$false B[5]=$false B[6]=$true Y=$procmux$838_CMP
|
||
|
|
.cname $procmux$838_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$true B[1]=$true B[2]=$true B[3]=$false B[4]=$false B[5]=$false B[6]=$true Y=$procmux$839_CMP
|
||
|
|
.cname $procmux$839_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $pmux A=$false B[0]=busy B[1]=busy B[2]=busy B[3]=busy B[4]=busy B[5]=busy B[6]=busy B[7]=busy B[8]=busy B[9]=busy B[10]=busy B[11]=busy B[12]=busy B[13]=busy B[14]=busy B[15]=busy B[16]=busy B[17]=busy B[18]=busy B[19]=busy B[20]=busy B[21]=busy B[22]=busy B[23]=busy B[24]=busy B[25]=busy B[26]=busy B[27]=busy B[28]=busy B[29]=busy B[30]=busy B[31]=busy B[32]=busy B[33]=busy B[34]=busy B[35]=busy B[36]=busy B[37]=busy B[38]=busy B[39]=busy B[40]=busy B[41]=busy B[42]=busy B[43]=busy B[44]=busy B[45]=busy B[46]=busy B[47]=busy B[48]=busy B[49]=busy B[50]=busy B[51]=busy B[52]=busy B[53]=busy B[54]=busy B[55]=busy B[56]=busy B[57]=busy B[58]=busy B[59]=busy B[60]=busy B[61]=busy B[62]=busy B[63]=busy B[64]=busy B[65]=busy B[66]=busy B[67]=busy B[68]=busy B[69]=busy B[70]=busy B[71]=busy B[72]=busy B[73]=busy B[74]=busy B[75]=busy B[76]=busy B[77]=busy B[78]=busy B[79]=$procmux$165_Y S[0]=$procmux$85_CMP S[1]=$procmux$86_CMP S[2]=$procmux$87_CMP S[3]=$procmux$88_CMP S[4]=$procmux$89_CMP S[5]=$procmux$90_CMP S[6]=$procmux$91_CMP S[7]=$procmux$92_CMP S[8]=$procmux$93_CMP S[9]=$procmux$94_CMP S[10]=$procmux$95_CMP S[11]=$procmux$96_CMP S[12]=$procmux$97_CMP S[13]=$procmux$98_CMP S[14]=$procmux$99_CMP S[15]=$procmux$100_CMP S[16]=$procmux$101_CMP S[17]=$procmux$102_CMP S[18]=$procmux$103_CMP S[19]=$procmux$104_CMP S[20]=$procmux$105_CMP S[21]=$procmux$106_CMP S[22]=$procmux$107_CMP S[23]=$procmux$108_CMP S[24]=$procmux$109_CMP S[25]=$procmux$110_CMP S[26]=$procmux$111_CMP S[27]=$procmux$112_CMP S[28]=$procmux$113_CMP S[29]=$procmux$114_CMP S[30]=$procmux$115_CMP S[31]=$procmux$116_CMP S[32]=$procmux$117_CMP S[33]=$procmux$118_CMP S[34]=$procmux$119_CMP S[35]=$procmux$120_CMP S[36]=$procmux$121_CMP S[37]=$procmux$122_CMP S[38]=$procmux$123_CMP S[39]=$procmux$124_CMP S[40]=$procmux$125_CMP S[41]=$procmux$126_CMP S[42]=$procmux$127_CMP S[43]=$procmux$128_CMP S[44]=$procmux$129_CMP S[45]=$procmux$130_CMP S[46]=$procmux$131_CMP S[47]=$procmux$132_CMP S[48]=$procmux$133_CMP S[49]=$procmux$134_CMP S[50]=$procmux$135_CMP S[51]=$procmux$136_CMP S[52]=$procmux$137_CMP S[53]=$procmux$138_CMP S[54]=$procmux$139_CMP S[55]=$procmux$140_CMP S[56]=$procmux$141_CMP S[57]=$procmux$142_CMP S[58]=$procmux$143_CMP S[59]=$procmux$144_CMP S[60]=$procmux$145_CMP S[61]=$procmux$146_CMP S[62]=$procmux$147_CMP S[63]=$procmux$148_CMP S[64]=$procmux$149_CMP S[65]=$procmux$150_CMP S[66]=$procmux$151_CMP S[67]=$procmux$152_CMP S[68]=$procmux$153_CMP S[69]=$procmux$154_CMP S[70]=$procmux$155_CMP S[71]=$procmux$156_CMP S[72]=$procmux$157_CMP S[73]=$procmux$158_CMP S[74]=$procmux$159_CMP S[75]=$procmux$160_CMP S[76]=$procmux$161_CMP S[77]=$procmux$162_CMP S[78]=$procmux$163_CMP S[79]=$procmux$167_CMP Y=$procmux$84_Y
|
||
|
|
.cname $procmux$84
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param S_WIDTH 00000000000000000000000001010000
|
||
|
|
.param WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$false B[1]=$true B[2]=$true B[3]=$false B[4]=$false B[5]=$false B[6]=$true Y=$procmux$840_CMP
|
||
|
|
.cname $procmux$840_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$true B[1]=$false B[2]=$true B[3]=$false B[4]=$false B[5]=$false B[6]=$true Y=$procmux$841_CMP
|
||
|
|
.cname $procmux$841_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$false B[1]=$false B[2]=$true B[3]=$false B[4]=$false B[5]=$false B[6]=$true Y=$procmux$842_CMP
|
||
|
|
.cname $procmux$842_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$true B[1]=$true B[2]=$false B[3]=$false B[4]=$false B[5]=$false B[6]=$true Y=$procmux$843_CMP
|
||
|
|
.cname $procmux$843_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$false B[1]=$true B[2]=$false B[3]=$false B[4]=$false B[5]=$false B[6]=$true Y=$procmux$844_CMP
|
||
|
|
.cname $procmux$844_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$true B[1]=$false B[2]=$false B[3]=$false B[4]=$false B[5]=$false B[6]=$true Y=$procmux$845_CMP
|
||
|
|
.cname $procmux$845_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$false B[1]=$false B[2]=$false B[3]=$false B[4]=$false B[5]=$false B[6]=$true Y=$procmux$846_CMP
|
||
|
|
.cname $procmux$846_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$true B[1]=$true B[2]=$true B[3]=$true B[4]=$true B[5]=$true B[6]=$false Y=$procmux$847_CMP
|
||
|
|
.cname $procmux$847_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$false B[1]=$true B[2]=$true B[3]=$true B[4]=$true B[5]=$true B[6]=$false Y=$procmux$848_CMP
|
||
|
|
.cname $procmux$848_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$true B[1]=$false B[2]=$true B[3]=$true B[4]=$true B[5]=$true B[6]=$false Y=$procmux$849_CMP
|
||
|
|
.cname $procmux$849_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$false B[1]=$false B[2]=$true B[3]=$true B[4]=$true B[5]=$true B[6]=$false Y=$procmux$850_CMP
|
||
|
|
.cname $procmux$850_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$true B[1]=$true B[2]=$false B[3]=$true B[4]=$true B[5]=$true B[6]=$false Y=$procmux$851_CMP
|
||
|
|
.cname $procmux$851_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$false B[1]=$true B[2]=$false B[3]=$true B[4]=$true B[5]=$true B[6]=$false Y=$procmux$852_CMP
|
||
|
|
.cname $procmux$852_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$true B[1]=$false B[2]=$false B[3]=$true B[4]=$true B[5]=$true B[6]=$false Y=$procmux$853_CMP
|
||
|
|
.cname $procmux$853_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$false B[1]=$false B[2]=$false B[3]=$true B[4]=$true B[5]=$true B[6]=$false Y=$procmux$854_CMP
|
||
|
|
.cname $procmux$854_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$true B[1]=$true B[2]=$true B[3]=$false B[4]=$true B[5]=$true B[6]=$false Y=$procmux$855_CMP
|
||
|
|
.cname $procmux$855_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$false B[1]=$true B[2]=$true B[3]=$false B[4]=$true B[5]=$true B[6]=$false Y=$procmux$856_CMP
|
||
|
|
.cname $procmux$856_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$true B[1]=$false B[2]=$true B[3]=$false B[4]=$true B[5]=$true B[6]=$false Y=$procmux$857_CMP
|
||
|
|
.cname $procmux$857_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$false B[1]=$false B[2]=$true B[3]=$false B[4]=$true B[5]=$true B[6]=$false Y=$procmux$858_CMP
|
||
|
|
.cname $procmux$858_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$true B[1]=$true B[2]=$false B[3]=$false B[4]=$true B[5]=$true B[6]=$false Y=$procmux$859_CMP
|
||
|
|
.cname $procmux$859_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$true B[1]=$true B[2]=$true B[3]=$true B[4]=$false B[5]=$false B[6]=$true Y=$procmux$85_CMP
|
||
|
|
.cname $procmux$85_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$false B[1]=$true B[2]=$false B[3]=$false B[4]=$true B[5]=$true B[6]=$false Y=$procmux$860_CMP
|
||
|
|
.cname $procmux$860_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$true B[1]=$false B[2]=$false B[3]=$false B[4]=$true B[5]=$true B[6]=$false Y=$procmux$861_CMP
|
||
|
|
.cname $procmux$861_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$false B[1]=$false B[2]=$false B[3]=$false B[4]=$true B[5]=$true B[6]=$false Y=$procmux$862_CMP
|
||
|
|
.cname $procmux$862_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$true B[1]=$true B[2]=$true B[3]=$true B[4]=$false B[5]=$true B[6]=$false Y=$procmux$863_CMP
|
||
|
|
.cname $procmux$863_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$false B[1]=$true B[2]=$true B[3]=$true B[4]=$false B[5]=$true B[6]=$false Y=$procmux$864_CMP
|
||
|
|
.cname $procmux$864_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$true B[1]=$false B[2]=$true B[3]=$true B[4]=$false B[5]=$true B[6]=$false Y=$procmux$865_CMP
|
||
|
|
.cname $procmux$865_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$false B[1]=$false B[2]=$true B[3]=$true B[4]=$false B[5]=$true B[6]=$false Y=$procmux$866_CMP
|
||
|
|
.cname $procmux$866_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$true B[1]=$true B[2]=$false B[3]=$true B[4]=$false B[5]=$true B[6]=$false Y=$procmux$867_CMP
|
||
|
|
.cname $procmux$867_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$false B[1]=$true B[2]=$false B[3]=$true B[4]=$false B[5]=$true B[6]=$false Y=$procmux$868_CMP
|
||
|
|
.cname $procmux$868_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$true B[1]=$false B[2]=$false B[3]=$true B[4]=$false B[5]=$true B[6]=$false Y=$procmux$869_CMP
|
||
|
|
.cname $procmux$869_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$false B[1]=$true B[2]=$true B[3]=$true B[4]=$false B[5]=$false B[6]=$true Y=$procmux$86_CMP
|
||
|
|
.cname $procmux$86_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$false B[1]=$false B[2]=$false B[3]=$true B[4]=$false B[5]=$true B[6]=$false Y=$procmux$870_CMP
|
||
|
|
.cname $procmux$870_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$true B[1]=$true B[2]=$true B[3]=$false B[4]=$false B[5]=$true B[6]=$false Y=$procmux$871_CMP
|
||
|
|
.cname $procmux$871_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$false B[1]=$true B[2]=$true B[3]=$false B[4]=$false B[5]=$true B[6]=$false Y=$procmux$872_CMP
|
||
|
|
.cname $procmux$872_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$true B[1]=$false B[2]=$true B[3]=$false B[4]=$false B[5]=$true B[6]=$false Y=$procmux$873_CMP
|
||
|
|
.cname $procmux$873_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$false B[1]=$false B[2]=$true B[3]=$false B[4]=$false B[5]=$true B[6]=$false Y=$procmux$874_CMP
|
||
|
|
.cname $procmux$874_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$true B[1]=$true B[2]=$false B[3]=$false B[4]=$false B[5]=$true B[6]=$false Y=$procmux$875_CMP
|
||
|
|
.cname $procmux$875_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$false B[1]=$true B[2]=$false B[3]=$false B[4]=$false B[5]=$true B[6]=$false Y=$procmux$876_CMP
|
||
|
|
.cname $procmux$876_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$true B[1]=$false B[2]=$false B[3]=$false B[4]=$false B[5]=$true B[6]=$false Y=$procmux$877_CMP
|
||
|
|
.cname $procmux$877_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$false B[1]=$false B[2]=$false B[3]=$false B[4]=$false B[5]=$true B[6]=$false Y=$procmux$878_CMP
|
||
|
|
.cname $procmux$878_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$true B[1]=$true B[2]=$true B[3]=$true B[4]=$true B[5]=$false B[6]=$false Y=$procmux$879_CMP
|
||
|
|
.cname $procmux$879_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$true B[1]=$false B[2]=$true B[3]=$true B[4]=$false B[5]=$false B[6]=$true Y=$procmux$87_CMP
|
||
|
|
.cname $procmux$87_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$false B[1]=$true B[2]=$true B[3]=$true B[4]=$true B[5]=$false B[6]=$false Y=$procmux$880_CMP
|
||
|
|
.cname $procmux$880_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$true B[1]=$false B[2]=$true B[3]=$true B[4]=$true B[5]=$false B[6]=$false Y=$procmux$881_CMP
|
||
|
|
.cname $procmux$881_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$false B[1]=$false B[2]=$true B[3]=$true B[4]=$true B[5]=$false B[6]=$false Y=$procmux$882_CMP
|
||
|
|
.cname $procmux$882_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$true B[1]=$true B[2]=$false B[3]=$true B[4]=$true B[5]=$false B[6]=$false Y=$procmux$883_CMP
|
||
|
|
.cname $procmux$883_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$false B[1]=$true B[2]=$false B[3]=$true B[4]=$true B[5]=$false B[6]=$false Y=$procmux$884_CMP
|
||
|
|
.cname $procmux$884_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$true B[1]=$false B[2]=$false B[3]=$true B[4]=$true B[5]=$false B[6]=$false Y=$procmux$885_CMP
|
||
|
|
.cname $procmux$885_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$false B[1]=$false B[2]=$false B[3]=$true B[4]=$true B[5]=$false B[6]=$false Y=$procmux$886_CMP
|
||
|
|
.cname $procmux$886_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$true B[1]=$true B[2]=$true B[3]=$false B[4]=$true B[5]=$false B[6]=$false Y=$procmux$887_CMP
|
||
|
|
.cname $procmux$887_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$false B[1]=$true B[2]=$true B[3]=$false B[4]=$true B[5]=$false B[6]=$false Y=$procmux$888_CMP
|
||
|
|
.cname $procmux$888_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$true B[1]=$false B[2]=$true B[3]=$false B[4]=$true B[5]=$false B[6]=$false Y=$procmux$889_CMP
|
||
|
|
.cname $procmux$889_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$false B[1]=$false B[2]=$true B[3]=$true B[4]=$false B[5]=$false B[6]=$true Y=$procmux$88_CMP
|
||
|
|
.cname $procmux$88_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$false B[1]=$false B[2]=$true B[3]=$false B[4]=$true B[5]=$false B[6]=$false Y=$procmux$890_CMP
|
||
|
|
.cname $procmux$890_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$true B[1]=$true B[2]=$false B[3]=$false B[4]=$true B[5]=$false B[6]=$false Y=$procmux$891_CMP
|
||
|
|
.cname $procmux$891_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$false B[1]=$true B[2]=$false B[3]=$false B[4]=$true B[5]=$false B[6]=$false Y=$procmux$892_CMP
|
||
|
|
.cname $procmux$892_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$true B[1]=$false B[2]=$false B[3]=$false B[4]=$true B[5]=$false B[6]=$false Y=$procmux$893_CMP
|
||
|
|
.cname $procmux$893_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$false B[1]=$false B[2]=$false B[3]=$false B[4]=$true B[5]=$false B[6]=$false Y=$procmux$894_CMP
|
||
|
|
.cname $procmux$894_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$false B[1]=$true B[2]=$true B[3]=$false B[4]=$false B[5]=$false B[6]=$false Y=$procmux$895_CMP
|
||
|
|
.cname $procmux$895_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $mux A[0]=$procmux$830_Y[0] A[1]=$procmux$830_Y[1] A[2]=$procmux$830_Y[2] A[3]=$procmux$830_Y[3] A[4]=$procmux$830_Y[4] A[5]=$procmux$830_Y[5] A[6]=$procmux$830_Y[6] A[7]=$procmux$830_Y[7] A[8]=$procmux$830_Y[8] A[9]=$procmux$830_Y[9] A[10]=$procmux$830_Y[10] A[11]=$procmux$830_Y[11] A[12]=$procmux$830_Y[12] A[13]=$procmux$830_Y[13] A[14]=$procmux$830_Y[14] A[15]=$procmux$830_Y[15] A[16]=$procmux$830_Y[16] A[17]=$procmux$830_Y[17] A[18]=$procmux$830_Y[18] A[19]=$procmux$830_Y[19] A[20]=$procmux$830_Y[20] A[21]=$procmux$830_Y[21] A[22]=$procmux$830_Y[22] A[23]=$procmux$830_Y[23] A[24]=$procmux$830_Y[24] A[25]=$procmux$830_Y[25] A[26]=$procmux$830_Y[26] A[27]=$procmux$830_Y[27] A[28]=$procmux$830_Y[28] A[29]=$procmux$830_Y[29] A[30]=$procmux$830_Y[30] A[31]=$procmux$830_Y[31] B[0]=$false B[1]=$false B[2]=$false B[3]=$false B[4]=$false B[5]=$false B[6]=$false B[7]=$false B[8]=$false B[9]=$false B[10]=$false B[11]=$false B[12]=$false B[13]=$false B[14]=$false B[15]=$false B[16]=$false B[17]=$false B[18]=$false B[19]=$false B[20]=$false B[21]=$false B[22]=$false B[23]=$false B[24]=$false B[25]=$false B[26]=$false B[27]=$false B[28]=$false B[29]=$false B[30]=$false B[31]=$false S=$procmux$898_CMP Y[0]=$procmux$897_Y[0] Y[1]=$procmux$897_Y[1] Y[2]=$procmux$897_Y[2] Y[3]=$procmux$897_Y[3] Y[4]=$procmux$897_Y[4] Y[5]=$procmux$897_Y[5] Y[6]=$procmux$897_Y[6] Y[7]=$procmux$897_Y[7] Y[8]=$procmux$897_Y[8] Y[9]=$procmux$897_Y[9] Y[10]=$procmux$897_Y[10] Y[11]=$procmux$897_Y[11] Y[12]=$procmux$897_Y[12] Y[13]=$procmux$897_Y[13] Y[14]=$procmux$897_Y[14] Y[15]=$procmux$897_Y[15] Y[16]=$procmux$897_Y[16] Y[17]=$procmux$897_Y[17] Y[18]=$procmux$897_Y[18] Y[19]=$procmux$897_Y[19] Y[20]=$procmux$897_Y[20] Y[21]=$procmux$897_Y[21] Y[22]=$procmux$897_Y[22] Y[23]=$procmux$897_Y[23] Y[24]=$procmux$897_Y[24] Y[25]=$procmux$897_Y[25] Y[26]=$procmux$897_Y[26] Y[27]=$procmux$897_Y[27] Y[28]=$procmux$897_Y[28] Y[29]=$procmux$897_Y[29] Y[30]=$procmux$897_Y[30] Y[31]=$procmux$897_Y[31]
|
||
|
|
.cname $procmux$897
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:150"
|
||
|
|
.param WIDTH 00000000000000000000000000100000
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$true B[1]=$true B[2]=$false B[3]=$true B[4]=$false B[5]=$false B[6]=$true Y=$procmux$89_CMP
|
||
|
|
.cname $procmux$89_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $pmux A[0]=W5[0] A[1]=W5[1] A[2]=W5[2] A[3]=W5[3] A[4]=W5[4] A[5]=W5[5] A[6]=W5[6] A[7]=W5[7] A[8]=W5[8] A[9]=W5[9] A[10]=W5[10] A[11]=W5[11] A[12]=W5[12] A[13]=W5[13] A[14]=W5[14] A[15]=W5[15] A[16]=W5[16] A[17]=W5[17] A[18]=W5[18] A[19]=W5[19] A[20]=W5[20] A[21]=W5[21] A[22]=W5[22] A[23]=W5[23] A[24]=W5[24] A[25]=W5[25] A[26]=W5[26] A[27]=W5[27] A[28]=W5[28] A[29]=W5[29] A[30]=W5[30] A[31]=W5[31] B[0]=W6[0] B[1]=W6[1] B[2]=W6[2] B[3]=W6[3] B[4]=W6[4] B[5]=W6[5] B[6]=W6[6] B[7]=W6[7] B[8]=W6[8] B[9]=W6[9] B[10]=W6[10] B[11]=W6[11] B[12]=W6[12] B[13]=W6[13] B[14]=W6[14] B[15]=W6[15] B[16]=W6[16] B[17]=W6[17] B[18]=W6[18] B[19]=W6[19] B[20]=W6[20] B[21]=W6[21] B[22]=W6[22] B[23]=W6[23] B[24]=W6[24] B[25]=W6[25] B[26]=W6[26] B[27]=W6[27] B[28]=W6[28] B[29]=W6[29] B[30]=W6[30] B[31]=W6[31] B[32]=W6[0] B[33]=W6[1] B[34]=W6[2] B[35]=W6[3] B[36]=W6[4] B[37]=W6[5] B[38]=W6[6] B[39]=W6[7] B[40]=W6[8] B[41]=W6[9] B[42]=W6[10] B[43]=W6[11] B[44]=W6[12] B[45]=W6[13] B[46]=W6[14] B[47]=W6[15] B[48]=W6[16] B[49]=W6[17] B[50]=W6[18] B[51]=W6[19] B[52]=W6[20] B[53]=W6[21] B[54]=W6[22] B[55]=W6[23] B[56]=W6[24] B[57]=W6[25] B[58]=W6[26] B[59]=W6[27] B[60]=W6[28] B[61]=W6[29] B[62]=W6[30] B[63]=W6[31] B[64]=W6[0] B[65]=W6[1] B[66]=W6[2] B[67]=W6[3] B[68]=W6[4] B[69]=W6[5] B[70]=W6[6] B[71]=W6[7] B[72]=W6[8] B[73]=W6[9] B[74]=W6[10] B[75]=W6[11] B[76]=W6[12] B[77]=W6[13] B[78]=W6[14] B[79]=W6[15] B[80]=W6[16] B[81]=W6[17] B[82]=W6[18] B[83]=W6[19] B[84]=W6[20] B[85]=W6[21] B[86]=W6[22] B[87]=W6[23] B[88]=W6[24] B[89]=W6[25] B[90]=W6[26] B[91]=W6[27] B[92]=W6[28] B[93]=W6[29] B[94]=W6[30] B[95]=W6[31] B[96]=W6[0] B[97]=W6[1] B[98]=W6[2] B[99]=W6[3] B[100]=W6[4] B[101]=W6[5] B[102]=W6[6] B[103]=W6[7] B[104]=W6[8] B[105]=W6[9] B[106]=W6[10] B[107]=W6[11] B[108]=W6[12] B[109]=W6[13] B[110]=W6[14] B[111]=W6[15] B[112]=W6[16] B[113]=W6[17] B[114]=W6[18] B[115]=W6[19] B[116]=W6[20] B[117]=W6[21] B[118]=W6[22] B[119]=W6[23] B[120]=W6[24] B[121]=W6[25] B[122]=W6[26] B[123]=W6[27] B[124]=W6[28] B[125]=W6[29] B[126]=W6[30] B[127]=W6[31] B[128]=W6[0] B[129]=W6[1] B[130]=W6[2] B[131]=W6[3] B[132]=W6[4] B[133]=W6[5] B[134]=W6[6] B[135]=W6[7] B[136]=W6[8] B[137]=W6[9] B[138]=W6[10] B[139]=W6[11] B[140]=W6[12] B[141]=W6[13] B[142]=W6[14] B[143]=W6[15] B[144]=W6[16] B[145]=W6[17] B[146]=W6[18] B[147]=W6[19] B[148]=W6[20] B[149]=W6[21] B[150]=W6[22] B[151]=W6[23] B[152]=W6[24] B[153]=W6[25] B[154]=W6[26] B[155]=W6[27] B[156]=W6[28] B[157]=W6[29] B[158]=W6[30] B[159]=W6[31] B[160]=W6[0] B[161]=W6[1] B[162]=W6[2] B[163]=W6[3] B[164]=W6[4] B[165]=W6[5] B[166]=W6[6] B[167]=W6[7] B[168]=W6[8] B[169]=W6[9] B[170]=W6[10] B[171]=W6[11] B[172]=W6[12] B[173]=W6[13] B[174]=W6[14] B[175]=W6[15] B[176]=W6[16] B[177]=W6[17] B[178]=W6[18] B[179]=W6[19] B[180]=W6[20] B[181]=W6[21] B[182]=W6[22] B[183]=W6[23] B[184]=W6[24] B[185]=W6[25] B[186]=W6[26] B[187]=W6[27] B[188]=W6[28] B[189]=W6[29] B[190]=W6[30] B[191]=W6[31] B[192]=W6[0] B[193]=W6[1] B[194]=W6[2] B[195]=W6[3] B[196]=W6[4] B[197]=W6[5] B[198]=W6[6] B[199]=W6[7] B[200]=W6[8] B[201]=W6[9] B[202]=W6[10] B[203]=W6[11] B[204]=W6[12] B[205]=W6[13] B[206]=W6[14] B[207]=W6[15] B[208]=W6[16] B[209]=W6[17] B[210]=W6[18] B[211]=W6[19] B[212]=W6[20] B[213]=W6[21] B[214]=W6[22] B[215]=W6[23] B[216]=W6[24] B[217]=W6[25] B[218]=W6[26] B[219]=W6[27] B[220]=W6[28] B[221]=W6[29] B[222]=W6[30] B[223]=W6[31] B[224]=W6[0] B[225]=W6[1] B[226]=W6[2] B[227]=W6[3] B[228]=W6[4] B[229]=W6[5] B[230]=W6[6] B[231]=W6[7] B[232]=W6[8] B[233]=W6[9] B[234]=W6[10] B[235]=W6[11] B[236]=W6[12] B[237]=W6[13] B[238]=W6[14] B[239]=W6[15] B[240]=W6[16] B[241]=W6[17] B[242]=W6[18] B[243]=W6[19] B[244]=W6[20] B[245]=W6[21] B[246]=W6[22] B[247]=W6[23] B[248]=W6[24] B[249]=W6[25] B[250]=W6[26] B[251]=W6[27] B[252]=W6[28] B[253]=W6[29] B[254]=W6[30] B[255]=W6[31] B[256]=W6[0] B[257]=W6[1] B[258]=W6[2] B[259]=W6[3] B[260]=W6[4] B[261]=W6[5] B[262]=W6[6] B[263]=W6[7] B[264]=W6[8] B[265]=W6[9] B[266]=W6[10] B[267]=W6[11] B[268]=W6[12] B[269]=W6[13] B[270]=W6[14] B[271]=W6[15] B[272]=W6[16] B[273]=W6[17] B[274]=W6[18] B[275]=W6[19] B[276]=W6[20] B[277]=
|
||
|
|
.cname $procmux$901
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param S_WIDTH 00000000000000000000000001000001
|
||
|
|
.param WIDTH 00000000000000000000000000100000
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$true B[1]=$true B[2]=$true B[3]=$true B[4]=$false B[5]=$false B[6]=$true Y=$procmux$902_CMP
|
||
|
|
.cname $procmux$902_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$false B[1]=$true B[2]=$true B[3]=$true B[4]=$false B[5]=$false B[6]=$true Y=$procmux$903_CMP
|
||
|
|
.cname $procmux$903_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$true B[1]=$false B[2]=$true B[3]=$true B[4]=$false B[5]=$false B[6]=$true Y=$procmux$904_CMP
|
||
|
|
.cname $procmux$904_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$false B[1]=$false B[2]=$true B[3]=$true B[4]=$false B[5]=$false B[6]=$true Y=$procmux$905_CMP
|
||
|
|
.cname $procmux$905_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$true B[1]=$true B[2]=$false B[3]=$true B[4]=$false B[5]=$false B[6]=$true Y=$procmux$906_CMP
|
||
|
|
.cname $procmux$906_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$false B[1]=$true B[2]=$false B[3]=$true B[4]=$false B[5]=$false B[6]=$true Y=$procmux$907_CMP
|
||
|
|
.cname $procmux$907_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$true B[1]=$false B[2]=$false B[3]=$true B[4]=$false B[5]=$false B[6]=$true Y=$procmux$908_CMP
|
||
|
|
.cname $procmux$908_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$false B[1]=$false B[2]=$false B[3]=$true B[4]=$false B[5]=$false B[6]=$true Y=$procmux$909_CMP
|
||
|
|
.cname $procmux$909_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$false B[1]=$true B[2]=$false B[3]=$true B[4]=$false B[5]=$false B[6]=$true Y=$procmux$90_CMP
|
||
|
|
.cname $procmux$90_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$true B[1]=$true B[2]=$true B[3]=$false B[4]=$false B[5]=$false B[6]=$true Y=$procmux$910_CMP
|
||
|
|
.cname $procmux$910_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$false B[1]=$true B[2]=$true B[3]=$false B[4]=$false B[5]=$false B[6]=$true Y=$procmux$911_CMP
|
||
|
|
.cname $procmux$911_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$true B[1]=$false B[2]=$true B[3]=$false B[4]=$false B[5]=$false B[6]=$true Y=$procmux$912_CMP
|
||
|
|
.cname $procmux$912_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$false B[1]=$false B[2]=$true B[3]=$false B[4]=$false B[5]=$false B[6]=$true Y=$procmux$913_CMP
|
||
|
|
.cname $procmux$913_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$true B[1]=$true B[2]=$false B[3]=$false B[4]=$false B[5]=$false B[6]=$true Y=$procmux$914_CMP
|
||
|
|
.cname $procmux$914_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$false B[1]=$true B[2]=$false B[3]=$false B[4]=$false B[5]=$false B[6]=$true Y=$procmux$915_CMP
|
||
|
|
.cname $procmux$915_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$true B[1]=$false B[2]=$false B[3]=$false B[4]=$false B[5]=$false B[6]=$true Y=$procmux$916_CMP
|
||
|
|
.cname $procmux$916_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$false B[1]=$false B[2]=$false B[3]=$false B[4]=$false B[5]=$false B[6]=$true Y=$procmux$917_CMP
|
||
|
|
.cname $procmux$917_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$true B[1]=$true B[2]=$true B[3]=$true B[4]=$true B[5]=$true B[6]=$false Y=$procmux$918_CMP
|
||
|
|
.cname $procmux$918_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$false B[1]=$true B[2]=$true B[3]=$true B[4]=$true B[5]=$true B[6]=$false Y=$procmux$919_CMP
|
||
|
|
.cname $procmux$919_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$true B[1]=$false B[2]=$false B[3]=$true B[4]=$false B[5]=$false B[6]=$true Y=$procmux$91_CMP
|
||
|
|
.cname $procmux$91_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$true B[1]=$false B[2]=$true B[3]=$true B[4]=$true B[5]=$true B[6]=$false Y=$procmux$920_CMP
|
||
|
|
.cname $procmux$920_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$false B[1]=$false B[2]=$true B[3]=$true B[4]=$true B[5]=$true B[6]=$false Y=$procmux$921_CMP
|
||
|
|
.cname $procmux$921_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$true B[1]=$true B[2]=$false B[3]=$true B[4]=$true B[5]=$true B[6]=$false Y=$procmux$922_CMP
|
||
|
|
.cname $procmux$922_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$false B[1]=$true B[2]=$false B[3]=$true B[4]=$true B[5]=$true B[6]=$false Y=$procmux$923_CMP
|
||
|
|
.cname $procmux$923_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$true B[1]=$false B[2]=$false B[3]=$true B[4]=$true B[5]=$true B[6]=$false Y=$procmux$924_CMP
|
||
|
|
.cname $procmux$924_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$false B[1]=$false B[2]=$false B[3]=$true B[4]=$true B[5]=$true B[6]=$false Y=$procmux$925_CMP
|
||
|
|
.cname $procmux$925_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$true B[1]=$true B[2]=$true B[3]=$false B[4]=$true B[5]=$true B[6]=$false Y=$procmux$926_CMP
|
||
|
|
.cname $procmux$926_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$false B[1]=$true B[2]=$true B[3]=$false B[4]=$true B[5]=$true B[6]=$false Y=$procmux$927_CMP
|
||
|
|
.cname $procmux$927_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$true B[1]=$false B[2]=$true B[3]=$false B[4]=$true B[5]=$true B[6]=$false Y=$procmux$928_CMP
|
||
|
|
.cname $procmux$928_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$false B[1]=$false B[2]=$true B[3]=$false B[4]=$true B[5]=$true B[6]=$false Y=$procmux$929_CMP
|
||
|
|
.cname $procmux$929_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$false B[1]=$false B[2]=$false B[3]=$true B[4]=$false B[5]=$false B[6]=$true Y=$procmux$92_CMP
|
||
|
|
.cname $procmux$92_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$true B[1]=$true B[2]=$false B[3]=$false B[4]=$true B[5]=$true B[6]=$false Y=$procmux$930_CMP
|
||
|
|
.cname $procmux$930_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$false B[1]=$true B[2]=$false B[3]=$false B[4]=$true B[5]=$true B[6]=$false Y=$procmux$931_CMP
|
||
|
|
.cname $procmux$931_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$true B[1]=$false B[2]=$false B[3]=$false B[4]=$true B[5]=$true B[6]=$false Y=$procmux$932_CMP
|
||
|
|
.cname $procmux$932_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$false B[1]=$false B[2]=$false B[3]=$false B[4]=$true B[5]=$true B[6]=$false Y=$procmux$933_CMP
|
||
|
|
.cname $procmux$933_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$true B[1]=$true B[2]=$true B[3]=$true B[4]=$false B[5]=$true B[6]=$false Y=$procmux$934_CMP
|
||
|
|
.cname $procmux$934_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$false B[1]=$true B[2]=$true B[3]=$true B[4]=$false B[5]=$true B[6]=$false Y=$procmux$935_CMP
|
||
|
|
.cname $procmux$935_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$true B[1]=$false B[2]=$true B[3]=$true B[4]=$false B[5]=$true B[6]=$false Y=$procmux$936_CMP
|
||
|
|
.cname $procmux$936_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$false B[1]=$false B[2]=$true B[3]=$true B[4]=$false B[5]=$true B[6]=$false Y=$procmux$937_CMP
|
||
|
|
.cname $procmux$937_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$true B[1]=$true B[2]=$false B[3]=$true B[4]=$false B[5]=$true B[6]=$false Y=$procmux$938_CMP
|
||
|
|
.cname $procmux$938_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$false B[1]=$true B[2]=$false B[3]=$true B[4]=$false B[5]=$true B[6]=$false Y=$procmux$939_CMP
|
||
|
|
.cname $procmux$939_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$true B[1]=$true B[2]=$true B[3]=$false B[4]=$false B[5]=$false B[6]=$true Y=$procmux$93_CMP
|
||
|
|
.cname $procmux$93_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$true B[1]=$false B[2]=$false B[3]=$true B[4]=$false B[5]=$true B[6]=$false Y=$procmux$940_CMP
|
||
|
|
.cname $procmux$940_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$false B[1]=$false B[2]=$false B[3]=$true B[4]=$false B[5]=$true B[6]=$false Y=$procmux$941_CMP
|
||
|
|
.cname $procmux$941_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$true B[1]=$true B[2]=$true B[3]=$false B[4]=$false B[5]=$true B[6]=$false Y=$procmux$942_CMP
|
||
|
|
.cname $procmux$942_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$false B[1]=$true B[2]=$true B[3]=$false B[4]=$false B[5]=$true B[6]=$false Y=$procmux$943_CMP
|
||
|
|
.cname $procmux$943_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$true B[1]=$false B[2]=$true B[3]=$false B[4]=$false B[5]=$true B[6]=$false Y=$procmux$944_CMP
|
||
|
|
.cname $procmux$944_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$false B[1]=$false B[2]=$true B[3]=$false B[4]=$false B[5]=$true B[6]=$false Y=$procmux$945_CMP
|
||
|
|
.cname $procmux$945_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$true B[1]=$true B[2]=$false B[3]=$false B[4]=$false B[5]=$true B[6]=$false Y=$procmux$946_CMP
|
||
|
|
.cname $procmux$946_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$false B[1]=$true B[2]=$false B[3]=$false B[4]=$false B[5]=$true B[6]=$false Y=$procmux$947_CMP
|
||
|
|
.cname $procmux$947_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$true B[1]=$false B[2]=$false B[3]=$false B[4]=$false B[5]=$true B[6]=$false Y=$procmux$948_CMP
|
||
|
|
.cname $procmux$948_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$false B[1]=$false B[2]=$false B[3]=$false B[4]=$false B[5]=$true B[6]=$false Y=$procmux$949_CMP
|
||
|
|
.cname $procmux$949_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$false B[1]=$true B[2]=$true B[3]=$false B[4]=$false B[5]=$false B[6]=$true Y=$procmux$94_CMP
|
||
|
|
.cname $procmux$94_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$true B[1]=$true B[2]=$true B[3]=$true B[4]=$true B[5]=$false B[6]=$false Y=$procmux$950_CMP
|
||
|
|
.cname $procmux$950_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$false B[1]=$true B[2]=$true B[3]=$true B[4]=$true B[5]=$false B[6]=$false Y=$procmux$951_CMP
|
||
|
|
.cname $procmux$951_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$true B[1]=$false B[2]=$true B[3]=$true B[4]=$true B[5]=$false B[6]=$false Y=$procmux$952_CMP
|
||
|
|
.cname $procmux$952_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$false B[1]=$false B[2]=$true B[3]=$true B[4]=$true B[5]=$false B[6]=$false Y=$procmux$953_CMP
|
||
|
|
.cname $procmux$953_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$true B[1]=$true B[2]=$false B[3]=$true B[4]=$true B[5]=$false B[6]=$false Y=$procmux$954_CMP
|
||
|
|
.cname $procmux$954_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$false B[1]=$true B[2]=$false B[3]=$true B[4]=$true B[5]=$false B[6]=$false Y=$procmux$955_CMP
|
||
|
|
.cname $procmux$955_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$true B[1]=$false B[2]=$false B[3]=$true B[4]=$true B[5]=$false B[6]=$false Y=$procmux$956_CMP
|
||
|
|
.cname $procmux$956_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$false B[1]=$false B[2]=$false B[3]=$true B[4]=$true B[5]=$false B[6]=$false Y=$procmux$957_CMP
|
||
|
|
.cname $procmux$957_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$true B[1]=$true B[2]=$true B[3]=$false B[4]=$true B[5]=$false B[6]=$false Y=$procmux$958_CMP
|
||
|
|
.cname $procmux$958_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$false B[1]=$true B[2]=$true B[3]=$false B[4]=$true B[5]=$false B[6]=$false Y=$procmux$959_CMP
|
||
|
|
.cname $procmux$959_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$true B[1]=$false B[2]=$true B[3]=$false B[4]=$false B[5]=$false B[6]=$true Y=$procmux$95_CMP
|
||
|
|
.cname $procmux$95_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$true B[1]=$false B[2]=$true B[3]=$false B[4]=$true B[5]=$false B[6]=$false Y=$procmux$960_CMP
|
||
|
|
.cname $procmux$960_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$false B[1]=$false B[2]=$true B[3]=$false B[4]=$true B[5]=$false B[6]=$false Y=$procmux$961_CMP
|
||
|
|
.cname $procmux$961_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$true B[1]=$true B[2]=$false B[3]=$false B[4]=$true B[5]=$false B[6]=$false Y=$procmux$962_CMP
|
||
|
|
.cname $procmux$962_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$false B[1]=$true B[2]=$false B[3]=$false B[4]=$true B[5]=$false B[6]=$false Y=$procmux$963_CMP
|
||
|
|
.cname $procmux$963_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$true B[1]=$false B[2]=$false B[3]=$false B[4]=$true B[5]=$false B[6]=$false Y=$procmux$964_CMP
|
||
|
|
.cname $procmux$964_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$false B[1]=$false B[2]=$false B[3]=$false B[4]=$true B[5]=$false B[6]=$false Y=$procmux$965_CMP
|
||
|
|
.cname $procmux$965_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$true B[1]=$false B[2]=$true B[3]=$false B[4]=$false B[5]=$false B[6]=$false Y=$procmux$966_CMP
|
||
|
|
.cname $procmux$966_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $mux A[0]=$procmux$901_Y[0] A[1]=$procmux$901_Y[1] A[2]=$procmux$901_Y[2] A[3]=$procmux$901_Y[3] A[4]=$procmux$901_Y[4] A[5]=$procmux$901_Y[5] A[6]=$procmux$901_Y[6] A[7]=$procmux$901_Y[7] A[8]=$procmux$901_Y[8] A[9]=$procmux$901_Y[9] A[10]=$procmux$901_Y[10] A[11]=$procmux$901_Y[11] A[12]=$procmux$901_Y[12] A[13]=$procmux$901_Y[13] A[14]=$procmux$901_Y[14] A[15]=$procmux$901_Y[15] A[16]=$procmux$901_Y[16] A[17]=$procmux$901_Y[17] A[18]=$procmux$901_Y[18] A[19]=$procmux$901_Y[19] A[20]=$procmux$901_Y[20] A[21]=$procmux$901_Y[21] A[22]=$procmux$901_Y[22] A[23]=$procmux$901_Y[23] A[24]=$procmux$901_Y[24] A[25]=$procmux$901_Y[25] A[26]=$procmux$901_Y[26] A[27]=$procmux$901_Y[27] A[28]=$procmux$901_Y[28] A[29]=$procmux$901_Y[29] A[30]=$procmux$901_Y[30] A[31]=$procmux$901_Y[31] B[0]=$false B[1]=$false B[2]=$false B[3]=$false B[4]=$false B[5]=$false B[6]=$false B[7]=$false B[8]=$false B[9]=$false B[10]=$false B[11]=$false B[12]=$false B[13]=$false B[14]=$false B[15]=$false B[16]=$false B[17]=$false B[18]=$false B[19]=$false B[20]=$false B[21]=$false B[22]=$false B[23]=$false B[24]=$false B[25]=$false B[26]=$false B[27]=$false B[28]=$false B[29]=$false B[30]=$false B[31]=$false S=$procmux$969_CMP Y[0]=$procmux$968_Y[0] Y[1]=$procmux$968_Y[1] Y[2]=$procmux$968_Y[2] Y[3]=$procmux$968_Y[3] Y[4]=$procmux$968_Y[4] Y[5]=$procmux$968_Y[5] Y[6]=$procmux$968_Y[6] Y[7]=$procmux$968_Y[7] Y[8]=$procmux$968_Y[8] Y[9]=$procmux$968_Y[9] Y[10]=$procmux$968_Y[10] Y[11]=$procmux$968_Y[11] Y[12]=$procmux$968_Y[12] Y[13]=$procmux$968_Y[13] Y[14]=$procmux$968_Y[14] Y[15]=$procmux$968_Y[15] Y[16]=$procmux$968_Y[16] Y[17]=$procmux$968_Y[17] Y[18]=$procmux$968_Y[18] Y[19]=$procmux$968_Y[19] Y[20]=$procmux$968_Y[20] Y[21]=$procmux$968_Y[21] Y[22]=$procmux$968_Y[22] Y[23]=$procmux$968_Y[23] Y[24]=$procmux$968_Y[24] Y[25]=$procmux$968_Y[25] Y[26]=$procmux$968_Y[26] Y[27]=$procmux$968_Y[27] Y[28]=$procmux$968_Y[28] Y[29]=$procmux$968_Y[29] Y[30]=$procmux$968_Y[30] Y[31]=$procmux$968_Y[31]
|
||
|
|
.cname $procmux$968
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:150"
|
||
|
|
.param WIDTH 00000000000000000000000000100000
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$false B[1]=$false B[2]=$true B[3]=$false B[4]=$false B[5]=$false B[6]=$true Y=$procmux$96_CMP
|
||
|
|
.cname $procmux$96_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $pmux A[0]=W4[0] A[1]=W4[1] A[2]=W4[2] A[3]=W4[3] A[4]=W4[4] A[5]=W4[5] A[6]=W4[6] A[7]=W4[7] A[8]=W4[8] A[9]=W4[9] A[10]=W4[10] A[11]=W4[11] A[12]=W4[12] A[13]=W4[13] A[14]=W4[14] A[15]=W4[15] A[16]=W4[16] A[17]=W4[17] A[18]=W4[18] A[19]=W4[19] A[20]=W4[20] A[21]=W4[21] A[22]=W4[22] A[23]=W4[23] A[24]=W4[24] A[25]=W4[25] A[26]=W4[26] A[27]=W4[27] A[28]=W4[28] A[29]=W4[29] A[30]=W4[30] A[31]=W4[31] B[0]=W5[0] B[1]=W5[1] B[2]=W5[2] B[3]=W5[3] B[4]=W5[4] B[5]=W5[5] B[6]=W5[6] B[7]=W5[7] B[8]=W5[8] B[9]=W5[9] B[10]=W5[10] B[11]=W5[11] B[12]=W5[12] B[13]=W5[13] B[14]=W5[14] B[15]=W5[15] B[16]=W5[16] B[17]=W5[17] B[18]=W5[18] B[19]=W5[19] B[20]=W5[20] B[21]=W5[21] B[22]=W5[22] B[23]=W5[23] B[24]=W5[24] B[25]=W5[25] B[26]=W5[26] B[27]=W5[27] B[28]=W5[28] B[29]=W5[29] B[30]=W5[30] B[31]=W5[31] B[32]=W5[0] B[33]=W5[1] B[34]=W5[2] B[35]=W5[3] B[36]=W5[4] B[37]=W5[5] B[38]=W5[6] B[39]=W5[7] B[40]=W5[8] B[41]=W5[9] B[42]=W5[10] B[43]=W5[11] B[44]=W5[12] B[45]=W5[13] B[46]=W5[14] B[47]=W5[15] B[48]=W5[16] B[49]=W5[17] B[50]=W5[18] B[51]=W5[19] B[52]=W5[20] B[53]=W5[21] B[54]=W5[22] B[55]=W5[23] B[56]=W5[24] B[57]=W5[25] B[58]=W5[26] B[59]=W5[27] B[60]=W5[28] B[61]=W5[29] B[62]=W5[30] B[63]=W5[31] B[64]=W5[0] B[65]=W5[1] B[66]=W5[2] B[67]=W5[3] B[68]=W5[4] B[69]=W5[5] B[70]=W5[6] B[71]=W5[7] B[72]=W5[8] B[73]=W5[9] B[74]=W5[10] B[75]=W5[11] B[76]=W5[12] B[77]=W5[13] B[78]=W5[14] B[79]=W5[15] B[80]=W5[16] B[81]=W5[17] B[82]=W5[18] B[83]=W5[19] B[84]=W5[20] B[85]=W5[21] B[86]=W5[22] B[87]=W5[23] B[88]=W5[24] B[89]=W5[25] B[90]=W5[26] B[91]=W5[27] B[92]=W5[28] B[93]=W5[29] B[94]=W5[30] B[95]=W5[31] B[96]=W5[0] B[97]=W5[1] B[98]=W5[2] B[99]=W5[3] B[100]=W5[4] B[101]=W5[5] B[102]=W5[6] B[103]=W5[7] B[104]=W5[8] B[105]=W5[9] B[106]=W5[10] B[107]=W5[11] B[108]=W5[12] B[109]=W5[13] B[110]=W5[14] B[111]=W5[15] B[112]=W5[16] B[113]=W5[17] B[114]=W5[18] B[115]=W5[19] B[116]=W5[20] B[117]=W5[21] B[118]=W5[22] B[119]=W5[23] B[120]=W5[24] B[121]=W5[25] B[122]=W5[26] B[123]=W5[27] B[124]=W5[28] B[125]=W5[29] B[126]=W5[30] B[127]=W5[31] B[128]=W5[0] B[129]=W5[1] B[130]=W5[2] B[131]=W5[3] B[132]=W5[4] B[133]=W5[5] B[134]=W5[6] B[135]=W5[7] B[136]=W5[8] B[137]=W5[9] B[138]=W5[10] B[139]=W5[11] B[140]=W5[12] B[141]=W5[13] B[142]=W5[14] B[143]=W5[15] B[144]=W5[16] B[145]=W5[17] B[146]=W5[18] B[147]=W5[19] B[148]=W5[20] B[149]=W5[21] B[150]=W5[22] B[151]=W5[23] B[152]=W5[24] B[153]=W5[25] B[154]=W5[26] B[155]=W5[27] B[156]=W5[28] B[157]=W5[29] B[158]=W5[30] B[159]=W5[31] B[160]=W5[0] B[161]=W5[1] B[162]=W5[2] B[163]=W5[3] B[164]=W5[4] B[165]=W5[5] B[166]=W5[6] B[167]=W5[7] B[168]=W5[8] B[169]=W5[9] B[170]=W5[10] B[171]=W5[11] B[172]=W5[12] B[173]=W5[13] B[174]=W5[14] B[175]=W5[15] B[176]=W5[16] B[177]=W5[17] B[178]=W5[18] B[179]=W5[19] B[180]=W5[20] B[181]=W5[21] B[182]=W5[22] B[183]=W5[23] B[184]=W5[24] B[185]=W5[25] B[186]=W5[26] B[187]=W5[27] B[188]=W5[28] B[189]=W5[29] B[190]=W5[30] B[191]=W5[31] B[192]=W5[0] B[193]=W5[1] B[194]=W5[2] B[195]=W5[3] B[196]=W5[4] B[197]=W5[5] B[198]=W5[6] B[199]=W5[7] B[200]=W5[8] B[201]=W5[9] B[202]=W5[10] B[203]=W5[11] B[204]=W5[12] B[205]=W5[13] B[206]=W5[14] B[207]=W5[15] B[208]=W5[16] B[209]=W5[17] B[210]=W5[18] B[211]=W5[19] B[212]=W5[20] B[213]=W5[21] B[214]=W5[22] B[215]=W5[23] B[216]=W5[24] B[217]=W5[25] B[218]=W5[26] B[219]=W5[27] B[220]=W5[28] B[221]=W5[29] B[222]=W5[30] B[223]=W5[31] B[224]=W5[0] B[225]=W5[1] B[226]=W5[2] B[227]=W5[3] B[228]=W5[4] B[229]=W5[5] B[230]=W5[6] B[231]=W5[7] B[232]=W5[8] B[233]=W5[9] B[234]=W5[10] B[235]=W5[11] B[236]=W5[12] B[237]=W5[13] B[238]=W5[14] B[239]=W5[15] B[240]=W5[16] B[241]=W5[17] B[242]=W5[18] B[243]=W5[19] B[244]=W5[20] B[245]=W5[21] B[246]=W5[22] B[247]=W5[23] B[248]=W5[24] B[249]=W5[25] B[250]=W5[26] B[251]=W5[27] B[252]=W5[28] B[253]=W5[29] B[254]=W5[30] B[255]=W5[31] B[256]=W5[0] B[257]=W5[1] B[258]=W5[2] B[259]=W5[3] B[260]=W5[4] B[261]=W5[5] B[262]=W5[6] B[263]=W5[7] B[264]=W5[8] B[265]=W5[9] B[266]=W5[10] B[267]=W5[11] B[268]=W5[12] B[269]=W5[13] B[270]=W5[14] B[271]=W5[15] B[272]=W5[16] B[273]=W5[17] B[274]=W5[18] B[275]=W5[19] B[276]=W5[20] B[277]=
|
||
|
|
.cname $procmux$972
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param S_WIDTH 00000000000000000000000001000001
|
||
|
|
.param WIDTH 00000000000000000000000000100000
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$true B[1]=$true B[2]=$true B[3]=$true B[4]=$false B[5]=$false B[6]=$true Y=$procmux$973_CMP
|
||
|
|
.cname $procmux$973_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$false B[1]=$true B[2]=$true B[3]=$true B[4]=$false B[5]=$false B[6]=$true Y=$procmux$974_CMP
|
||
|
|
.cname $procmux$974_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$true B[1]=$false B[2]=$true B[3]=$true B[4]=$false B[5]=$false B[6]=$true Y=$procmux$975_CMP
|
||
|
|
.cname $procmux$975_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$false B[1]=$false B[2]=$true B[3]=$true B[4]=$false B[5]=$false B[6]=$true Y=$procmux$976_CMP
|
||
|
|
.cname $procmux$976_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$true B[1]=$true B[2]=$false B[3]=$true B[4]=$false B[5]=$false B[6]=$true Y=$procmux$977_CMP
|
||
|
|
.cname $procmux$977_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$false B[1]=$true B[2]=$false B[3]=$true B[4]=$false B[5]=$false B[6]=$true Y=$procmux$978_CMP
|
||
|
|
.cname $procmux$978_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$true B[1]=$false B[2]=$false B[3]=$true B[4]=$false B[5]=$false B[6]=$true Y=$procmux$979_CMP
|
||
|
|
.cname $procmux$979_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$true B[1]=$true B[2]=$false B[3]=$false B[4]=$false B[5]=$false B[6]=$true Y=$procmux$97_CMP
|
||
|
|
.cname $procmux$97_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$false B[1]=$false B[2]=$false B[3]=$true B[4]=$false B[5]=$false B[6]=$true Y=$procmux$980_CMP
|
||
|
|
.cname $procmux$980_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$true B[1]=$true B[2]=$true B[3]=$false B[4]=$false B[5]=$false B[6]=$true Y=$procmux$981_CMP
|
||
|
|
.cname $procmux$981_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$false B[1]=$true B[2]=$true B[3]=$false B[4]=$false B[5]=$false B[6]=$true Y=$procmux$982_CMP
|
||
|
|
.cname $procmux$982_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$true B[1]=$false B[2]=$true B[3]=$false B[4]=$false B[5]=$false B[6]=$true Y=$procmux$983_CMP
|
||
|
|
.cname $procmux$983_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$false B[1]=$false B[2]=$true B[3]=$false B[4]=$false B[5]=$false B[6]=$true Y=$procmux$984_CMP
|
||
|
|
.cname $procmux$984_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$true B[1]=$true B[2]=$false B[3]=$false B[4]=$false B[5]=$false B[6]=$true Y=$procmux$985_CMP
|
||
|
|
.cname $procmux$985_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$false B[1]=$true B[2]=$false B[3]=$false B[4]=$false B[5]=$false B[6]=$true Y=$procmux$986_CMP
|
||
|
|
.cname $procmux$986_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$true B[1]=$false B[2]=$false B[3]=$false B[4]=$false B[5]=$false B[6]=$true Y=$procmux$987_CMP
|
||
|
|
.cname $procmux$987_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$false B[1]=$false B[2]=$false B[3]=$false B[4]=$false B[5]=$false B[6]=$true Y=$procmux$988_CMP
|
||
|
|
.cname $procmux$988_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$true B[1]=$true B[2]=$true B[3]=$true B[4]=$true B[5]=$true B[6]=$false Y=$procmux$989_CMP
|
||
|
|
.cname $procmux$989_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$false B[1]=$true B[2]=$false B[3]=$false B[4]=$false B[5]=$false B[6]=$true Y=$procmux$98_CMP
|
||
|
|
.cname $procmux$98_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$false B[1]=$true B[2]=$true B[3]=$true B[4]=$true B[5]=$true B[6]=$false Y=$procmux$990_CMP
|
||
|
|
.cname $procmux$990_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$true B[1]=$false B[2]=$true B[3]=$true B[4]=$true B[5]=$true B[6]=$false Y=$procmux$991_CMP
|
||
|
|
.cname $procmux$991_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$false B[1]=$false B[2]=$true B[3]=$true B[4]=$true B[5]=$true B[6]=$false Y=$procmux$992_CMP
|
||
|
|
.cname $procmux$992_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$true B[1]=$true B[2]=$false B[3]=$true B[4]=$true B[5]=$true B[6]=$false Y=$procmux$993_CMP
|
||
|
|
.cname $procmux$993_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$false B[1]=$true B[2]=$false B[3]=$true B[4]=$true B[5]=$true B[6]=$false Y=$procmux$994_CMP
|
||
|
|
.cname $procmux$994_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$true B[1]=$false B[2]=$false B[3]=$true B[4]=$true B[5]=$true B[6]=$false Y=$procmux$995_CMP
|
||
|
|
.cname $procmux$995_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$false B[1]=$false B[2]=$false B[3]=$true B[4]=$true B[5]=$true B[6]=$false Y=$procmux$996_CMP
|
||
|
|
.cname $procmux$996_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$true B[1]=$true B[2]=$true B[3]=$false B[4]=$true B[5]=$true B[6]=$false Y=$procmux$997_CMP
|
||
|
|
.cname $procmux$997_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$false B[1]=$true B[2]=$true B[3]=$false B[4]=$true B[5]=$true B[6]=$false Y=$procmux$998_CMP
|
||
|
|
.cname $procmux$998_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$true B[1]=$false B[2]=$true B[3]=$false B[4]=$true B[5]=$true B[6]=$false Y=$procmux$999_CMP
|
||
|
|
.cname $procmux$999_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $eq A[0]=round[0] A[1]=round[1] A[2]=round[2] A[3]=round[3] A[4]=round[4] A[5]=round[5] A[6]=round[6] B[0]=$true B[1]=$false B[2]=$false B[3]=$false B[4]=$false B[5]=$false B[6]=$true Y=$procmux$99_CMP
|
||
|
|
.cname $procmux$99_CMP0
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:187"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000111
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $reduce_or A[0]=read_counter[0] A[1]=read_counter[1] A[2]=read_counter[2] Y=$reduce_or$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:2159$40_Y
|
||
|
|
.cname $reduce_or$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:2159$40
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:2159"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000011
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000001
|
||
|
|
.subckt $sub A[0]=read_counter[0] A[1]=read_counter[1] A[2]=read_counter[2] B[0]=$true B[1]=$false B[2]=$false B[3]=$false B[4]=$false B[5]=$false B[6]=$false Y[0]=$sub$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:2160$41_Y[0] Y[1]=$sub$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:2160$41_Y[1] Y[2]=$sub$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:2160$41_Y[2] Y[3]=$sub$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:2160$41_Y[3] Y[4]=$sub$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:2160$41_Y[4] Y[5]=$sub$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:2160$41_Y[5] Y[6]=$sub$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:2160$41_Y[6]
|
||
|
|
.cname $sub$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:2160$41
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:2160"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000000011
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000000111
|
||
|
|
.param Y_WIDTH 00000000000000000000000000000111
|
||
|
|
.subckt $mux A[0]=SHA1_f2_BCD[0] A[1]=SHA1_f2_BCD[1] A[2]=SHA1_f2_BCD[2] A[3]=SHA1_f2_BCD[3] A[4]=SHA1_f2_BCD[4] A[5]=SHA1_f2_BCD[5] A[6]=SHA1_f2_BCD[6] A[7]=SHA1_f2_BCD[7] A[8]=SHA1_f2_BCD[8] A[9]=SHA1_f2_BCD[9] A[10]=SHA1_f2_BCD[10] A[11]=SHA1_f2_BCD[11] A[12]=SHA1_f2_BCD[12] A[13]=SHA1_f2_BCD[13] A[14]=SHA1_f2_BCD[14] A[15]=SHA1_f2_BCD[15] A[16]=SHA1_f2_BCD[16] A[17]=SHA1_f2_BCD[17] A[18]=SHA1_f2_BCD[18] A[19]=SHA1_f2_BCD[19] A[20]=SHA1_f2_BCD[20] A[21]=SHA1_f2_BCD[21] A[22]=SHA1_f2_BCD[22] A[23]=SHA1_f2_BCD[23] A[24]=SHA1_f2_BCD[24] A[25]=SHA1_f2_BCD[25] A[26]=SHA1_f2_BCD[26] A[27]=SHA1_f2_BCD[27] A[28]=SHA1_f2_BCD[28] A[29]=SHA1_f2_BCD[29] A[30]=SHA1_f2_BCD[30] A[31]=SHA1_f2_BCD[31] B[0]=SHA1_f3_BCD[0] B[1]=SHA1_f3_BCD[1] B[2]=SHA1_f3_BCD[2] B[3]=SHA1_f3_BCD[3] B[4]=SHA1_f3_BCD[4] B[5]=SHA1_f3_BCD[5] B[6]=SHA1_f3_BCD[6] B[7]=SHA1_f3_BCD[7] B[8]=SHA1_f3_BCD[8] B[9]=SHA1_f3_BCD[9] B[10]=SHA1_f3_BCD[10] B[11]=SHA1_f3_BCD[11] B[12]=SHA1_f3_BCD[12] B[13]=SHA1_f3_BCD[13] B[14]=SHA1_f3_BCD[14] B[15]=SHA1_f3_BCD[15] B[16]=SHA1_f3_BCD[16] B[17]=SHA1_f3_BCD[17] B[18]=SHA1_f3_BCD[18] B[19]=SHA1_f3_BCD[19] B[20]=SHA1_f3_BCD[20] B[21]=SHA1_f3_BCD[21] B[22]=SHA1_f3_BCD[22] B[23]=SHA1_f3_BCD[23] B[24]=SHA1_f3_BCD[24] B[25]=SHA1_f3_BCD[25] B[26]=SHA1_f3_BCD[26] B[27]=SHA1_f3_BCD[27] B[28]=SHA1_f3_BCD[28] B[29]=SHA1_f3_BCD[29] B[30]=SHA1_f3_BCD[30] B[31]=SHA1_f3_BCD[31] S=$lt$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:131$16_Y Y[0]=$ternary$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:131$17_Y[0] Y[1]=$ternary$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:131$17_Y[1] Y[2]=$ternary$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:131$17_Y[2] Y[3]=$ternary$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:131$17_Y[3] Y[4]=$ternary$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:131$17_Y[4] Y[5]=$ternary$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:131$17_Y[5] Y[6]=$ternary$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:131$17_Y[6] Y[7]=$ternary$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:131$17_Y[7] Y[8]=$ternary$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:131$17_Y[8] Y[9]=$ternary$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:131$17_Y[9] Y[10]=$ternary$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:131$17_Y[10] Y[11]=$ternary$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:131$17_Y[11] Y[12]=$ternary$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:131$17_Y[12] Y[13]=$ternary$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:131$17_Y[13] Y[14]=$ternary$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:131$17_Y[14] Y[15]=$ternary$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:131$17_Y[15] Y[16]=$ternary$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:131$17_Y[16] Y[17]=$ternary$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:131$17_Y[17] Y[18]=$ternary$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:131$17_Y[18] Y[19]=$ternary$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:131$17_Y[19] Y[20]=$ternary$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:131$17_Y[20] Y[21]=$ternary$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:131$17_Y[21] Y[22]=$ternary$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:131$17_Y[22] Y[23]=$ternary$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:131$17_Y[23] Y[24]=$ternary$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:131$17_Y[24] Y[25]=$ternary$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:131$17_Y[25] Y[26]=$ternary$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:131$17_Y[26] Y[27]=$ternary$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:131$17_Y[27] Y[28]=$ternary$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:131$17_Y[28] Y[29]=$ternary$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:131$17_Y[29] Y[30]=$ternary$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:131$17_Y[30] Y[31]=$ternary$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:131$17_Y[31]
|
||
|
|
.cname $ternary$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:131$17
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:131"
|
||
|
|
.param WIDTH 00000000000000000000000000100000
|
||
|
|
.subckt $mux A[0]=$ternary$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:131$17_Y[0] A[1]=$ternary$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:131$17_Y[1] A[2]=$ternary$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:131$17_Y[2] A[3]=$ternary$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:131$17_Y[3] A[4]=$ternary$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:131$17_Y[4] A[5]=$ternary$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:131$17_Y[5] A[6]=$ternary$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:131$17_Y[6] A[7]=$ternary$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:131$17_Y[7] A[8]=$ternary$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:131$17_Y[8] A[9]=$ternary$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:131$17_Y[9] A[10]=$ternary$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:131$17_Y[10] A[11]=$ternary$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:131$17_Y[11] A[12]=$ternary$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:131$17_Y[12] A[13]=$ternary$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:131$17_Y[13] A[14]=$ternary$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:131$17_Y[14] A[15]=$ternary$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:131$17_Y[15] A[16]=$ternary$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:131$17_Y[16] A[17]=$ternary$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:131$17_Y[17] A[18]=$ternary$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:131$17_Y[18] A[19]=$ternary$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:131$17_Y[19] A[20]=$ternary$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:131$17_Y[20] A[21]=$ternary$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:131$17_Y[21] A[22]=$ternary$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:131$17_Y[22] A[23]=$ternary$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:131$17_Y[23] A[24]=$ternary$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:131$17_Y[24] A[25]=$ternary$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:131$17_Y[25] A[26]=$ternary$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:131$17_Y[26] A[27]=$ternary$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:131$17_Y[27] A[28]=$ternary$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:131$17_Y[28] A[29]=$ternary$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:131$17_Y[29] A[30]=$ternary$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:131$17_Y[30] A[31]=$ternary$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:131$17_Y[31] B[0]=SHA1_f2_BCD[0] B[1]=SHA1_f2_BCD[1] B[2]=SHA1_f2_BCD[2] B[3]=SHA1_f2_BCD[3] B[4]=SHA1_f2_BCD[4] B[5]=SHA1_f2_BCD[5] B[6]=SHA1_f2_BCD[6] B[7]=SHA1_f2_BCD[7] B[8]=SHA1_f2_BCD[8] B[9]=SHA1_f2_BCD[9] B[10]=SHA1_f2_BCD[10] B[11]=SHA1_f2_BCD[11] B[12]=SHA1_f2_BCD[12] B[13]=SHA1_f2_BCD[13] B[14]=SHA1_f2_BCD[14] B[15]=SHA1_f2_BCD[15] B[16]=SHA1_f2_BCD[16] B[17]=SHA1_f2_BCD[17] B[18]=SHA1_f2_BCD[18] B[19]=SHA1_f2_BCD[19] B[20]=SHA1_f2_BCD[20] B[21]=SHA1_f2_BCD[21] B[22]=SHA1_f2_BCD[22] B[23]=SHA1_f2_BCD[23] B[24]=SHA1_f2_BCD[24] B[25]=SHA1_f2_BCD[25] B[26]=SHA1_f2_BCD[26] B[27]=SHA1_f2_BCD[27] B[28]=SHA1_f2_BCD[28] B[29]=SHA1_f2_BCD[29] B[30]=SHA1_f2_BCD[30] B[31]=SHA1_f2_BCD[31] S=$lt$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:131$15_Y Y[0]=$ternary$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:131$18_Y[0] Y[1]=$ternary$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:131$18_Y[1] Y[2]=$ternary$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:131$18_Y[2] Y[3]=$ternary$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:131$18_Y[3] Y[4]=$ternary$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:131$18_Y[4] Y[5]=$ternary$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:131$18_Y[5] Y[6]=$ternary$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:131$18_Y[6] Y[7]=$ternary$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:131$18_Y[7] Y[8]=$ternary$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:131$18_Y[8] Y[9]=$ternary$/project/trees/vtr/vtr_flow/bench
|
||
|
|
.cname $ternary$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:131$18
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:131"
|
||
|
|
.param WIDTH 00000000000000000000000000100000
|
||
|
|
.subckt $mux A[0]=$ternary$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:131$18_Y[0] A[1]=$ternary$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:131$18_Y[1] A[2]=$ternary$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:131$18_Y[2] A[3]=$ternary$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:131$18_Y[3] A[4]=$ternary$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:131$18_Y[4] A[5]=$ternary$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:131$18_Y[5] A[6]=$ternary$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:131$18_Y[6] A[7]=$ternary$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:131$18_Y[7] A[8]=$ternary$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:131$18_Y[8] A[9]=$ternary$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:131$18_Y[9] A[10]=$ternary$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:131$18_Y[10] A[11]=$ternary$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:131$18_Y[11] A[12]=$ternary$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:131$18_Y[12] A[13]=$ternary$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:131$18_Y[13] A[14]=$ternary$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:131$18_Y[14] A[15]=$ternary$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:131$18_Y[15] A[16]=$ternary$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:131$18_Y[16] A[17]=$ternary$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:131$18_Y[17] A[18]=$ternary$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:131$18_Y[18] A[19]=$ternary$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:131$18_Y[19] A[20]=$ternary$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:131$18_Y[20] A[21]=$ternary$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:131$18_Y[21] A[22]=$ternary$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:131$18_Y[22] A[23]=$ternary$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:131$18_Y[23] A[24]=$ternary$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:131$18_Y[24] A[25]=$ternary$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:131$18_Y[25] A[26]=$ternary$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:131$18_Y[26] A[27]=$ternary$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:131$18_Y[27] A[28]=$ternary$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:131$18_Y[28] A[29]=$ternary$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:131$18_Y[29] A[30]=$ternary$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:131$18_Y[30] A[31]=$ternary$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:131$18_Y[31] B[0]=SHA1_f1_BCD[0] B[1]=SHA1_f1_BCD[1] B[2]=SHA1_f1_BCD[2] B[3]=SHA1_f1_BCD[3] B[4]=SHA1_f1_BCD[4] B[5]=SHA1_f1_BCD[5] B[6]=SHA1_f1_BCD[6] B[7]=SHA1_f1_BCD[7] B[8]=SHA1_f1_BCD[8] B[9]=SHA1_f1_BCD[9] B[10]=SHA1_f1_BCD[10] B[11]=SHA1_f1_BCD[11] B[12]=SHA1_f1_BCD[12] B[13]=SHA1_f1_BCD[13] B[14]=SHA1_f1_BCD[14] B[15]=SHA1_f1_BCD[15] B[16]=SHA1_f1_BCD[16] B[17]=SHA1_f1_BCD[17] B[18]=SHA1_f1_BCD[18] B[19]=SHA1_f1_BCD[19] B[20]=SHA1_f1_BCD[20] B[21]=SHA1_f1_BCD[21] B[22]=SHA1_f1_BCD[22] B[23]=SHA1_f1_BCD[23] B[24]=SHA1_f1_BCD[24] B[25]=SHA1_f1_BCD[25] B[26]=SHA1_f1_BCD[26] B[27]=SHA1_f1_BCD[27] B[28]=SHA1_f1_BCD[28] B[29]=SHA1_f1_BCD[29] B[30]=SHA1_f1_BCD[30] B[31]=SHA1_f1_BCD[31] S=$lt$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:131$14_Y Y[0]=$ternary$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:131$19_Y[0] Y[1]=$ternary$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:131$19_Y[1] Y[2]=$ternary$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:131$19_Y[2] Y[3]=$ternary$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:131$19_Y[3] Y[4]=$ternary$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:131$19_Y[4] Y[5]=$ternary$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:131$19_Y[5] Y[6]=$ternary$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:131$19_Y[6] Y[7]=$ternary$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:131$19_Y[7] Y[8]=$ternary$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:131$19_Y[8] Y[9]=$ternary$/project/trees/vtr/vtr_flow/bench
|
||
|
|
.cname $ternary$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:131$19
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:131"
|
||
|
|
.param WIDTH 00000000000000000000000000100000
|
||
|
|
.subckt $xor A[0]=$and$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:127$3_Y[0] A[1]=$and$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:127$3_Y[1] A[2]=$and$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:127$3_Y[2] A[3]=$and$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:127$3_Y[3] A[4]=$and$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:127$3_Y[4] A[5]=$and$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:127$3_Y[5] A[6]=$and$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:127$3_Y[6] A[7]=$and$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:127$3_Y[7] A[8]=$and$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:127$3_Y[8] A[9]=$and$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:127$3_Y[9] A[10]=$and$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:127$3_Y[10] A[11]=$and$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:127$3_Y[11] A[12]=$and$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:127$3_Y[12] A[13]=$and$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:127$3_Y[13] A[14]=$and$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:127$3_Y[14] A[15]=$and$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:127$3_Y[15] A[16]=$and$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:127$3_Y[16] A[17]=$and$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:127$3_Y[17] A[18]=$and$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:127$3_Y[18] A[19]=$and$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:127$3_Y[19] A[20]=$and$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:127$3_Y[20] A[21]=$and$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:127$3_Y[21] A[22]=$and$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:127$3_Y[22] A[23]=$and$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:127$3_Y[23] A[24]=$and$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:127$3_Y[24] A[25]=$and$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:127$3_Y[25] A[26]=$and$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:127$3_Y[26] A[27]=$and$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:127$3_Y[27] A[28]=$and$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:127$3_Y[28] A[29]=$and$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:127$3_Y[29] A[30]=$and$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:127$3_Y[30] A[31]=$and$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:127$3_Y[31] B[0]=$and$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:127$5_Y[0] B[1]=$and$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:127$5_Y[1] B[2]=$and$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:127$5_Y[2] B[3]=$and$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:127$5_Y[3] B[4]=$and$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:127$5_Y[4] B[5]=$and$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:127$5_Y[5] B[6]=$and$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:127$5_Y[6] B[7]=$and$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:127$5_Y[7] B[8]=$and$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:127$5_Y[8] B[9]=$and$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:127$5_Y[9] B[10]=$and$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:127$5_Y[10] B[11]=$and$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:127$5_Y[11] B[12]=$and$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:127$5_Y[12] B[13]=$and$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:127$5_Y[13] B[14]=$and$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:127$5_Y[14] B[15]=$and$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:127$5_Y[15] B[16]=$and$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:127$5_Y[16] B[17]=$and$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:127$5_Y[17] B[18]=$and$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:127$5_Y[18] B[19]=$and$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:127$5_Y[19] B[20]=$and$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:127$5_Y[20] B[21]=$and$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:127$5_Y[21] B[22]=$and$/projec
|
||
|
|
.cname $xor$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:127$6
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:127"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000100000
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000100000
|
||
|
|
.param Y_WIDTH 00000000000000000000000000100000
|
||
|
|
.subckt $xor A[0]=B[0] A[1]=B[1] A[2]=B[2] A[3]=B[3] A[4]=B[4] A[5]=B[5] A[6]=B[6] A[7]=B[7] A[8]=B[8] A[9]=B[9] A[10]=B[10] A[11]=B[11] A[12]=B[12] A[13]=B[13] A[14]=B[14] A[15]=B[15] A[16]=B[16] A[17]=B[17] A[18]=B[18] A[19]=B[19] A[20]=B[20] A[21]=B[21] A[22]=B[22] A[23]=B[23] A[24]=B[24] A[25]=B[25] A[26]=B[26] A[27]=B[27] A[28]=B[28] A[29]=B[29] A[30]=B[30] A[31]=B[31] B[0]=C[0] B[1]=C[1] B[2]=C[2] B[3]=C[3] B[4]=C[4] B[5]=C[5] B[6]=C[6] B[7]=C[7] B[8]=C[8] B[9]=C[9] B[10]=C[10] B[11]=C[11] B[12]=C[12] B[13]=C[13] B[14]=C[14] B[15]=C[15] B[16]=C[16] B[17]=C[17] B[18]=C[18] B[19]=C[19] B[20]=C[20] B[21]=C[21] B[22]=C[22] B[23]=C[23] B[24]=C[24] B[25]=C[25] B[26]=C[26] B[27]=C[27] B[28]=C[28] B[29]=C[29] B[30]=C[30] B[31]=C[31] Y[0]=$xor$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:128$7_Y[0] Y[1]=$xor$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:128$7_Y[1] Y[2]=$xor$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:128$7_Y[2] Y[3]=$xor$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:128$7_Y[3] Y[4]=$xor$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:128$7_Y[4] Y[5]=$xor$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:128$7_Y[5] Y[6]=$xor$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:128$7_Y[6] Y[7]=$xor$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:128$7_Y[7] Y[8]=$xor$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:128$7_Y[8] Y[9]=$xor$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:128$7_Y[9] Y[10]=$xor$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:128$7_Y[10] Y[11]=$xor$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:128$7_Y[11] Y[12]=$xor$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:128$7_Y[12] Y[13]=$xor$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:128$7_Y[13] Y[14]=$xor$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:128$7_Y[14] Y[15]=$xor$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:128$7_Y[15] Y[16]=$xor$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:128$7_Y[16] Y[17]=$xor$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:128$7_Y[17] Y[18]=$xor$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:128$7_Y[18] Y[19]=$xor$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:128$7_Y[19] Y[20]=$xor$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:128$7_Y[20] Y[21]=$xor$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:128$7_Y[21] Y[22]=$xor$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:128$7_Y[22] Y[23]=$xor$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:128$7_Y[23] Y[24]=$xor$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:128$7_Y[24] Y[25]=$xor$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:128$7_Y[25] Y[26]=$xor$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:128$7_Y[26] Y[27]=$xor$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:128$7_Y[27] Y[28]=$xor$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:128$7_Y[28] Y[29]=$xor$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:128$7_Y[29] Y[30]=$xor$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:128$7_Y[30] Y[31]=$xor$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:128$7_Y[31]
|
||
|
|
.cname $xor$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:128$7
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:128"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000100000
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000100000
|
||
|
|
.param Y_WIDTH 00000000000000000000000000100000
|
||
|
|
.subckt $xor A[0]=$xor$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:128$7_Y[0] A[1]=$xor$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:128$7_Y[1] A[2]=$xor$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:128$7_Y[2] A[3]=$xor$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:128$7_Y[3] A[4]=$xor$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:128$7_Y[4] A[5]=$xor$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:128$7_Y[5] A[6]=$xor$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:128$7_Y[6] A[7]=$xor$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:128$7_Y[7] A[8]=$xor$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:128$7_Y[8] A[9]=$xor$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:128$7_Y[9] A[10]=$xor$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:128$7_Y[10] A[11]=$xor$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:128$7_Y[11] A[12]=$xor$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:128$7_Y[12] A[13]=$xor$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:128$7_Y[13] A[14]=$xor$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:128$7_Y[14] A[15]=$xor$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:128$7_Y[15] A[16]=$xor$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:128$7_Y[16] A[17]=$xor$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:128$7_Y[17] A[18]=$xor$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:128$7_Y[18] A[19]=$xor$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:128$7_Y[19] A[20]=$xor$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:128$7_Y[20] A[21]=$xor$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:128$7_Y[21] A[22]=$xor$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:128$7_Y[22] A[23]=$xor$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:128$7_Y[23] A[24]=$xor$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:128$7_Y[24] A[25]=$xor$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:128$7_Y[25] A[26]=$xor$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:128$7_Y[26] A[27]=$xor$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:128$7_Y[27] A[28]=$xor$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:128$7_Y[28] A[29]=$xor$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:128$7_Y[29] A[30]=$xor$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:128$7_Y[30] A[31]=$xor$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:128$7_Y[31] B[0]=D[0] B[1]=D[1] B[2]=D[2] B[3]=D[3] B[4]=D[4] B[5]=D[5] B[6]=D[6] B[7]=D[7] B[8]=D[8] B[9]=D[9] B[10]=D[10] B[11]=D[11] B[12]=D[12] B[13]=D[13] B[14]=D[14] B[15]=D[15] B[16]=D[16] B[17]=D[17] B[18]=D[18] B[19]=D[19] B[20]=D[20] B[21]=D[21] B[22]=D[22] B[23]=D[23] B[24]=D[24] B[25]=D[25] B[26]=D[26] B[27]=D[27] B[28]=D[28] B[29]=D[29] B[30]=D[30] B[31]=D[31] Y[0]=$xor$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:128$8_Y[0] Y[1]=$xor$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:128$8_Y[1] Y[2]=$xor$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:128$8_Y[2] Y[3]=$xor$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:128$8_Y[3] Y[4]=$xor$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:128$8_Y[4] Y[5]=$xor$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:128$8_Y[5] Y[6]=$xor$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:128$8_Y[6] Y[7]=$xor$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:128$8_Y[7] Y[8]=$xor$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:128$8_Y[8] Y[9]=$xor$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:128$8_Y[9] Y[10]=$xor$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:128$8_Y[10] Y[11]=$xor$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:128$8_Y[11] Y[12]=$xor$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:128$8_Y[12] Y[13]=$xor$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:128$8_Y[13] Y[14]=$xor$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:128$8_Y[14] Y[15]=$xor$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:128$8_Y[15] Y[16]=$xor$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:128$8_Y[16] Y[17]=$xor$/project/trees/vtr/vtr_
|
||
|
|
.cname $xor$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:128$8
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:128"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000100000
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000100000
|
||
|
|
.param Y_WIDTH 00000000000000000000000000100000
|
||
|
|
.subckt $xor A[0]=$and$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:129$9_Y[0] A[1]=$and$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:129$9_Y[1] A[2]=$and$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:129$9_Y[2] A[3]=$and$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:129$9_Y[3] A[4]=$and$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:129$9_Y[4] A[5]=$and$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:129$9_Y[5] A[6]=$and$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:129$9_Y[6] A[7]=$and$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:129$9_Y[7] A[8]=$and$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:129$9_Y[8] A[9]=$and$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:129$9_Y[9] A[10]=$and$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:129$9_Y[10] A[11]=$and$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:129$9_Y[11] A[12]=$and$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:129$9_Y[12] A[13]=$and$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:129$9_Y[13] A[14]=$and$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:129$9_Y[14] A[15]=$and$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:129$9_Y[15] A[16]=$and$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:129$9_Y[16] A[17]=$and$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:129$9_Y[17] A[18]=$and$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:129$9_Y[18] A[19]=$and$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:129$9_Y[19] A[20]=$and$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:129$9_Y[20] A[21]=$and$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:129$9_Y[21] A[22]=$and$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:129$9_Y[22] A[23]=$and$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:129$9_Y[23] A[24]=$and$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:129$9_Y[24] A[25]=$and$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:129$9_Y[25] A[26]=$and$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:129$9_Y[26] A[27]=$and$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:129$9_Y[27] A[28]=$and$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:129$9_Y[28] A[29]=$and$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:129$9_Y[29] A[30]=$and$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:129$9_Y[30] A[31]=$and$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:129$9_Y[31] B[0]=$and$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:129$10_Y[0] B[1]=$and$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:129$10_Y[1] B[2]=$and$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:129$10_Y[2] B[3]=$and$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:129$10_Y[3] B[4]=$and$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:129$10_Y[4] B[5]=$and$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:129$10_Y[5] B[6]=$and$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:129$10_Y[6] B[7]=$and$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:129$10_Y[7] B[8]=$and$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:129$10_Y[8] B[9]=$and$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:129$10_Y[9] B[10]=$and$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:129$10_Y[10] B[11]=$and$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:129$10_Y[11] B[12]=$and$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:129$10_Y[12] B[13]=$and$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:129$10_Y[13] B[14]=$and$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:129$10_Y[14] B[15]=$and$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:129$10_Y[15] B[16]=$and$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:129$10_Y[16] B[17]=$and$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:129$10_Y[17] B[18]=$and$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:129$10_Y[18] B[19]=$and$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:129$10_Y[19] B[20]=$and$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:129$10_Y[20] B[21]=$and$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:129$10_Y[
|
||
|
|
.cname $xor$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:129$11
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:129"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000100000
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000100000
|
||
|
|
.param Y_WIDTH 00000000000000000000000000100000
|
||
|
|
.subckt $xor A[0]=$xor$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:129$11_Y[0] A[1]=$xor$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:129$11_Y[1] A[2]=$xor$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:129$11_Y[2] A[3]=$xor$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:129$11_Y[3] A[4]=$xor$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:129$11_Y[4] A[5]=$xor$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:129$11_Y[5] A[6]=$xor$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:129$11_Y[6] A[7]=$xor$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:129$11_Y[7] A[8]=$xor$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:129$11_Y[8] A[9]=$xor$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:129$11_Y[9] A[10]=$xor$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:129$11_Y[10] A[11]=$xor$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:129$11_Y[11] A[12]=$xor$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:129$11_Y[12] A[13]=$xor$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:129$11_Y[13] A[14]=$xor$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:129$11_Y[14] A[15]=$xor$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:129$11_Y[15] A[16]=$xor$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:129$11_Y[16] A[17]=$xor$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:129$11_Y[17] A[18]=$xor$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:129$11_Y[18] A[19]=$xor$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:129$11_Y[19] A[20]=$xor$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:129$11_Y[20] A[21]=$xor$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:129$11_Y[21] A[22]=$xor$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:129$11_Y[22] A[23]=$xor$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:129$11_Y[23] A[24]=$xor$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:129$11_Y[24] A[25]=$xor$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:129$11_Y[25] A[26]=$xor$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:129$11_Y[26] A[27]=$xor$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:129$11_Y[27] A[28]=$xor$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:129$11_Y[28] A[29]=$xor$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:129$11_Y[29] A[30]=$xor$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:129$11_Y[30] A[31]=$xor$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:129$11_Y[31] B[0]=$and$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:129$12_Y[0] B[1]=$and$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:129$12_Y[1] B[2]=$and$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:129$12_Y[2] B[3]=$and$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:129$12_Y[3] B[4]=$and$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:129$12_Y[4] B[5]=$and$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:129$12_Y[5] B[6]=$and$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:129$12_Y[6] B[7]=$and$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:129$12_Y[7] B[8]=$and$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:129$12_Y[8] B[9]=$and$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:129$12_Y[9] B[10]=$and$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:129$12_Y[10] B[11]=$and$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:129$12_Y[11] B[12]=$and$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:129$12_Y[12] B[13]=$and$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:129$12_Y[13] B[14]=$and$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:129$12_Y[14] B[15]=$and$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:129$12_Y[15] B[16]=$and$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:129$12_Y[16] B[17]=$and$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:129$12_Y[17] B[18]=$and$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:129$12_Y[18] B[19]=$and$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:129$12_Y[19] B[20]=$and$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:129$12_Y[20] B[21]=$and$/project/trees/vtr/vtr_flow/be
|
||
|
|
.cname $xor$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:129$13
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:129"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000100000
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000100000
|
||
|
|
.param Y_WIDTH 00000000000000000000000000100000
|
||
|
|
.subckt $xor A[0]=W13[0] A[1]=W13[1] A[2]=W13[2] A[3]=W13[3] A[4]=W13[4] A[5]=W13[5] A[6]=W13[6] A[7]=W13[7] A[8]=W13[8] A[9]=W13[9] A[10]=W13[10] A[11]=W13[11] A[12]=W13[12] A[13]=W13[13] A[14]=W13[14] A[15]=W13[15] A[16]=W13[16] A[17]=W13[17] A[18]=W13[18] A[19]=W13[19] A[20]=W13[20] A[21]=W13[21] A[22]=W13[22] A[23]=W13[23] A[24]=W13[24] A[25]=W13[25] A[26]=W13[26] A[27]=W13[27] A[28]=W13[28] A[29]=W13[29] A[30]=W13[30] A[31]=W13[31] B[0]=W8[0] B[1]=W8[1] B[2]=W8[2] B[3]=W8[3] B[4]=W8[4] B[5]=W8[5] B[6]=W8[6] B[7]=W8[7] B[8]=W8[8] B[9]=W8[9] B[10]=W8[10] B[11]=W8[11] B[12]=W8[12] B[13]=W8[13] B[14]=W8[14] B[15]=W8[15] B[16]=W8[16] B[17]=W8[17] B[18]=W8[18] B[19]=W8[19] B[20]=W8[20] B[21]=W8[21] B[22]=W8[22] B[23]=W8[23] B[24]=W8[24] B[25]=W8[25] B[26]=W8[26] B[27]=W8[27] B[28]=W8[28] B[29]=W8[29] B[30]=W8[30] B[31]=W8[31] Y[0]=$xor$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:135$20_Y[0] Y[1]=$xor$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:135$20_Y[1] Y[2]=$xor$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:135$20_Y[2] Y[3]=$xor$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:135$20_Y[3] Y[4]=$xor$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:135$20_Y[4] Y[5]=$xor$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:135$20_Y[5] Y[6]=$xor$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:135$20_Y[6] Y[7]=$xor$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:135$20_Y[7] Y[8]=$xor$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:135$20_Y[8] Y[9]=$xor$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:135$20_Y[9] Y[10]=$xor$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:135$20_Y[10] Y[11]=$xor$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:135$20_Y[11] Y[12]=$xor$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:135$20_Y[12] Y[13]=$xor$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:135$20_Y[13] Y[14]=$xor$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:135$20_Y[14] Y[15]=$xor$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:135$20_Y[15] Y[16]=$xor$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:135$20_Y[16] Y[17]=$xor$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:135$20_Y[17] Y[18]=$xor$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:135$20_Y[18] Y[19]=$xor$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:135$20_Y[19] Y[20]=$xor$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:135$20_Y[20] Y[21]=$xor$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:135$20_Y[21] Y[22]=$xor$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:135$20_Y[22] Y[23]=$xor$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:135$20_Y[23] Y[24]=$xor$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:135$20_Y[24] Y[25]=$xor$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:135$20_Y[25] Y[26]=$xor$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:135$20_Y[26] Y[27]=$xor$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:135$20_Y[27] Y[28]=$xor$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:135$20_Y[28] Y[29]=$xor$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:135$20_Y[29] Y[30]=$xor$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:135$20_Y[30] Y[31]=$xor$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:135$20_Y[31]
|
||
|
|
.cname $xor$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:135$20
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:135"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000100000
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000100000
|
||
|
|
.param Y_WIDTH 00000000000000000000000000100000
|
||
|
|
.subckt $xor A[0]=$xor$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:135$20_Y[0] A[1]=$xor$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:135$20_Y[1] A[2]=$xor$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:135$20_Y[2] A[3]=$xor$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:135$20_Y[3] A[4]=$xor$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:135$20_Y[4] A[5]=$xor$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:135$20_Y[5] A[6]=$xor$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:135$20_Y[6] A[7]=$xor$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:135$20_Y[7] A[8]=$xor$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:135$20_Y[8] A[9]=$xor$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:135$20_Y[9] A[10]=$xor$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:135$20_Y[10] A[11]=$xor$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:135$20_Y[11] A[12]=$xor$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:135$20_Y[12] A[13]=$xor$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:135$20_Y[13] A[14]=$xor$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:135$20_Y[14] A[15]=$xor$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:135$20_Y[15] A[16]=$xor$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:135$20_Y[16] A[17]=$xor$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:135$20_Y[17] A[18]=$xor$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:135$20_Y[18] A[19]=$xor$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:135$20_Y[19] A[20]=$xor$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:135$20_Y[20] A[21]=$xor$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:135$20_Y[21] A[22]=$xor$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:135$20_Y[22] A[23]=$xor$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:135$20_Y[23] A[24]=$xor$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:135$20_Y[24] A[25]=$xor$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:135$20_Y[25] A[26]=$xor$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:135$20_Y[26] A[27]=$xor$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:135$20_Y[27] A[28]=$xor$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:135$20_Y[28] A[29]=$xor$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:135$20_Y[29] A[30]=$xor$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:135$20_Y[30] A[31]=$xor$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:135$20_Y[31] B[0]=W2[0] B[1]=W2[1] B[2]=W2[2] B[3]=W2[3] B[4]=W2[4] B[5]=W2[5] B[6]=W2[6] B[7]=W2[7] B[8]=W2[8] B[9]=W2[9] B[10]=W2[10] B[11]=W2[11] B[12]=W2[12] B[13]=W2[13] B[14]=W2[14] B[15]=W2[15] B[16]=W2[16] B[17]=W2[17] B[18]=W2[18] B[19]=W2[19] B[20]=W2[20] B[21]=W2[21] B[22]=W2[22] B[23]=W2[23] B[24]=W2[24] B[25]=W2[25] B[26]=W2[26] B[27]=W2[27] B[28]=W2[28] B[29]=W2[29] B[30]=W2[30] B[31]=W2[31] Y[0]=$xor$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:135$21_Y[0] Y[1]=$xor$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:135$21_Y[1] Y[2]=$xor$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:135$21_Y[2] Y[3]=$xor$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:135$21_Y[3] Y[4]=$xor$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:135$21_Y[4] Y[5]=$xor$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:135$21_Y[5] Y[6]=$xor$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:135$21_Y[6] Y[7]=$xor$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:135$21_Y[7] Y[8]=$xor$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:135$21_Y[8] Y[9]=$xor$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:135$21_Y[9] Y[10]=$xor$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:135$21_Y[10] Y[11]=$xor$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:135$21_Y[11] Y[12]=$xor$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:135$21_Y[12] Y[13]=$xor$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:135$21_Y[13] Y[14]=$xor$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:135$21_Y[14] Y[15]=$xor$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:135$21_Y[15] Y[16]=$xor$/project/trees/vtr/
|
||
|
|
.cname $xor$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:135$21
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:135"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000100000
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000100000
|
||
|
|
.param Y_WIDTH 00000000000000000000000000100000
|
||
|
|
.subckt $xor A[0]=$xor$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:135$21_Y[0] A[1]=$xor$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:135$21_Y[1] A[2]=$xor$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:135$21_Y[2] A[3]=$xor$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:135$21_Y[3] A[4]=$xor$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:135$21_Y[4] A[5]=$xor$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:135$21_Y[5] A[6]=$xor$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:135$21_Y[6] A[7]=$xor$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:135$21_Y[7] A[8]=$xor$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:135$21_Y[8] A[9]=$xor$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:135$21_Y[9] A[10]=$xor$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:135$21_Y[10] A[11]=$xor$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:135$21_Y[11] A[12]=$xor$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:135$21_Y[12] A[13]=$xor$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:135$21_Y[13] A[14]=$xor$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:135$21_Y[14] A[15]=$xor$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:135$21_Y[15] A[16]=$xor$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:135$21_Y[16] A[17]=$xor$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:135$21_Y[17] A[18]=$xor$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:135$21_Y[18] A[19]=$xor$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:135$21_Y[19] A[20]=$xor$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:135$21_Y[20] A[21]=$xor$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:135$21_Y[21] A[22]=$xor$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:135$21_Y[22] A[23]=$xor$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:135$21_Y[23] A[24]=$xor$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:135$21_Y[24] A[25]=$xor$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:135$21_Y[25] A[26]=$xor$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:135$21_Y[26] A[27]=$xor$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:135$21_Y[27] A[28]=$xor$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:135$21_Y[28] A[29]=$xor$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:135$21_Y[29] A[30]=$xor$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:135$21_Y[30] A[31]=$xor$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:135$21_Y[31] B[0]=W0[0] B[1]=W0[1] B[2]=W0[2] B[3]=W0[3] B[4]=W0[4] B[5]=W0[5] B[6]=W0[6] B[7]=W0[7] B[8]=W0[8] B[9]=W0[9] B[10]=W0[10] B[11]=W0[11] B[12]=W0[12] B[13]=W0[13] B[14]=W0[14] B[15]=W0[15] B[16]=W0[16] B[17]=W0[17] B[18]=W0[18] B[19]=W0[19] B[20]=W0[20] B[21]=W0[21] B[22]=W0[22] B[23]=W0[23] B[24]=W0[24] B[25]=W0[25] B[26]=W0[26] B[27]=W0[27] B[28]=W0[28] B[29]=W0[29] B[30]=W0[30] B[31]=W0[31] Y[0]=$xor$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:135$22_Y[0] Y[1]=$xor$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:135$22_Y[1] Y[2]=$xor$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:135$22_Y[2] Y[3]=$xor$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:135$22_Y[3] Y[4]=$xor$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:135$22_Y[4] Y[5]=$xor$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:135$22_Y[5] Y[6]=$xor$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:135$22_Y[6] Y[7]=$xor$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:135$22_Y[7] Y[8]=$xor$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:135$22_Y[8] Y[9]=$xor$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:135$22_Y[9] Y[10]=$xor$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:135$22_Y[10] Y[11]=$xor$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:135$22_Y[11] Y[12]=$xor$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:135$22_Y[12] Y[13]=$xor$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:135$22_Y[13] Y[14]=$xor$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:135$22_Y[14] Y[15]=$xor$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:135$22_Y[15] Y[16]=$xor$/project/trees/vtr/
|
||
|
|
.cname $xor$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:135$22
|
||
|
|
.attr src "/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:135"
|
||
|
|
.param A_SIGNED 00000000000000000000000000000000
|
||
|
|
.param A_WIDTH 00000000000000000000000000100000
|
||
|
|
.param B_SIGNED 00000000000000000000000000000000
|
||
|
|
.param B_WIDTH 00000000000000000000000000100000
|
||
|
|
.param Y_WIDTH 00000000000000000000000000100000
|
||
|
|
.conn cmd[0] cmd_o[0]
|
||
|
|
.conn cmd[1] cmd_o[1]
|
||
|
|
.conn cmd[2] cmd_o[2]
|
||
|
|
.conn cmd[3] cmd_o[3]
|
||
|
|
.conn $xor$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:127$6_Y[0] SHA1_f1_BCD[0]
|
||
|
|
.conn $xor$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:127$6_Y[1] SHA1_f1_BCD[1]
|
||
|
|
.conn $xor$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:127$6_Y[2] SHA1_f1_BCD[2]
|
||
|
|
.conn $xor$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:127$6_Y[3] SHA1_f1_BCD[3]
|
||
|
|
.conn $xor$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:127$6_Y[4] SHA1_f1_BCD[4]
|
||
|
|
.conn $xor$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:127$6_Y[5] SHA1_f1_BCD[5]
|
||
|
|
.conn $xor$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:127$6_Y[6] SHA1_f1_BCD[6]
|
||
|
|
.conn $xor$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:127$6_Y[7] SHA1_f1_BCD[7]
|
||
|
|
.conn $xor$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:127$6_Y[8] SHA1_f1_BCD[8]
|
||
|
|
.conn $xor$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:127$6_Y[9] SHA1_f1_BCD[9]
|
||
|
|
.conn $xor$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:127$6_Y[10] SHA1_f1_BCD[10]
|
||
|
|
.conn $xor$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:127$6_Y[11] SHA1_f1_BCD[11]
|
||
|
|
.conn $xor$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:127$6_Y[12] SHA1_f1_BCD[12]
|
||
|
|
.conn $xor$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:127$6_Y[13] SHA1_f1_BCD[13]
|
||
|
|
.conn $xor$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:127$6_Y[14] SHA1_f1_BCD[14]
|
||
|
|
.conn $xor$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:127$6_Y[15] SHA1_f1_BCD[15]
|
||
|
|
.conn $xor$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:127$6_Y[16] SHA1_f1_BCD[16]
|
||
|
|
.conn $xor$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:127$6_Y[17] SHA1_f1_BCD[17]
|
||
|
|
.conn $xor$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:127$6_Y[18] SHA1_f1_BCD[18]
|
||
|
|
.conn $xor$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:127$6_Y[19] SHA1_f1_BCD[19]
|
||
|
|
.conn $xor$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:127$6_Y[20] SHA1_f1_BCD[20]
|
||
|
|
.conn $xor$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:127$6_Y[21] SHA1_f1_BCD[21]
|
||
|
|
.conn $xor$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:127$6_Y[22] SHA1_f1_BCD[22]
|
||
|
|
.conn $xor$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:127$6_Y[23] SHA1_f1_BCD[23]
|
||
|
|
.conn $xor$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:127$6_Y[24] SHA1_f1_BCD[24]
|
||
|
|
.conn $xor$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:127$6_Y[25] SHA1_f1_BCD[25]
|
||
|
|
.conn $xor$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:127$6_Y[26] SHA1_f1_BCD[26]
|
||
|
|
.conn $xor$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:127$6_Y[27] SHA1_f1_BCD[27]
|
||
|
|
.conn $xor$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:127$6_Y[28] SHA1_f1_BCD[28]
|
||
|
|
.conn $xor$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:127$6_Y[29] SHA1_f1_BCD[29]
|
||
|
|
.conn $xor$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:127$6_Y[30] SHA1_f1_BCD[30]
|
||
|
|
.conn $xor$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:127$6_Y[31] SHA1_f1_BCD[31]
|
||
|
|
.conn $xor$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:128$8_Y[0] SHA1_f2_BCD[0]
|
||
|
|
.conn $xor$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:128$8_Y[1] SHA1_f2_BCD[1]
|
||
|
|
.conn $xor$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:128$8_Y[2] SHA1_f2_BCD[2]
|
||
|
|
.conn $xor$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:128$8_Y[3] SHA1_f2_BCD[3]
|
||
|
|
.conn $xor$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:128$8_Y[4] SHA1_f2_BCD[4]
|
||
|
|
.conn $xor$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:128$8_Y[5] SHA1_f2_BCD[5]
|
||
|
|
.conn $xor$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:128$8_Y[6] SHA1_f2_BCD[6]
|
||
|
|
.conn $xor$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:128$8_Y[7] SHA1_f2_BCD[7]
|
||
|
|
.conn $xor$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:128$8_Y[8] SHA1_f2_BCD[8]
|
||
|
|
.conn $xor$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:128$8_Y[9] SHA1_f2_BCD[9]
|
||
|
|
.conn $xor$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:128$8_Y[10] SHA1_f2_BCD[10]
|
||
|
|
.conn $xor$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:128$8_Y[11] SHA1_f2_BCD[11]
|
||
|
|
.conn $xor$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:128$8_Y[12] SHA1_f2_BCD[12]
|
||
|
|
.conn $xor$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:128$8_Y[13] SHA1_f2_BCD[13]
|
||
|
|
.conn $xor$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:128$8_Y[14] SHA1_f2_BCD[14]
|
||
|
|
.conn $xor$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:128$8_Y[15] SHA1_f2_BCD[15]
|
||
|
|
.conn $xor$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:128$8_Y[16] SHA1_f2_BCD[16]
|
||
|
|
.conn $xor$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:128$8_Y[17] SHA1_f2_BCD[17]
|
||
|
|
.conn $xor$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:128$8_Y[18] SHA1_f2_BCD[18]
|
||
|
|
.conn $xor$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:128$8_Y[19] SHA1_f2_BCD[19]
|
||
|
|
.conn $xor$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:128$8_Y[20] SHA1_f2_BCD[20]
|
||
|
|
.conn $xor$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:128$8_Y[21] SHA1_f2_BCD[21]
|
||
|
|
.conn $xor$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:128$8_Y[22] SHA1_f2_BCD[22]
|
||
|
|
.conn $xor$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:128$8_Y[23] SHA1_f2_BCD[23]
|
||
|
|
.conn $xor$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:128$8_Y[24] SHA1_f2_BCD[24]
|
||
|
|
.conn $xor$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:128$8_Y[25] SHA1_f2_BCD[25]
|
||
|
|
.conn $xor$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:128$8_Y[26] SHA1_f2_BCD[26]
|
||
|
|
.conn $xor$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:128$8_Y[27] SHA1_f2_BCD[27]
|
||
|
|
.conn $xor$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:128$8_Y[28] SHA1_f2_BCD[28]
|
||
|
|
.conn $xor$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:128$8_Y[29] SHA1_f2_BCD[29]
|
||
|
|
.conn $xor$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:128$8_Y[30] SHA1_f2_BCD[30]
|
||
|
|
.conn $xor$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:128$8_Y[31] SHA1_f2_BCD[31]
|
||
|
|
.conn $xor$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:129$13_Y[0] SHA1_f3_BCD[0]
|
||
|
|
.conn $xor$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:129$13_Y[1] SHA1_f3_BCD[1]
|
||
|
|
.conn $xor$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:129$13_Y[2] SHA1_f3_BCD[2]
|
||
|
|
.conn $xor$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:129$13_Y[3] SHA1_f3_BCD[3]
|
||
|
|
.conn $xor$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:129$13_Y[4] SHA1_f3_BCD[4]
|
||
|
|
.conn $xor$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:129$13_Y[5] SHA1_f3_BCD[5]
|
||
|
|
.conn $xor$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:129$13_Y[6] SHA1_f3_BCD[6]
|
||
|
|
.conn $xor$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:129$13_Y[7] SHA1_f3_BCD[7]
|
||
|
|
.conn $xor$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:129$13_Y[8] SHA1_f3_BCD[8]
|
||
|
|
.conn $xor$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:129$13_Y[9] SHA1_f3_BCD[9]
|
||
|
|
.conn $xor$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:129$13_Y[10] SHA1_f3_BCD[10]
|
||
|
|
.conn $xor$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:129$13_Y[11] SHA1_f3_BCD[11]
|
||
|
|
.conn $xor$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:129$13_Y[12] SHA1_f3_BCD[12]
|
||
|
|
.conn $xor$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:129$13_Y[13] SHA1_f3_BCD[13]
|
||
|
|
.conn $xor$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:129$13_Y[14] SHA1_f3_BCD[14]
|
||
|
|
.conn $xor$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:129$13_Y[15] SHA1_f3_BCD[15]
|
||
|
|
.conn $xor$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:129$13_Y[16] SHA1_f3_BCD[16]
|
||
|
|
.conn $xor$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:129$13_Y[17] SHA1_f3_BCD[17]
|
||
|
|
.conn $xor$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:129$13_Y[18] SHA1_f3_BCD[18]
|
||
|
|
.conn $xor$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:129$13_Y[19] SHA1_f3_BCD[19]
|
||
|
|
.conn $xor$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:129$13_Y[20] SHA1_f3_BCD[20]
|
||
|
|
.conn $xor$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:129$13_Y[21] SHA1_f3_BCD[21]
|
||
|
|
.conn $xor$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:129$13_Y[22] SHA1_f3_BCD[22]
|
||
|
|
.conn $xor$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:129$13_Y[23] SHA1_f3_BCD[23]
|
||
|
|
.conn $xor$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:129$13_Y[24] SHA1_f3_BCD[24]
|
||
|
|
.conn $xor$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:129$13_Y[25] SHA1_f3_BCD[25]
|
||
|
|
.conn $xor$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:129$13_Y[26] SHA1_f3_BCD[26]
|
||
|
|
.conn $xor$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:129$13_Y[27] SHA1_f3_BCD[27]
|
||
|
|
.conn $xor$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:129$13_Y[28] SHA1_f3_BCD[28]
|
||
|
|
.conn $xor$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:129$13_Y[29] SHA1_f3_BCD[29]
|
||
|
|
.conn $xor$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:129$13_Y[30] SHA1_f3_BCD[30]
|
||
|
|
.conn $xor$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:129$13_Y[31] SHA1_f3_BCD[31]
|
||
|
|
.conn $ternary$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:131$19_Y[0] SHA1_ft_BCD[0]
|
||
|
|
.conn $ternary$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:131$19_Y[1] SHA1_ft_BCD[1]
|
||
|
|
.conn $ternary$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:131$19_Y[2] SHA1_ft_BCD[2]
|
||
|
|
.conn $ternary$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:131$19_Y[3] SHA1_ft_BCD[3]
|
||
|
|
.conn $ternary$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:131$19_Y[4] SHA1_ft_BCD[4]
|
||
|
|
.conn $ternary$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:131$19_Y[5] SHA1_ft_BCD[5]
|
||
|
|
.conn $ternary$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:131$19_Y[6] SHA1_ft_BCD[6]
|
||
|
|
.conn $ternary$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:131$19_Y[7] SHA1_ft_BCD[7]
|
||
|
|
.conn $ternary$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:131$19_Y[8] SHA1_ft_BCD[8]
|
||
|
|
.conn $ternary$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:131$19_Y[9] SHA1_ft_BCD[9]
|
||
|
|
.conn $ternary$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:131$19_Y[10] SHA1_ft_BCD[10]
|
||
|
|
.conn $ternary$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:131$19_Y[11] SHA1_ft_BCD[11]
|
||
|
|
.conn $ternary$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:131$19_Y[12] SHA1_ft_BCD[12]
|
||
|
|
.conn $ternary$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:131$19_Y[13] SHA1_ft_BCD[13]
|
||
|
|
.conn $ternary$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:131$19_Y[14] SHA1_ft_BCD[14]
|
||
|
|
.conn $ternary$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:131$19_Y[15] SHA1_ft_BCD[15]
|
||
|
|
.conn $ternary$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:131$19_Y[16] SHA1_ft_BCD[16]
|
||
|
|
.conn $ternary$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:131$19_Y[17] SHA1_ft_BCD[17]
|
||
|
|
.conn $ternary$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:131$19_Y[18] SHA1_ft_BCD[18]
|
||
|
|
.conn $ternary$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:131$19_Y[19] SHA1_ft_BCD[19]
|
||
|
|
.conn $ternary$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:131$19_Y[20] SHA1_ft_BCD[20]
|
||
|
|
.conn $ternary$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:131$19_Y[21] SHA1_ft_BCD[21]
|
||
|
|
.conn $ternary$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:131$19_Y[22] SHA1_ft_BCD[22]
|
||
|
|
.conn $ternary$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:131$19_Y[23] SHA1_ft_BCD[23]
|
||
|
|
.conn $ternary$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:131$19_Y[24] SHA1_ft_BCD[24]
|
||
|
|
.conn $ternary$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:131$19_Y[25] SHA1_ft_BCD[25]
|
||
|
|
.conn $ternary$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:131$19_Y[26] SHA1_ft_BCD[26]
|
||
|
|
.conn $ternary$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:131$19_Y[27] SHA1_ft_BCD[27]
|
||
|
|
.conn $ternary$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:131$19_Y[28] SHA1_ft_BCD[28]
|
||
|
|
.conn $ternary$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:131$19_Y[29] SHA1_ft_BCD[29]
|
||
|
|
.conn $ternary$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:131$19_Y[30] SHA1_ft_BCD[30]
|
||
|
|
.conn $ternary$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:131$19_Y[31] SHA1_ft_BCD[31]
|
||
|
|
.conn $xor$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:135$22_Y[0] SHA1_Wt_1[0]
|
||
|
|
.conn $xor$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:135$22_Y[1] SHA1_Wt_1[1]
|
||
|
|
.conn $xor$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:135$22_Y[2] SHA1_Wt_1[2]
|
||
|
|
.conn $xor$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:135$22_Y[3] SHA1_Wt_1[3]
|
||
|
|
.conn $xor$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:135$22_Y[4] SHA1_Wt_1[4]
|
||
|
|
.conn $xor$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:135$22_Y[5] SHA1_Wt_1[5]
|
||
|
|
.conn $xor$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:135$22_Y[6] SHA1_Wt_1[6]
|
||
|
|
.conn $xor$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:135$22_Y[7] SHA1_Wt_1[7]
|
||
|
|
.conn $xor$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:135$22_Y[8] SHA1_Wt_1[8]
|
||
|
|
.conn $xor$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:135$22_Y[9] SHA1_Wt_1[9]
|
||
|
|
.conn $xor$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:135$22_Y[10] SHA1_Wt_1[10]
|
||
|
|
.conn $xor$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:135$22_Y[11] SHA1_Wt_1[11]
|
||
|
|
.conn $xor$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:135$22_Y[12] SHA1_Wt_1[12]
|
||
|
|
.conn $xor$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:135$22_Y[13] SHA1_Wt_1[13]
|
||
|
|
.conn $xor$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:135$22_Y[14] SHA1_Wt_1[14]
|
||
|
|
.conn $xor$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:135$22_Y[15] SHA1_Wt_1[15]
|
||
|
|
.conn $xor$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:135$22_Y[16] SHA1_Wt_1[16]
|
||
|
|
.conn $xor$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:135$22_Y[17] SHA1_Wt_1[17]
|
||
|
|
.conn $xor$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:135$22_Y[18] SHA1_Wt_1[18]
|
||
|
|
.conn $xor$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:135$22_Y[19] SHA1_Wt_1[19]
|
||
|
|
.conn $xor$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:135$22_Y[20] SHA1_Wt_1[20]
|
||
|
|
.conn $xor$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:135$22_Y[21] SHA1_Wt_1[21]
|
||
|
|
.conn $xor$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:135$22_Y[22] SHA1_Wt_1[22]
|
||
|
|
.conn $xor$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:135$22_Y[23] SHA1_Wt_1[23]
|
||
|
|
.conn $xor$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:135$22_Y[24] SHA1_Wt_1[24]
|
||
|
|
.conn $xor$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:135$22_Y[25] SHA1_Wt_1[25]
|
||
|
|
.conn $xor$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:135$22_Y[26] SHA1_Wt_1[26]
|
||
|
|
.conn $xor$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:135$22_Y[27] SHA1_Wt_1[27]
|
||
|
|
.conn $xor$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:135$22_Y[28] SHA1_Wt_1[28]
|
||
|
|
.conn $xor$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:135$22_Y[29] SHA1_Wt_1[29]
|
||
|
|
.conn $xor$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:135$22_Y[30] SHA1_Wt_1[30]
|
||
|
|
.conn $xor$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:135$22_Y[31] SHA1_Wt_1[31]
|
||
|
|
.conn SHA1_Wt_1[31] next_Wt[0]
|
||
|
|
.conn SHA1_Wt_1[0] next_Wt[1]
|
||
|
|
.conn SHA1_Wt_1[1] next_Wt[2]
|
||
|
|
.conn SHA1_Wt_1[2] next_Wt[3]
|
||
|
|
.conn SHA1_Wt_1[3] next_Wt[4]
|
||
|
|
.conn SHA1_Wt_1[4] next_Wt[5]
|
||
|
|
.conn SHA1_Wt_1[5] next_Wt[6]
|
||
|
|
.conn SHA1_Wt_1[6] next_Wt[7]
|
||
|
|
.conn SHA1_Wt_1[7] next_Wt[8]
|
||
|
|
.conn SHA1_Wt_1[8] next_Wt[9]
|
||
|
|
.conn SHA1_Wt_1[9] next_Wt[10]
|
||
|
|
.conn SHA1_Wt_1[10] next_Wt[11]
|
||
|
|
.conn SHA1_Wt_1[11] next_Wt[12]
|
||
|
|
.conn SHA1_Wt_1[12] next_Wt[13]
|
||
|
|
.conn SHA1_Wt_1[13] next_Wt[14]
|
||
|
|
.conn SHA1_Wt_1[14] next_Wt[15]
|
||
|
|
.conn SHA1_Wt_1[15] next_Wt[16]
|
||
|
|
.conn SHA1_Wt_1[16] next_Wt[17]
|
||
|
|
.conn SHA1_Wt_1[17] next_Wt[18]
|
||
|
|
.conn SHA1_Wt_1[18] next_Wt[19]
|
||
|
|
.conn SHA1_Wt_1[19] next_Wt[20]
|
||
|
|
.conn SHA1_Wt_1[20] next_Wt[21]
|
||
|
|
.conn SHA1_Wt_1[21] next_Wt[22]
|
||
|
|
.conn SHA1_Wt_1[22] next_Wt[23]
|
||
|
|
.conn SHA1_Wt_1[23] next_Wt[24]
|
||
|
|
.conn SHA1_Wt_1[24] next_Wt[25]
|
||
|
|
.conn SHA1_Wt_1[25] next_Wt[26]
|
||
|
|
.conn SHA1_Wt_1[26] next_Wt[27]
|
||
|
|
.conn SHA1_Wt_1[27] next_Wt[28]
|
||
|
|
.conn SHA1_Wt_1[28] next_Wt[29]
|
||
|
|
.conn SHA1_Wt_1[29] next_Wt[30]
|
||
|
|
.conn SHA1_Wt_1[30] next_Wt[31]
|
||
|
|
.conn $add$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:138$26_Y[0] next_A[0]
|
||
|
|
.conn $add$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:138$26_Y[1] next_A[1]
|
||
|
|
.conn $add$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:138$26_Y[2] next_A[2]
|
||
|
|
.conn $add$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:138$26_Y[3] next_A[3]
|
||
|
|
.conn $add$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:138$26_Y[4] next_A[4]
|
||
|
|
.conn $add$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:138$26_Y[5] next_A[5]
|
||
|
|
.conn $add$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:138$26_Y[6] next_A[6]
|
||
|
|
.conn $add$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:138$26_Y[7] next_A[7]
|
||
|
|
.conn $add$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:138$26_Y[8] next_A[8]
|
||
|
|
.conn $add$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:138$26_Y[9] next_A[9]
|
||
|
|
.conn $add$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:138$26_Y[10] next_A[10]
|
||
|
|
.conn $add$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:138$26_Y[11] next_A[11]
|
||
|
|
.conn $add$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:138$26_Y[12] next_A[12]
|
||
|
|
.conn $add$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:138$26_Y[13] next_A[13]
|
||
|
|
.conn $add$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:138$26_Y[14] next_A[14]
|
||
|
|
.conn $add$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:138$26_Y[15] next_A[15]
|
||
|
|
.conn $add$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:138$26_Y[16] next_A[16]
|
||
|
|
.conn $add$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:138$26_Y[17] next_A[17]
|
||
|
|
.conn $add$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:138$26_Y[18] next_A[18]
|
||
|
|
.conn $add$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:138$26_Y[19] next_A[19]
|
||
|
|
.conn $add$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:138$26_Y[20] next_A[20]
|
||
|
|
.conn $add$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:138$26_Y[21] next_A[21]
|
||
|
|
.conn $add$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:138$26_Y[22] next_A[22]
|
||
|
|
.conn $add$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:138$26_Y[23] next_A[23]
|
||
|
|
.conn $add$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:138$26_Y[24] next_A[24]
|
||
|
|
.conn $add$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:138$26_Y[25] next_A[25]
|
||
|
|
.conn $add$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:138$26_Y[26] next_A[26]
|
||
|
|
.conn $add$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:138$26_Y[27] next_A[27]
|
||
|
|
.conn $add$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:138$26_Y[28] next_A[28]
|
||
|
|
.conn $add$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:138$26_Y[29] next_A[29]
|
||
|
|
.conn $add$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:138$26_Y[30] next_A[30]
|
||
|
|
.conn $add$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:138$26_Y[31] next_A[31]
|
||
|
|
.conn B[2] next_C[0]
|
||
|
|
.conn B[3] next_C[1]
|
||
|
|
.conn B[4] next_C[2]
|
||
|
|
.conn B[5] next_C[3]
|
||
|
|
.conn B[6] next_C[4]
|
||
|
|
.conn B[7] next_C[5]
|
||
|
|
.conn B[8] next_C[6]
|
||
|
|
.conn B[9] next_C[7]
|
||
|
|
.conn B[10] next_C[8]
|
||
|
|
.conn B[11] next_C[9]
|
||
|
|
.conn B[12] next_C[10]
|
||
|
|
.conn B[13] next_C[11]
|
||
|
|
.conn B[14] next_C[12]
|
||
|
|
.conn B[15] next_C[13]
|
||
|
|
.conn B[16] next_C[14]
|
||
|
|
.conn B[17] next_C[15]
|
||
|
|
.conn B[18] next_C[16]
|
||
|
|
.conn B[19] next_C[17]
|
||
|
|
.conn B[20] next_C[18]
|
||
|
|
.conn B[21] next_C[19]
|
||
|
|
.conn B[22] next_C[20]
|
||
|
|
.conn B[23] next_C[21]
|
||
|
|
.conn B[24] next_C[22]
|
||
|
|
.conn B[25] next_C[23]
|
||
|
|
.conn B[26] next_C[24]
|
||
|
|
.conn B[27] next_C[25]
|
||
|
|
.conn B[28] next_C[26]
|
||
|
|
.conn B[29] next_C[27]
|
||
|
|
.conn B[30] next_C[28]
|
||
|
|
.conn B[31] next_C[29]
|
||
|
|
.conn B[0] next_C[30]
|
||
|
|
.conn B[1] next_C[31]
|
||
|
|
.conn E[0] SHA1_result[0]
|
||
|
|
.conn E[1] SHA1_result[1]
|
||
|
|
.conn E[2] SHA1_result[2]
|
||
|
|
.conn E[3] SHA1_result[3]
|
||
|
|
.conn E[4] SHA1_result[4]
|
||
|
|
.conn E[5] SHA1_result[5]
|
||
|
|
.conn E[6] SHA1_result[6]
|
||
|
|
.conn E[7] SHA1_result[7]
|
||
|
|
.conn E[8] SHA1_result[8]
|
||
|
|
.conn E[9] SHA1_result[9]
|
||
|
|
.conn E[10] SHA1_result[10]
|
||
|
|
.conn E[11] SHA1_result[11]
|
||
|
|
.conn E[12] SHA1_result[12]
|
||
|
|
.conn E[13] SHA1_result[13]
|
||
|
|
.conn E[14] SHA1_result[14]
|
||
|
|
.conn E[15] SHA1_result[15]
|
||
|
|
.conn E[16] SHA1_result[16]
|
||
|
|
.conn E[17] SHA1_result[17]
|
||
|
|
.conn E[18] SHA1_result[18]
|
||
|
|
.conn E[19] SHA1_result[19]
|
||
|
|
.conn E[20] SHA1_result[20]
|
||
|
|
.conn E[21] SHA1_result[21]
|
||
|
|
.conn E[22] SHA1_result[22]
|
||
|
|
.conn E[23] SHA1_result[23]
|
||
|
|
.conn E[24] SHA1_result[24]
|
||
|
|
.conn E[25] SHA1_result[25]
|
||
|
|
.conn E[26] SHA1_result[26]
|
||
|
|
.conn E[27] SHA1_result[27]
|
||
|
|
.conn E[28] SHA1_result[28]
|
||
|
|
.conn E[29] SHA1_result[29]
|
||
|
|
.conn E[30] SHA1_result[30]
|
||
|
|
.conn E[31] SHA1_result[31]
|
||
|
|
.conn D[0] SHA1_result[32]
|
||
|
|
.conn D[1] SHA1_result[33]
|
||
|
|
.conn D[2] SHA1_result[34]
|
||
|
|
.conn D[3] SHA1_result[35]
|
||
|
|
.conn D[4] SHA1_result[36]
|
||
|
|
.conn D[5] SHA1_result[37]
|
||
|
|
.conn D[6] SHA1_result[38]
|
||
|
|
.conn D[7] SHA1_result[39]
|
||
|
|
.conn D[8] SHA1_result[40]
|
||
|
|
.conn D[9] SHA1_result[41]
|
||
|
|
.conn D[10] SHA1_result[42]
|
||
|
|
.conn D[11] SHA1_result[43]
|
||
|
|
.conn D[12] SHA1_result[44]
|
||
|
|
.conn D[13] SHA1_result[45]
|
||
|
|
.conn D[14] SHA1_result[46]
|
||
|
|
.conn D[15] SHA1_result[47]
|
||
|
|
.conn D[16] SHA1_result[48]
|
||
|
|
.conn D[17] SHA1_result[49]
|
||
|
|
.conn D[18] SHA1_result[50]
|
||
|
|
.conn D[19] SHA1_result[51]
|
||
|
|
.conn D[20] SHA1_result[52]
|
||
|
|
.conn D[21] SHA1_result[53]
|
||
|
|
.conn D[22] SHA1_result[54]
|
||
|
|
.conn D[23] SHA1_result[55]
|
||
|
|
.conn D[24] SHA1_result[56]
|
||
|
|
.conn D[25] SHA1_result[57]
|
||
|
|
.conn D[26] SHA1_result[58]
|
||
|
|
.conn D[27] SHA1_result[59]
|
||
|
|
.conn D[28] SHA1_result[60]
|
||
|
|
.conn D[29] SHA1_result[61]
|
||
|
|
.conn D[30] SHA1_result[62]
|
||
|
|
.conn D[31] SHA1_result[63]
|
||
|
|
.conn C[0] SHA1_result[64]
|
||
|
|
.conn C[1] SHA1_result[65]
|
||
|
|
.conn C[2] SHA1_result[66]
|
||
|
|
.conn C[3] SHA1_result[67]
|
||
|
|
.conn C[4] SHA1_result[68]
|
||
|
|
.conn C[5] SHA1_result[69]
|
||
|
|
.conn C[6] SHA1_result[70]
|
||
|
|
.conn C[7] SHA1_result[71]
|
||
|
|
.conn C[8] SHA1_result[72]
|
||
|
|
.conn C[9] SHA1_result[73]
|
||
|
|
.conn C[10] SHA1_result[74]
|
||
|
|
.conn C[11] SHA1_result[75]
|
||
|
|
.conn C[12] SHA1_result[76]
|
||
|
|
.conn C[13] SHA1_result[77]
|
||
|
|
.conn C[14] SHA1_result[78]
|
||
|
|
.conn C[15] SHA1_result[79]
|
||
|
|
.conn C[16] SHA1_result[80]
|
||
|
|
.conn C[17] SHA1_result[81]
|
||
|
|
.conn C[18] SHA1_result[82]
|
||
|
|
.conn C[19] SHA1_result[83]
|
||
|
|
.conn C[20] SHA1_result[84]
|
||
|
|
.conn C[21] SHA1_result[85]
|
||
|
|
.conn C[22] SHA1_result[86]
|
||
|
|
.conn C[23] SHA1_result[87]
|
||
|
|
.conn C[24] SHA1_result[88]
|
||
|
|
.conn C[25] SHA1_result[89]
|
||
|
|
.conn C[26] SHA1_result[90]
|
||
|
|
.conn C[27] SHA1_result[91]
|
||
|
|
.conn C[28] SHA1_result[92]
|
||
|
|
.conn C[29] SHA1_result[93]
|
||
|
|
.conn C[30] SHA1_result[94]
|
||
|
|
.conn C[31] SHA1_result[95]
|
||
|
|
.conn B[0] SHA1_result[96]
|
||
|
|
.conn B[1] SHA1_result[97]
|
||
|
|
.conn B[2] SHA1_result[98]
|
||
|
|
.conn B[3] SHA1_result[99]
|
||
|
|
.conn B[4] SHA1_result[100]
|
||
|
|
.conn B[5] SHA1_result[101]
|
||
|
|
.conn B[6] SHA1_result[102]
|
||
|
|
.conn B[7] SHA1_result[103]
|
||
|
|
.conn B[8] SHA1_result[104]
|
||
|
|
.conn B[9] SHA1_result[105]
|
||
|
|
.conn B[10] SHA1_result[106]
|
||
|
|
.conn B[11] SHA1_result[107]
|
||
|
|
.conn B[12] SHA1_result[108]
|
||
|
|
.conn B[13] SHA1_result[109]
|
||
|
|
.conn B[14] SHA1_result[110]
|
||
|
|
.conn B[15] SHA1_result[111]
|
||
|
|
.conn B[16] SHA1_result[112]
|
||
|
|
.conn B[17] SHA1_result[113]
|
||
|
|
.conn B[18] SHA1_result[114]
|
||
|
|
.conn B[19] SHA1_result[115]
|
||
|
|
.conn B[20] SHA1_result[116]
|
||
|
|
.conn B[21] SHA1_result[117]
|
||
|
|
.conn B[22] SHA1_result[118]
|
||
|
|
.conn B[23] SHA1_result[119]
|
||
|
|
.conn B[24] SHA1_result[120]
|
||
|
|
.conn B[25] SHA1_result[121]
|
||
|
|
.conn B[26] SHA1_result[122]
|
||
|
|
.conn B[27] SHA1_result[123]
|
||
|
|
.conn B[28] SHA1_result[124]
|
||
|
|
.conn B[29] SHA1_result[125]
|
||
|
|
.conn B[30] SHA1_result[126]
|
||
|
|
.conn B[31] SHA1_result[127]
|
||
|
|
.conn A[0] SHA1_result[128]
|
||
|
|
.conn A[1] SHA1_result[129]
|
||
|
|
.conn A[2] SHA1_result[130]
|
||
|
|
.conn A[3] SHA1_result[131]
|
||
|
|
.conn A[4] SHA1_result[132]
|
||
|
|
.conn A[5] SHA1_result[133]
|
||
|
|
.conn A[6] SHA1_result[134]
|
||
|
|
.conn A[7] SHA1_result[135]
|
||
|
|
.conn A[8] SHA1_result[136]
|
||
|
|
.conn A[9] SHA1_result[137]
|
||
|
|
.conn A[10] SHA1_result[138]
|
||
|
|
.conn A[11] SHA1_result[139]
|
||
|
|
.conn A[12] SHA1_result[140]
|
||
|
|
.conn A[13] SHA1_result[141]
|
||
|
|
.conn A[14] SHA1_result[142]
|
||
|
|
.conn A[15] SHA1_result[143]
|
||
|
|
.conn A[16] SHA1_result[144]
|
||
|
|
.conn A[17] SHA1_result[145]
|
||
|
|
.conn A[18] SHA1_result[146]
|
||
|
|
.conn A[19] SHA1_result[147]
|
||
|
|
.conn A[20] SHA1_result[148]
|
||
|
|
.conn A[21] SHA1_result[149]
|
||
|
|
.conn A[22] SHA1_result[150]
|
||
|
|
.conn A[23] SHA1_result[151]
|
||
|
|
.conn A[24] SHA1_result[152]
|
||
|
|
.conn A[25] SHA1_result[153]
|
||
|
|
.conn A[26] SHA1_result[154]
|
||
|
|
.conn A[27] SHA1_result[155]
|
||
|
|
.conn A[28] SHA1_result[156]
|
||
|
|
.conn A[29] SHA1_result[157]
|
||
|
|
.conn A[30] SHA1_result[158]
|
||
|
|
.conn A[31] SHA1_result[159]
|
||
|
|
.conn $add$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:143$27_Y[0] round_plus_1[0]
|
||
|
|
.conn $add$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:143$27_Y[1] round_plus_1[1]
|
||
|
|
.conn $add$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:143$27_Y[2] round_plus_1[2]
|
||
|
|
.conn $add$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:143$27_Y[3] round_plus_1[3]
|
||
|
|
.conn $add$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:143$27_Y[4] round_plus_1[4]
|
||
|
|
.conn $add$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:143$27_Y[5] round_plus_1[5]
|
||
|
|
.conn $add$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:143$27_Y[6] round_plus_1[6]
|
||
|
|
.conn $reduce_or$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:2159$40_Y $procmux$45_CMP
|
||
|
|
.conn $not$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:2149$39_Y $procmux$47_CMP
|
||
|
|
.conn cmd[0] $procmux$50_CMP
|
||
|
|
.conn rst_i $procmux$53_CMP
|
||
|
|
.conn $procmux$52_Y[0] $0\read_counter[2:0][0]
|
||
|
|
.conn $procmux$52_Y[1] $0\read_counter[2:0][1]
|
||
|
|
.conn $procmux$52_Y[2] $0\read_counter[2:0][2]
|
||
|
|
.conn $not$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:2149$39_Y $procmux$63_CMP
|
||
|
|
.conn cmd[0] $procmux$66_CMP
|
||
|
|
.conn rst_i $procmux$69_CMP
|
||
|
|
.conn $procmux$68_Y[0] $0\text_o[31:0][0]
|
||
|
|
.conn $procmux$68_Y[1] $0\text_o[31:0][1]
|
||
|
|
.conn $procmux$68_Y[2] $0\text_o[31:0][2]
|
||
|
|
.conn $procmux$68_Y[3] $0\text_o[31:0][3]
|
||
|
|
.conn $procmux$68_Y[4] $0\text_o[31:0][4]
|
||
|
|
.conn $procmux$68_Y[5] $0\text_o[31:0][5]
|
||
|
|
.conn $procmux$68_Y[6] $0\text_o[31:0][6]
|
||
|
|
.conn $procmux$68_Y[7] $0\text_o[31:0][7]
|
||
|
|
.conn $procmux$68_Y[8] $0\text_o[31:0][8]
|
||
|
|
.conn $procmux$68_Y[9] $0\text_o[31:0][9]
|
||
|
|
.conn $procmux$68_Y[10] $0\text_o[31:0][10]
|
||
|
|
.conn $procmux$68_Y[11] $0\text_o[31:0][11]
|
||
|
|
.conn $procmux$68_Y[12] $0\text_o[31:0][12]
|
||
|
|
.conn $procmux$68_Y[13] $0\text_o[31:0][13]
|
||
|
|
.conn $procmux$68_Y[14] $0\text_o[31:0][14]
|
||
|
|
.conn $procmux$68_Y[15] $0\text_o[31:0][15]
|
||
|
|
.conn $procmux$68_Y[16] $0\text_o[31:0][16]
|
||
|
|
.conn $procmux$68_Y[17] $0\text_o[31:0][17]
|
||
|
|
.conn $procmux$68_Y[18] $0\text_o[31:0][18]
|
||
|
|
.conn $procmux$68_Y[19] $0\text_o[31:0][19]
|
||
|
|
.conn $procmux$68_Y[20] $0\text_o[31:0][20]
|
||
|
|
.conn $procmux$68_Y[21] $0\text_o[31:0][21]
|
||
|
|
.conn $procmux$68_Y[22] $0\text_o[31:0][22]
|
||
|
|
.conn $procmux$68_Y[23] $0\text_o[31:0][23]
|
||
|
|
.conn $procmux$68_Y[24] $0\text_o[31:0][24]
|
||
|
|
.conn $procmux$68_Y[25] $0\text_o[31:0][25]
|
||
|
|
.conn $procmux$68_Y[26] $0\text_o[31:0][26]
|
||
|
|
.conn $procmux$68_Y[27] $0\text_o[31:0][27]
|
||
|
|
.conn $procmux$68_Y[28] $0\text_o[31:0][28]
|
||
|
|
.conn $procmux$68_Y[29] $0\text_o[31:0][29]
|
||
|
|
.conn $procmux$68_Y[30] $0\text_o[31:0][30]
|
||
|
|
.conn $procmux$68_Y[31] $0\text_o[31:0][31]
|
||
|
|
.conn $lt$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:2124$37_Y $procmux$72_CMP
|
||
|
|
.conn $lt$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:2121$36_Y $procmux$75_CMP
|
||
|
|
.conn $lt$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:2118$35_Y $procmux$78_CMP
|
||
|
|
.conn rst_i $procmux$81_CMP
|
||
|
|
.conn $procmux$80_Y[0] $0\Kt[31:0][0]
|
||
|
|
.conn $procmux$80_Y[1] $0\Kt[31:0][1]
|
||
|
|
.conn $procmux$80_Y[2] $0\Kt[31:0][2]
|
||
|
|
.conn $procmux$80_Y[3] $0\Kt[31:0][3]
|
||
|
|
.conn $procmux$80_Y[4] $0\Kt[31:0][4]
|
||
|
|
.conn $procmux$80_Y[5] $0\Kt[31:0][5]
|
||
|
|
.conn $procmux$80_Y[6] $0\Kt[31:0][6]
|
||
|
|
.conn $procmux$80_Y[7] $0\Kt[31:0][7]
|
||
|
|
.conn $procmux$80_Y[8] $0\Kt[31:0][8]
|
||
|
|
.conn $procmux$80_Y[9] $0\Kt[31:0][9]
|
||
|
|
.conn $procmux$80_Y[10] $0\Kt[31:0][10]
|
||
|
|
.conn $procmux$80_Y[11] $0\Kt[31:0][11]
|
||
|
|
.conn $procmux$80_Y[12] $0\Kt[31:0][12]
|
||
|
|
.conn $procmux$80_Y[13] $0\Kt[31:0][13]
|
||
|
|
.conn $procmux$80_Y[14] $0\Kt[31:0][14]
|
||
|
|
.conn $procmux$80_Y[15] $0\Kt[31:0][15]
|
||
|
|
.conn $procmux$80_Y[16] $0\Kt[31:0][16]
|
||
|
|
.conn $procmux$80_Y[17] $0\Kt[31:0][17]
|
||
|
|
.conn $procmux$80_Y[18] $0\Kt[31:0][18]
|
||
|
|
.conn $procmux$80_Y[19] $0\Kt[31:0][19]
|
||
|
|
.conn $procmux$80_Y[20] $0\Kt[31:0][20]
|
||
|
|
.conn $procmux$80_Y[21] $0\Kt[31:0][21]
|
||
|
|
.conn $procmux$80_Y[22] $0\Kt[31:0][22]
|
||
|
|
.conn $procmux$80_Y[23] $0\Kt[31:0][23]
|
||
|
|
.conn $procmux$80_Y[24] $0\Kt[31:0][24]
|
||
|
|
.conn $procmux$80_Y[25] $0\Kt[31:0][25]
|
||
|
|
.conn $procmux$80_Y[26] $0\Kt[31:0][26]
|
||
|
|
.conn $procmux$80_Y[27] $0\Kt[31:0][27]
|
||
|
|
.conn $procmux$80_Y[28] $0\Kt[31:0][28]
|
||
|
|
.conn $procmux$80_Y[29] $0\Kt[31:0][29]
|
||
|
|
.conn $procmux$80_Y[30] $0\Kt[31:0][30]
|
||
|
|
.conn $procmux$80_Y[31] $0\Kt[31:0][31]
|
||
|
|
.conn cmd[1] $procmux$166_CMP
|
||
|
|
.conn rst_i $procmux$170_CMP
|
||
|
|
.conn $procmux$169_Y $0\busy[0:0]
|
||
|
|
.conn cmd[1] $procmux$255_CMP
|
||
|
|
.conn rst_i $procmux$259_CMP
|
||
|
|
.conn $procmux$258_Y[0] $0\Wt[31:0][0]
|
||
|
|
.conn $procmux$258_Y[1] $0\Wt[31:0][1]
|
||
|
|
.conn $procmux$258_Y[2] $0\Wt[31:0][2]
|
||
|
|
.conn $procmux$258_Y[3] $0\Wt[31:0][3]
|
||
|
|
.conn $procmux$258_Y[4] $0\Wt[31:0][4]
|
||
|
|
.conn $procmux$258_Y[5] $0\Wt[31:0][5]
|
||
|
|
.conn $procmux$258_Y[6] $0\Wt[31:0][6]
|
||
|
|
.conn $procmux$258_Y[7] $0\Wt[31:0][7]
|
||
|
|
.conn $procmux$258_Y[8] $0\Wt[31:0][8]
|
||
|
|
.conn $procmux$258_Y[9] $0\Wt[31:0][9]
|
||
|
|
.conn $procmux$258_Y[10] $0\Wt[31:0][10]
|
||
|
|
.conn $procmux$258_Y[11] $0\Wt[31:0][11]
|
||
|
|
.conn $procmux$258_Y[12] $0\Wt[31:0][12]
|
||
|
|
.conn $procmux$258_Y[13] $0\Wt[31:0][13]
|
||
|
|
.conn $procmux$258_Y[14] $0\Wt[31:0][14]
|
||
|
|
.conn $procmux$258_Y[15] $0\Wt[31:0][15]
|
||
|
|
.conn $procmux$258_Y[16] $0\Wt[31:0][16]
|
||
|
|
.conn $procmux$258_Y[17] $0\Wt[31:0][17]
|
||
|
|
.conn $procmux$258_Y[18] $0\Wt[31:0][18]
|
||
|
|
.conn $procmux$258_Y[19] $0\Wt[31:0][19]
|
||
|
|
.conn $procmux$258_Y[20] $0\Wt[31:0][20]
|
||
|
|
.conn $procmux$258_Y[21] $0\Wt[31:0][21]
|
||
|
|
.conn $procmux$258_Y[22] $0\Wt[31:0][22]
|
||
|
|
.conn $procmux$258_Y[23] $0\Wt[31:0][23]
|
||
|
|
.conn $procmux$258_Y[24] $0\Wt[31:0][24]
|
||
|
|
.conn $procmux$258_Y[25] $0\Wt[31:0][25]
|
||
|
|
.conn $procmux$258_Y[26] $0\Wt[31:0][26]
|
||
|
|
.conn $procmux$258_Y[27] $0\Wt[31:0][27]
|
||
|
|
.conn $procmux$258_Y[28] $0\Wt[31:0][28]
|
||
|
|
.conn $procmux$258_Y[29] $0\Wt[31:0][29]
|
||
|
|
.conn $procmux$258_Y[30] $0\Wt[31:0][30]
|
||
|
|
.conn $procmux$258_Y[31] $0\Wt[31:0][31]
|
||
|
|
.conn rst_i $procmux$330_CMP
|
||
|
|
.conn $procmux$329_Y[0] $0\W14[31:0][0]
|
||
|
|
.conn $procmux$329_Y[1] $0\W14[31:0][1]
|
||
|
|
.conn $procmux$329_Y[2] $0\W14[31:0][2]
|
||
|
|
.conn $procmux$329_Y[3] $0\W14[31:0][3]
|
||
|
|
.conn $procmux$329_Y[4] $0\W14[31:0][4]
|
||
|
|
.conn $procmux$329_Y[5] $0\W14[31:0][5]
|
||
|
|
.conn $procmux$329_Y[6] $0\W14[31:0][6]
|
||
|
|
.conn $procmux$329_Y[7] $0\W14[31:0][7]
|
||
|
|
.conn $procmux$329_Y[8] $0\W14[31:0][8]
|
||
|
|
.conn $procmux$329_Y[9] $0\W14[31:0][9]
|
||
|
|
.conn $procmux$329_Y[10] $0\W14[31:0][10]
|
||
|
|
.conn $procmux$329_Y[11] $0\W14[31:0][11]
|
||
|
|
.conn $procmux$329_Y[12] $0\W14[31:0][12]
|
||
|
|
.conn $procmux$329_Y[13] $0\W14[31:0][13]
|
||
|
|
.conn $procmux$329_Y[14] $0\W14[31:0][14]
|
||
|
|
.conn $procmux$329_Y[15] $0\W14[31:0][15]
|
||
|
|
.conn $procmux$329_Y[16] $0\W14[31:0][16]
|
||
|
|
.conn $procmux$329_Y[17] $0\W14[31:0][17]
|
||
|
|
.conn $procmux$329_Y[18] $0\W14[31:0][18]
|
||
|
|
.conn $procmux$329_Y[19] $0\W14[31:0][19]
|
||
|
|
.conn $procmux$329_Y[20] $0\W14[31:0][20]
|
||
|
|
.conn $procmux$329_Y[21] $0\W14[31:0][21]
|
||
|
|
.conn $procmux$329_Y[22] $0\W14[31:0][22]
|
||
|
|
.conn $procmux$329_Y[23] $0\W14[31:0][23]
|
||
|
|
.conn $procmux$329_Y[24] $0\W14[31:0][24]
|
||
|
|
.conn $procmux$329_Y[25] $0\W14[31:0][25]
|
||
|
|
.conn $procmux$329_Y[26] $0\W14[31:0][26]
|
||
|
|
.conn $procmux$329_Y[27] $0\W14[31:0][27]
|
||
|
|
.conn $procmux$329_Y[28] $0\W14[31:0][28]
|
||
|
|
.conn $procmux$329_Y[29] $0\W14[31:0][29]
|
||
|
|
.conn $procmux$329_Y[30] $0\W14[31:0][30]
|
||
|
|
.conn $procmux$329_Y[31] $0\W14[31:0][31]
|
||
|
|
.conn rst_i $procmux$401_CMP
|
||
|
|
.conn $procmux$400_Y[0] $0\W13[31:0][0]
|
||
|
|
.conn $procmux$400_Y[1] $0\W13[31:0][1]
|
||
|
|
.conn $procmux$400_Y[2] $0\W13[31:0][2]
|
||
|
|
.conn $procmux$400_Y[3] $0\W13[31:0][3]
|
||
|
|
.conn $procmux$400_Y[4] $0\W13[31:0][4]
|
||
|
|
.conn $procmux$400_Y[5] $0\W13[31:0][5]
|
||
|
|
.conn $procmux$400_Y[6] $0\W13[31:0][6]
|
||
|
|
.conn $procmux$400_Y[7] $0\W13[31:0][7]
|
||
|
|
.conn $procmux$400_Y[8] $0\W13[31:0][8]
|
||
|
|
.conn $procmux$400_Y[9] $0\W13[31:0][9]
|
||
|
|
.conn $procmux$400_Y[10] $0\W13[31:0][10]
|
||
|
|
.conn $procmux$400_Y[11] $0\W13[31:0][11]
|
||
|
|
.conn $procmux$400_Y[12] $0\W13[31:0][12]
|
||
|
|
.conn $procmux$400_Y[13] $0\W13[31:0][13]
|
||
|
|
.conn $procmux$400_Y[14] $0\W13[31:0][14]
|
||
|
|
.conn $procmux$400_Y[15] $0\W13[31:0][15]
|
||
|
|
.conn $procmux$400_Y[16] $0\W13[31:0][16]
|
||
|
|
.conn $procmux$400_Y[17] $0\W13[31:0][17]
|
||
|
|
.conn $procmux$400_Y[18] $0\W13[31:0][18]
|
||
|
|
.conn $procmux$400_Y[19] $0\W13[31:0][19]
|
||
|
|
.conn $procmux$400_Y[20] $0\W13[31:0][20]
|
||
|
|
.conn $procmux$400_Y[21] $0\W13[31:0][21]
|
||
|
|
.conn $procmux$400_Y[22] $0\W13[31:0][22]
|
||
|
|
.conn $procmux$400_Y[23] $0\W13[31:0][23]
|
||
|
|
.conn $procmux$400_Y[24] $0\W13[31:0][24]
|
||
|
|
.conn $procmux$400_Y[25] $0\W13[31:0][25]
|
||
|
|
.conn $procmux$400_Y[26] $0\W13[31:0][26]
|
||
|
|
.conn $procmux$400_Y[27] $0\W13[31:0][27]
|
||
|
|
.conn $procmux$400_Y[28] $0\W13[31:0][28]
|
||
|
|
.conn $procmux$400_Y[29] $0\W13[31:0][29]
|
||
|
|
.conn $procmux$400_Y[30] $0\W13[31:0][30]
|
||
|
|
.conn $procmux$400_Y[31] $0\W13[31:0][31]
|
||
|
|
.conn rst_i $procmux$472_CMP
|
||
|
|
.conn $procmux$471_Y[0] $0\W12[31:0][0]
|
||
|
|
.conn $procmux$471_Y[1] $0\W12[31:0][1]
|
||
|
|
.conn $procmux$471_Y[2] $0\W12[31:0][2]
|
||
|
|
.conn $procmux$471_Y[3] $0\W12[31:0][3]
|
||
|
|
.conn $procmux$471_Y[4] $0\W12[31:0][4]
|
||
|
|
.conn $procmux$471_Y[5] $0\W12[31:0][5]
|
||
|
|
.conn $procmux$471_Y[6] $0\W12[31:0][6]
|
||
|
|
.conn $procmux$471_Y[7] $0\W12[31:0][7]
|
||
|
|
.conn $procmux$471_Y[8] $0\W12[31:0][8]
|
||
|
|
.conn $procmux$471_Y[9] $0\W12[31:0][9]
|
||
|
|
.conn $procmux$471_Y[10] $0\W12[31:0][10]
|
||
|
|
.conn $procmux$471_Y[11] $0\W12[31:0][11]
|
||
|
|
.conn $procmux$471_Y[12] $0\W12[31:0][12]
|
||
|
|
.conn $procmux$471_Y[13] $0\W12[31:0][13]
|
||
|
|
.conn $procmux$471_Y[14] $0\W12[31:0][14]
|
||
|
|
.conn $procmux$471_Y[15] $0\W12[31:0][15]
|
||
|
|
.conn $procmux$471_Y[16] $0\W12[31:0][16]
|
||
|
|
.conn $procmux$471_Y[17] $0\W12[31:0][17]
|
||
|
|
.conn $procmux$471_Y[18] $0\W12[31:0][18]
|
||
|
|
.conn $procmux$471_Y[19] $0\W12[31:0][19]
|
||
|
|
.conn $procmux$471_Y[20] $0\W12[31:0][20]
|
||
|
|
.conn $procmux$471_Y[21] $0\W12[31:0][21]
|
||
|
|
.conn $procmux$471_Y[22] $0\W12[31:0][22]
|
||
|
|
.conn $procmux$471_Y[23] $0\W12[31:0][23]
|
||
|
|
.conn $procmux$471_Y[24] $0\W12[31:0][24]
|
||
|
|
.conn $procmux$471_Y[25] $0\W12[31:0][25]
|
||
|
|
.conn $procmux$471_Y[26] $0\W12[31:0][26]
|
||
|
|
.conn $procmux$471_Y[27] $0\W12[31:0][27]
|
||
|
|
.conn $procmux$471_Y[28] $0\W12[31:0][28]
|
||
|
|
.conn $procmux$471_Y[29] $0\W12[31:0][29]
|
||
|
|
.conn $procmux$471_Y[30] $0\W12[31:0][30]
|
||
|
|
.conn $procmux$471_Y[31] $0\W12[31:0][31]
|
||
|
|
.conn rst_i $procmux$543_CMP
|
||
|
|
.conn $procmux$542_Y[0] $0\W11[31:0][0]
|
||
|
|
.conn $procmux$542_Y[1] $0\W11[31:0][1]
|
||
|
|
.conn $procmux$542_Y[2] $0\W11[31:0][2]
|
||
|
|
.conn $procmux$542_Y[3] $0\W11[31:0][3]
|
||
|
|
.conn $procmux$542_Y[4] $0\W11[31:0][4]
|
||
|
|
.conn $procmux$542_Y[5] $0\W11[31:0][5]
|
||
|
|
.conn $procmux$542_Y[6] $0\W11[31:0][6]
|
||
|
|
.conn $procmux$542_Y[7] $0\W11[31:0][7]
|
||
|
|
.conn $procmux$542_Y[8] $0\W11[31:0][8]
|
||
|
|
.conn $procmux$542_Y[9] $0\W11[31:0][9]
|
||
|
|
.conn $procmux$542_Y[10] $0\W11[31:0][10]
|
||
|
|
.conn $procmux$542_Y[11] $0\W11[31:0][11]
|
||
|
|
.conn $procmux$542_Y[12] $0\W11[31:0][12]
|
||
|
|
.conn $procmux$542_Y[13] $0\W11[31:0][13]
|
||
|
|
.conn $procmux$542_Y[14] $0\W11[31:0][14]
|
||
|
|
.conn $procmux$542_Y[15] $0\W11[31:0][15]
|
||
|
|
.conn $procmux$542_Y[16] $0\W11[31:0][16]
|
||
|
|
.conn $procmux$542_Y[17] $0\W11[31:0][17]
|
||
|
|
.conn $procmux$542_Y[18] $0\W11[31:0][18]
|
||
|
|
.conn $procmux$542_Y[19] $0\W11[31:0][19]
|
||
|
|
.conn $procmux$542_Y[20] $0\W11[31:0][20]
|
||
|
|
.conn $procmux$542_Y[21] $0\W11[31:0][21]
|
||
|
|
.conn $procmux$542_Y[22] $0\W11[31:0][22]
|
||
|
|
.conn $procmux$542_Y[23] $0\W11[31:0][23]
|
||
|
|
.conn $procmux$542_Y[24] $0\W11[31:0][24]
|
||
|
|
.conn $procmux$542_Y[25] $0\W11[31:0][25]
|
||
|
|
.conn $procmux$542_Y[26] $0\W11[31:0][26]
|
||
|
|
.conn $procmux$542_Y[27] $0\W11[31:0][27]
|
||
|
|
.conn $procmux$542_Y[28] $0\W11[31:0][28]
|
||
|
|
.conn $procmux$542_Y[29] $0\W11[31:0][29]
|
||
|
|
.conn $procmux$542_Y[30] $0\W11[31:0][30]
|
||
|
|
.conn $procmux$542_Y[31] $0\W11[31:0][31]
|
||
|
|
.conn rst_i $procmux$614_CMP
|
||
|
|
.conn $procmux$613_Y[0] $0\W10[31:0][0]
|
||
|
|
.conn $procmux$613_Y[1] $0\W10[31:0][1]
|
||
|
|
.conn $procmux$613_Y[2] $0\W10[31:0][2]
|
||
|
|
.conn $procmux$613_Y[3] $0\W10[31:0][3]
|
||
|
|
.conn $procmux$613_Y[4] $0\W10[31:0][4]
|
||
|
|
.conn $procmux$613_Y[5] $0\W10[31:0][5]
|
||
|
|
.conn $procmux$613_Y[6] $0\W10[31:0][6]
|
||
|
|
.conn $procmux$613_Y[7] $0\W10[31:0][7]
|
||
|
|
.conn $procmux$613_Y[8] $0\W10[31:0][8]
|
||
|
|
.conn $procmux$613_Y[9] $0\W10[31:0][9]
|
||
|
|
.conn $procmux$613_Y[10] $0\W10[31:0][10]
|
||
|
|
.conn $procmux$613_Y[11] $0\W10[31:0][11]
|
||
|
|
.conn $procmux$613_Y[12] $0\W10[31:0][12]
|
||
|
|
.conn $procmux$613_Y[13] $0\W10[31:0][13]
|
||
|
|
.conn $procmux$613_Y[14] $0\W10[31:0][14]
|
||
|
|
.conn $procmux$613_Y[15] $0\W10[31:0][15]
|
||
|
|
.conn $procmux$613_Y[16] $0\W10[31:0][16]
|
||
|
|
.conn $procmux$613_Y[17] $0\W10[31:0][17]
|
||
|
|
.conn $procmux$613_Y[18] $0\W10[31:0][18]
|
||
|
|
.conn $procmux$613_Y[19] $0\W10[31:0][19]
|
||
|
|
.conn $procmux$613_Y[20] $0\W10[31:0][20]
|
||
|
|
.conn $procmux$613_Y[21] $0\W10[31:0][21]
|
||
|
|
.conn $procmux$613_Y[22] $0\W10[31:0][22]
|
||
|
|
.conn $procmux$613_Y[23] $0\W10[31:0][23]
|
||
|
|
.conn $procmux$613_Y[24] $0\W10[31:0][24]
|
||
|
|
.conn $procmux$613_Y[25] $0\W10[31:0][25]
|
||
|
|
.conn $procmux$613_Y[26] $0\W10[31:0][26]
|
||
|
|
.conn $procmux$613_Y[27] $0\W10[31:0][27]
|
||
|
|
.conn $procmux$613_Y[28] $0\W10[31:0][28]
|
||
|
|
.conn $procmux$613_Y[29] $0\W10[31:0][29]
|
||
|
|
.conn $procmux$613_Y[30] $0\W10[31:0][30]
|
||
|
|
.conn $procmux$613_Y[31] $0\W10[31:0][31]
|
||
|
|
.conn rst_i $procmux$685_CMP
|
||
|
|
.conn $procmux$684_Y[0] $0\W9[31:0][0]
|
||
|
|
.conn $procmux$684_Y[1] $0\W9[31:0][1]
|
||
|
|
.conn $procmux$684_Y[2] $0\W9[31:0][2]
|
||
|
|
.conn $procmux$684_Y[3] $0\W9[31:0][3]
|
||
|
|
.conn $procmux$684_Y[4] $0\W9[31:0][4]
|
||
|
|
.conn $procmux$684_Y[5] $0\W9[31:0][5]
|
||
|
|
.conn $procmux$684_Y[6] $0\W9[31:0][6]
|
||
|
|
.conn $procmux$684_Y[7] $0\W9[31:0][7]
|
||
|
|
.conn $procmux$684_Y[8] $0\W9[31:0][8]
|
||
|
|
.conn $procmux$684_Y[9] $0\W9[31:0][9]
|
||
|
|
.conn $procmux$684_Y[10] $0\W9[31:0][10]
|
||
|
|
.conn $procmux$684_Y[11] $0\W9[31:0][11]
|
||
|
|
.conn $procmux$684_Y[12] $0\W9[31:0][12]
|
||
|
|
.conn $procmux$684_Y[13] $0\W9[31:0][13]
|
||
|
|
.conn $procmux$684_Y[14] $0\W9[31:0][14]
|
||
|
|
.conn $procmux$684_Y[15] $0\W9[31:0][15]
|
||
|
|
.conn $procmux$684_Y[16] $0\W9[31:0][16]
|
||
|
|
.conn $procmux$684_Y[17] $0\W9[31:0][17]
|
||
|
|
.conn $procmux$684_Y[18] $0\W9[31:0][18]
|
||
|
|
.conn $procmux$684_Y[19] $0\W9[31:0][19]
|
||
|
|
.conn $procmux$684_Y[20] $0\W9[31:0][20]
|
||
|
|
.conn $procmux$684_Y[21] $0\W9[31:0][21]
|
||
|
|
.conn $procmux$684_Y[22] $0\W9[31:0][22]
|
||
|
|
.conn $procmux$684_Y[23] $0\W9[31:0][23]
|
||
|
|
.conn $procmux$684_Y[24] $0\W9[31:0][24]
|
||
|
|
.conn $procmux$684_Y[25] $0\W9[31:0][25]
|
||
|
|
.conn $procmux$684_Y[26] $0\W9[31:0][26]
|
||
|
|
.conn $procmux$684_Y[27] $0\W9[31:0][27]
|
||
|
|
.conn $procmux$684_Y[28] $0\W9[31:0][28]
|
||
|
|
.conn $procmux$684_Y[29] $0\W9[31:0][29]
|
||
|
|
.conn $procmux$684_Y[30] $0\W9[31:0][30]
|
||
|
|
.conn $procmux$684_Y[31] $0\W9[31:0][31]
|
||
|
|
.conn rst_i $procmux$756_CMP
|
||
|
|
.conn $procmux$755_Y[0] $0\W8[31:0][0]
|
||
|
|
.conn $procmux$755_Y[1] $0\W8[31:0][1]
|
||
|
|
.conn $procmux$755_Y[2] $0\W8[31:0][2]
|
||
|
|
.conn $procmux$755_Y[3] $0\W8[31:0][3]
|
||
|
|
.conn $procmux$755_Y[4] $0\W8[31:0][4]
|
||
|
|
.conn $procmux$755_Y[5] $0\W8[31:0][5]
|
||
|
|
.conn $procmux$755_Y[6] $0\W8[31:0][6]
|
||
|
|
.conn $procmux$755_Y[7] $0\W8[31:0][7]
|
||
|
|
.conn $procmux$755_Y[8] $0\W8[31:0][8]
|
||
|
|
.conn $procmux$755_Y[9] $0\W8[31:0][9]
|
||
|
|
.conn $procmux$755_Y[10] $0\W8[31:0][10]
|
||
|
|
.conn $procmux$755_Y[11] $0\W8[31:0][11]
|
||
|
|
.conn $procmux$755_Y[12] $0\W8[31:0][12]
|
||
|
|
.conn $procmux$755_Y[13] $0\W8[31:0][13]
|
||
|
|
.conn $procmux$755_Y[14] $0\W8[31:0][14]
|
||
|
|
.conn $procmux$755_Y[15] $0\W8[31:0][15]
|
||
|
|
.conn $procmux$755_Y[16] $0\W8[31:0][16]
|
||
|
|
.conn $procmux$755_Y[17] $0\W8[31:0][17]
|
||
|
|
.conn $procmux$755_Y[18] $0\W8[31:0][18]
|
||
|
|
.conn $procmux$755_Y[19] $0\W8[31:0][19]
|
||
|
|
.conn $procmux$755_Y[20] $0\W8[31:0][20]
|
||
|
|
.conn $procmux$755_Y[21] $0\W8[31:0][21]
|
||
|
|
.conn $procmux$755_Y[22] $0\W8[31:0][22]
|
||
|
|
.conn $procmux$755_Y[23] $0\W8[31:0][23]
|
||
|
|
.conn $procmux$755_Y[24] $0\W8[31:0][24]
|
||
|
|
.conn $procmux$755_Y[25] $0\W8[31:0][25]
|
||
|
|
.conn $procmux$755_Y[26] $0\W8[31:0][26]
|
||
|
|
.conn $procmux$755_Y[27] $0\W8[31:0][27]
|
||
|
|
.conn $procmux$755_Y[28] $0\W8[31:0][28]
|
||
|
|
.conn $procmux$755_Y[29] $0\W8[31:0][29]
|
||
|
|
.conn $procmux$755_Y[30] $0\W8[31:0][30]
|
||
|
|
.conn $procmux$755_Y[31] $0\W8[31:0][31]
|
||
|
|
.conn rst_i $procmux$827_CMP
|
||
|
|
.conn $procmux$826_Y[0] $0\W7[31:0][0]
|
||
|
|
.conn $procmux$826_Y[1] $0\W7[31:0][1]
|
||
|
|
.conn $procmux$826_Y[2] $0\W7[31:0][2]
|
||
|
|
.conn $procmux$826_Y[3] $0\W7[31:0][3]
|
||
|
|
.conn $procmux$826_Y[4] $0\W7[31:0][4]
|
||
|
|
.conn $procmux$826_Y[5] $0\W7[31:0][5]
|
||
|
|
.conn $procmux$826_Y[6] $0\W7[31:0][6]
|
||
|
|
.conn $procmux$826_Y[7] $0\W7[31:0][7]
|
||
|
|
.conn $procmux$826_Y[8] $0\W7[31:0][8]
|
||
|
|
.conn $procmux$826_Y[9] $0\W7[31:0][9]
|
||
|
|
.conn $procmux$826_Y[10] $0\W7[31:0][10]
|
||
|
|
.conn $procmux$826_Y[11] $0\W7[31:0][11]
|
||
|
|
.conn $procmux$826_Y[12] $0\W7[31:0][12]
|
||
|
|
.conn $procmux$826_Y[13] $0\W7[31:0][13]
|
||
|
|
.conn $procmux$826_Y[14] $0\W7[31:0][14]
|
||
|
|
.conn $procmux$826_Y[15] $0\W7[31:0][15]
|
||
|
|
.conn $procmux$826_Y[16] $0\W7[31:0][16]
|
||
|
|
.conn $procmux$826_Y[17] $0\W7[31:0][17]
|
||
|
|
.conn $procmux$826_Y[18] $0\W7[31:0][18]
|
||
|
|
.conn $procmux$826_Y[19] $0\W7[31:0][19]
|
||
|
|
.conn $procmux$826_Y[20] $0\W7[31:0][20]
|
||
|
|
.conn $procmux$826_Y[21] $0\W7[31:0][21]
|
||
|
|
.conn $procmux$826_Y[22] $0\W7[31:0][22]
|
||
|
|
.conn $procmux$826_Y[23] $0\W7[31:0][23]
|
||
|
|
.conn $procmux$826_Y[24] $0\W7[31:0][24]
|
||
|
|
.conn $procmux$826_Y[25] $0\W7[31:0][25]
|
||
|
|
.conn $procmux$826_Y[26] $0\W7[31:0][26]
|
||
|
|
.conn $procmux$826_Y[27] $0\W7[31:0][27]
|
||
|
|
.conn $procmux$826_Y[28] $0\W7[31:0][28]
|
||
|
|
.conn $procmux$826_Y[29] $0\W7[31:0][29]
|
||
|
|
.conn $procmux$826_Y[30] $0\W7[31:0][30]
|
||
|
|
.conn $procmux$826_Y[31] $0\W7[31:0][31]
|
||
|
|
.conn rst_i $procmux$898_CMP
|
||
|
|
.conn $procmux$897_Y[0] $0\W6[31:0][0]
|
||
|
|
.conn $procmux$897_Y[1] $0\W6[31:0][1]
|
||
|
|
.conn $procmux$897_Y[2] $0\W6[31:0][2]
|
||
|
|
.conn $procmux$897_Y[3] $0\W6[31:0][3]
|
||
|
|
.conn $procmux$897_Y[4] $0\W6[31:0][4]
|
||
|
|
.conn $procmux$897_Y[5] $0\W6[31:0][5]
|
||
|
|
.conn $procmux$897_Y[6] $0\W6[31:0][6]
|
||
|
|
.conn $procmux$897_Y[7] $0\W6[31:0][7]
|
||
|
|
.conn $procmux$897_Y[8] $0\W6[31:0][8]
|
||
|
|
.conn $procmux$897_Y[9] $0\W6[31:0][9]
|
||
|
|
.conn $procmux$897_Y[10] $0\W6[31:0][10]
|
||
|
|
.conn $procmux$897_Y[11] $0\W6[31:0][11]
|
||
|
|
.conn $procmux$897_Y[12] $0\W6[31:0][12]
|
||
|
|
.conn $procmux$897_Y[13] $0\W6[31:0][13]
|
||
|
|
.conn $procmux$897_Y[14] $0\W6[31:0][14]
|
||
|
|
.conn $procmux$897_Y[15] $0\W6[31:0][15]
|
||
|
|
.conn $procmux$897_Y[16] $0\W6[31:0][16]
|
||
|
|
.conn $procmux$897_Y[17] $0\W6[31:0][17]
|
||
|
|
.conn $procmux$897_Y[18] $0\W6[31:0][18]
|
||
|
|
.conn $procmux$897_Y[19] $0\W6[31:0][19]
|
||
|
|
.conn $procmux$897_Y[20] $0\W6[31:0][20]
|
||
|
|
.conn $procmux$897_Y[21] $0\W6[31:0][21]
|
||
|
|
.conn $procmux$897_Y[22] $0\W6[31:0][22]
|
||
|
|
.conn $procmux$897_Y[23] $0\W6[31:0][23]
|
||
|
|
.conn $procmux$897_Y[24] $0\W6[31:0][24]
|
||
|
|
.conn $procmux$897_Y[25] $0\W6[31:0][25]
|
||
|
|
.conn $procmux$897_Y[26] $0\W6[31:0][26]
|
||
|
|
.conn $procmux$897_Y[27] $0\W6[31:0][27]
|
||
|
|
.conn $procmux$897_Y[28] $0\W6[31:0][28]
|
||
|
|
.conn $procmux$897_Y[29] $0\W6[31:0][29]
|
||
|
|
.conn $procmux$897_Y[30] $0\W6[31:0][30]
|
||
|
|
.conn $procmux$897_Y[31] $0\W6[31:0][31]
|
||
|
|
.conn rst_i $procmux$969_CMP
|
||
|
|
.conn $procmux$968_Y[0] $0\W5[31:0][0]
|
||
|
|
.conn $procmux$968_Y[1] $0\W5[31:0][1]
|
||
|
|
.conn $procmux$968_Y[2] $0\W5[31:0][2]
|
||
|
|
.conn $procmux$968_Y[3] $0\W5[31:0][3]
|
||
|
|
.conn $procmux$968_Y[4] $0\W5[31:0][4]
|
||
|
|
.conn $procmux$968_Y[5] $0\W5[31:0][5]
|
||
|
|
.conn $procmux$968_Y[6] $0\W5[31:0][6]
|
||
|
|
.conn $procmux$968_Y[7] $0\W5[31:0][7]
|
||
|
|
.conn $procmux$968_Y[8] $0\W5[31:0][8]
|
||
|
|
.conn $procmux$968_Y[9] $0\W5[31:0][9]
|
||
|
|
.conn $procmux$968_Y[10] $0\W5[31:0][10]
|
||
|
|
.conn $procmux$968_Y[11] $0\W5[31:0][11]
|
||
|
|
.conn $procmux$968_Y[12] $0\W5[31:0][12]
|
||
|
|
.conn $procmux$968_Y[13] $0\W5[31:0][13]
|
||
|
|
.conn $procmux$968_Y[14] $0\W5[31:0][14]
|
||
|
|
.conn $procmux$968_Y[15] $0\W5[31:0][15]
|
||
|
|
.conn $procmux$968_Y[16] $0\W5[31:0][16]
|
||
|
|
.conn $procmux$968_Y[17] $0\W5[31:0][17]
|
||
|
|
.conn $procmux$968_Y[18] $0\W5[31:0][18]
|
||
|
|
.conn $procmux$968_Y[19] $0\W5[31:0][19]
|
||
|
|
.conn $procmux$968_Y[20] $0\W5[31:0][20]
|
||
|
|
.conn $procmux$968_Y[21] $0\W5[31:0][21]
|
||
|
|
.conn $procmux$968_Y[22] $0\W5[31:0][22]
|
||
|
|
.conn $procmux$968_Y[23] $0\W5[31:0][23]
|
||
|
|
.conn $procmux$968_Y[24] $0\W5[31:0][24]
|
||
|
|
.conn $procmux$968_Y[25] $0\W5[31:0][25]
|
||
|
|
.conn $procmux$968_Y[26] $0\W5[31:0][26]
|
||
|
|
.conn $procmux$968_Y[27] $0\W5[31:0][27]
|
||
|
|
.conn $procmux$968_Y[28] $0\W5[31:0][28]
|
||
|
|
.conn $procmux$968_Y[29] $0\W5[31:0][29]
|
||
|
|
.conn $procmux$968_Y[30] $0\W5[31:0][30]
|
||
|
|
.conn $procmux$968_Y[31] $0\W5[31:0][31]
|
||
|
|
.conn rst_i $procmux$1040_CMP
|
||
|
|
.conn $procmux$1039_Y[0] $0\W4[31:0][0]
|
||
|
|
.conn $procmux$1039_Y[1] $0\W4[31:0][1]
|
||
|
|
.conn $procmux$1039_Y[2] $0\W4[31:0][2]
|
||
|
|
.conn $procmux$1039_Y[3] $0\W4[31:0][3]
|
||
|
|
.conn $procmux$1039_Y[4] $0\W4[31:0][4]
|
||
|
|
.conn $procmux$1039_Y[5] $0\W4[31:0][5]
|
||
|
|
.conn $procmux$1039_Y[6] $0\W4[31:0][6]
|
||
|
|
.conn $procmux$1039_Y[7] $0\W4[31:0][7]
|
||
|
|
.conn $procmux$1039_Y[8] $0\W4[31:0][8]
|
||
|
|
.conn $procmux$1039_Y[9] $0\W4[31:0][9]
|
||
|
|
.conn $procmux$1039_Y[10] $0\W4[31:0][10]
|
||
|
|
.conn $procmux$1039_Y[11] $0\W4[31:0][11]
|
||
|
|
.conn $procmux$1039_Y[12] $0\W4[31:0][12]
|
||
|
|
.conn $procmux$1039_Y[13] $0\W4[31:0][13]
|
||
|
|
.conn $procmux$1039_Y[14] $0\W4[31:0][14]
|
||
|
|
.conn $procmux$1039_Y[15] $0\W4[31:0][15]
|
||
|
|
.conn $procmux$1039_Y[16] $0\W4[31:0][16]
|
||
|
|
.conn $procmux$1039_Y[17] $0\W4[31:0][17]
|
||
|
|
.conn $procmux$1039_Y[18] $0\W4[31:0][18]
|
||
|
|
.conn $procmux$1039_Y[19] $0\W4[31:0][19]
|
||
|
|
.conn $procmux$1039_Y[20] $0\W4[31:0][20]
|
||
|
|
.conn $procmux$1039_Y[21] $0\W4[31:0][21]
|
||
|
|
.conn $procmux$1039_Y[22] $0\W4[31:0][22]
|
||
|
|
.conn $procmux$1039_Y[23] $0\W4[31:0][23]
|
||
|
|
.conn $procmux$1039_Y[24] $0\W4[31:0][24]
|
||
|
|
.conn $procmux$1039_Y[25] $0\W4[31:0][25]
|
||
|
|
.conn $procmux$1039_Y[26] $0\W4[31:0][26]
|
||
|
|
.conn $procmux$1039_Y[27] $0\W4[31:0][27]
|
||
|
|
.conn $procmux$1039_Y[28] $0\W4[31:0][28]
|
||
|
|
.conn $procmux$1039_Y[29] $0\W4[31:0][29]
|
||
|
|
.conn $procmux$1039_Y[30] $0\W4[31:0][30]
|
||
|
|
.conn $procmux$1039_Y[31] $0\W4[31:0][31]
|
||
|
|
.conn rst_i $procmux$1111_CMP
|
||
|
|
.conn $procmux$1110_Y[0] $0\W3[31:0][0]
|
||
|
|
.conn $procmux$1110_Y[1] $0\W3[31:0][1]
|
||
|
|
.conn $procmux$1110_Y[2] $0\W3[31:0][2]
|
||
|
|
.conn $procmux$1110_Y[3] $0\W3[31:0][3]
|
||
|
|
.conn $procmux$1110_Y[4] $0\W3[31:0][4]
|
||
|
|
.conn $procmux$1110_Y[5] $0\W3[31:0][5]
|
||
|
|
.conn $procmux$1110_Y[6] $0\W3[31:0][6]
|
||
|
|
.conn $procmux$1110_Y[7] $0\W3[31:0][7]
|
||
|
|
.conn $procmux$1110_Y[8] $0\W3[31:0][8]
|
||
|
|
.conn $procmux$1110_Y[9] $0\W3[31:0][9]
|
||
|
|
.conn $procmux$1110_Y[10] $0\W3[31:0][10]
|
||
|
|
.conn $procmux$1110_Y[11] $0\W3[31:0][11]
|
||
|
|
.conn $procmux$1110_Y[12] $0\W3[31:0][12]
|
||
|
|
.conn $procmux$1110_Y[13] $0\W3[31:0][13]
|
||
|
|
.conn $procmux$1110_Y[14] $0\W3[31:0][14]
|
||
|
|
.conn $procmux$1110_Y[15] $0\W3[31:0][15]
|
||
|
|
.conn $procmux$1110_Y[16] $0\W3[31:0][16]
|
||
|
|
.conn $procmux$1110_Y[17] $0\W3[31:0][17]
|
||
|
|
.conn $procmux$1110_Y[18] $0\W3[31:0][18]
|
||
|
|
.conn $procmux$1110_Y[19] $0\W3[31:0][19]
|
||
|
|
.conn $procmux$1110_Y[20] $0\W3[31:0][20]
|
||
|
|
.conn $procmux$1110_Y[21] $0\W3[31:0][21]
|
||
|
|
.conn $procmux$1110_Y[22] $0\W3[31:0][22]
|
||
|
|
.conn $procmux$1110_Y[23] $0\W3[31:0][23]
|
||
|
|
.conn $procmux$1110_Y[24] $0\W3[31:0][24]
|
||
|
|
.conn $procmux$1110_Y[25] $0\W3[31:0][25]
|
||
|
|
.conn $procmux$1110_Y[26] $0\W3[31:0][26]
|
||
|
|
.conn $procmux$1110_Y[27] $0\W3[31:0][27]
|
||
|
|
.conn $procmux$1110_Y[28] $0\W3[31:0][28]
|
||
|
|
.conn $procmux$1110_Y[29] $0\W3[31:0][29]
|
||
|
|
.conn $procmux$1110_Y[30] $0\W3[31:0][30]
|
||
|
|
.conn $procmux$1110_Y[31] $0\W3[31:0][31]
|
||
|
|
.conn rst_i $procmux$1182_CMP
|
||
|
|
.conn $procmux$1181_Y[0] $0\W2[31:0][0]
|
||
|
|
.conn $procmux$1181_Y[1] $0\W2[31:0][1]
|
||
|
|
.conn $procmux$1181_Y[2] $0\W2[31:0][2]
|
||
|
|
.conn $procmux$1181_Y[3] $0\W2[31:0][3]
|
||
|
|
.conn $procmux$1181_Y[4] $0\W2[31:0][4]
|
||
|
|
.conn $procmux$1181_Y[5] $0\W2[31:0][5]
|
||
|
|
.conn $procmux$1181_Y[6] $0\W2[31:0][6]
|
||
|
|
.conn $procmux$1181_Y[7] $0\W2[31:0][7]
|
||
|
|
.conn $procmux$1181_Y[8] $0\W2[31:0][8]
|
||
|
|
.conn $procmux$1181_Y[9] $0\W2[31:0][9]
|
||
|
|
.conn $procmux$1181_Y[10] $0\W2[31:0][10]
|
||
|
|
.conn $procmux$1181_Y[11] $0\W2[31:0][11]
|
||
|
|
.conn $procmux$1181_Y[12] $0\W2[31:0][12]
|
||
|
|
.conn $procmux$1181_Y[13] $0\W2[31:0][13]
|
||
|
|
.conn $procmux$1181_Y[14] $0\W2[31:0][14]
|
||
|
|
.conn $procmux$1181_Y[15] $0\W2[31:0][15]
|
||
|
|
.conn $procmux$1181_Y[16] $0\W2[31:0][16]
|
||
|
|
.conn $procmux$1181_Y[17] $0\W2[31:0][17]
|
||
|
|
.conn $procmux$1181_Y[18] $0\W2[31:0][18]
|
||
|
|
.conn $procmux$1181_Y[19] $0\W2[31:0][19]
|
||
|
|
.conn $procmux$1181_Y[20] $0\W2[31:0][20]
|
||
|
|
.conn $procmux$1181_Y[21] $0\W2[31:0][21]
|
||
|
|
.conn $procmux$1181_Y[22] $0\W2[31:0][22]
|
||
|
|
.conn $procmux$1181_Y[23] $0\W2[31:0][23]
|
||
|
|
.conn $procmux$1181_Y[24] $0\W2[31:0][24]
|
||
|
|
.conn $procmux$1181_Y[25] $0\W2[31:0][25]
|
||
|
|
.conn $procmux$1181_Y[26] $0\W2[31:0][26]
|
||
|
|
.conn $procmux$1181_Y[27] $0\W2[31:0][27]
|
||
|
|
.conn $procmux$1181_Y[28] $0\W2[31:0][28]
|
||
|
|
.conn $procmux$1181_Y[29] $0\W2[31:0][29]
|
||
|
|
.conn $procmux$1181_Y[30] $0\W2[31:0][30]
|
||
|
|
.conn $procmux$1181_Y[31] $0\W2[31:0][31]
|
||
|
|
.conn rst_i $procmux$1253_CMP
|
||
|
|
.conn $procmux$1252_Y[0] $0\W1[31:0][0]
|
||
|
|
.conn $procmux$1252_Y[1] $0\W1[31:0][1]
|
||
|
|
.conn $procmux$1252_Y[2] $0\W1[31:0][2]
|
||
|
|
.conn $procmux$1252_Y[3] $0\W1[31:0][3]
|
||
|
|
.conn $procmux$1252_Y[4] $0\W1[31:0][4]
|
||
|
|
.conn $procmux$1252_Y[5] $0\W1[31:0][5]
|
||
|
|
.conn $procmux$1252_Y[6] $0\W1[31:0][6]
|
||
|
|
.conn $procmux$1252_Y[7] $0\W1[31:0][7]
|
||
|
|
.conn $procmux$1252_Y[8] $0\W1[31:0][8]
|
||
|
|
.conn $procmux$1252_Y[9] $0\W1[31:0][9]
|
||
|
|
.conn $procmux$1252_Y[10] $0\W1[31:0][10]
|
||
|
|
.conn $procmux$1252_Y[11] $0\W1[31:0][11]
|
||
|
|
.conn $procmux$1252_Y[12] $0\W1[31:0][12]
|
||
|
|
.conn $procmux$1252_Y[13] $0\W1[31:0][13]
|
||
|
|
.conn $procmux$1252_Y[14] $0\W1[31:0][14]
|
||
|
|
.conn $procmux$1252_Y[15] $0\W1[31:0][15]
|
||
|
|
.conn $procmux$1252_Y[16] $0\W1[31:0][16]
|
||
|
|
.conn $procmux$1252_Y[17] $0\W1[31:0][17]
|
||
|
|
.conn $procmux$1252_Y[18] $0\W1[31:0][18]
|
||
|
|
.conn $procmux$1252_Y[19] $0\W1[31:0][19]
|
||
|
|
.conn $procmux$1252_Y[20] $0\W1[31:0][20]
|
||
|
|
.conn $procmux$1252_Y[21] $0\W1[31:0][21]
|
||
|
|
.conn $procmux$1252_Y[22] $0\W1[31:0][22]
|
||
|
|
.conn $procmux$1252_Y[23] $0\W1[31:0][23]
|
||
|
|
.conn $procmux$1252_Y[24] $0\W1[31:0][24]
|
||
|
|
.conn $procmux$1252_Y[25] $0\W1[31:0][25]
|
||
|
|
.conn $procmux$1252_Y[26] $0\W1[31:0][26]
|
||
|
|
.conn $procmux$1252_Y[27] $0\W1[31:0][27]
|
||
|
|
.conn $procmux$1252_Y[28] $0\W1[31:0][28]
|
||
|
|
.conn $procmux$1252_Y[29] $0\W1[31:0][29]
|
||
|
|
.conn $procmux$1252_Y[30] $0\W1[31:0][30]
|
||
|
|
.conn $procmux$1252_Y[31] $0\W1[31:0][31]
|
||
|
|
.conn cmd[1] $procmux$1323_CMP
|
||
|
|
.conn rst_i $procmux$1327_CMP
|
||
|
|
.conn $procmux$1326_Y[0] $0\W0[31:0][0]
|
||
|
|
.conn $procmux$1326_Y[1] $0\W0[31:0][1]
|
||
|
|
.conn $procmux$1326_Y[2] $0\W0[31:0][2]
|
||
|
|
.conn $procmux$1326_Y[3] $0\W0[31:0][3]
|
||
|
|
.conn $procmux$1326_Y[4] $0\W0[31:0][4]
|
||
|
|
.conn $procmux$1326_Y[5] $0\W0[31:0][5]
|
||
|
|
.conn $procmux$1326_Y[6] $0\W0[31:0][6]
|
||
|
|
.conn $procmux$1326_Y[7] $0\W0[31:0][7]
|
||
|
|
.conn $procmux$1326_Y[8] $0\W0[31:0][8]
|
||
|
|
.conn $procmux$1326_Y[9] $0\W0[31:0][9]
|
||
|
|
.conn $procmux$1326_Y[10] $0\W0[31:0][10]
|
||
|
|
.conn $procmux$1326_Y[11] $0\W0[31:0][11]
|
||
|
|
.conn $procmux$1326_Y[12] $0\W0[31:0][12]
|
||
|
|
.conn $procmux$1326_Y[13] $0\W0[31:0][13]
|
||
|
|
.conn $procmux$1326_Y[14] $0\W0[31:0][14]
|
||
|
|
.conn $procmux$1326_Y[15] $0\W0[31:0][15]
|
||
|
|
.conn $procmux$1326_Y[16] $0\W0[31:0][16]
|
||
|
|
.conn $procmux$1326_Y[17] $0\W0[31:0][17]
|
||
|
|
.conn $procmux$1326_Y[18] $0\W0[31:0][18]
|
||
|
|
.conn $procmux$1326_Y[19] $0\W0[31:0][19]
|
||
|
|
.conn $procmux$1326_Y[20] $0\W0[31:0][20]
|
||
|
|
.conn $procmux$1326_Y[21] $0\W0[31:0][21]
|
||
|
|
.conn $procmux$1326_Y[22] $0\W0[31:0][22]
|
||
|
|
.conn $procmux$1326_Y[23] $0\W0[31:0][23]
|
||
|
|
.conn $procmux$1326_Y[24] $0\W0[31:0][24]
|
||
|
|
.conn $procmux$1326_Y[25] $0\W0[31:0][25]
|
||
|
|
.conn $procmux$1326_Y[26] $0\W0[31:0][26]
|
||
|
|
.conn $procmux$1326_Y[27] $0\W0[31:0][27]
|
||
|
|
.conn $procmux$1326_Y[28] $0\W0[31:0][28]
|
||
|
|
.conn $procmux$1326_Y[29] $0\W0[31:0][29]
|
||
|
|
.conn $procmux$1326_Y[30] $0\W0[31:0][30]
|
||
|
|
.conn $procmux$1326_Y[31] $0\W0[31:0][31]
|
||
|
|
.conn cmd[2] $procmux$1411_CMP
|
||
|
|
.conn cmd[1] $procmux$1414_CMP
|
||
|
|
.conn rst_i $procmux$1419_CMP
|
||
|
|
.conn $procmux$1418_Y[0] $0\H4[31:0][0]
|
||
|
|
.conn $procmux$1418_Y[1] $0\H4[31:0][1]
|
||
|
|
.conn $procmux$1418_Y[2] $0\H4[31:0][2]
|
||
|
|
.conn $procmux$1418_Y[3] $0\H4[31:0][3]
|
||
|
|
.conn $procmux$1418_Y[4] $0\H4[31:0][4]
|
||
|
|
.conn $procmux$1418_Y[5] $0\H4[31:0][5]
|
||
|
|
.conn $procmux$1418_Y[6] $0\H4[31:0][6]
|
||
|
|
.conn $procmux$1418_Y[7] $0\H4[31:0][7]
|
||
|
|
.conn $procmux$1418_Y[8] $0\H4[31:0][8]
|
||
|
|
.conn $procmux$1418_Y[9] $0\H4[31:0][9]
|
||
|
|
.conn $procmux$1418_Y[10] $0\H4[31:0][10]
|
||
|
|
.conn $procmux$1418_Y[11] $0\H4[31:0][11]
|
||
|
|
.conn $procmux$1418_Y[12] $0\H4[31:0][12]
|
||
|
|
.conn $procmux$1418_Y[13] $0\H4[31:0][13]
|
||
|
|
.conn $procmux$1418_Y[14] $0\H4[31:0][14]
|
||
|
|
.conn $procmux$1418_Y[15] $0\H4[31:0][15]
|
||
|
|
.conn $procmux$1418_Y[16] $0\H4[31:0][16]
|
||
|
|
.conn $procmux$1418_Y[17] $0\H4[31:0][17]
|
||
|
|
.conn $procmux$1418_Y[18] $0\H4[31:0][18]
|
||
|
|
.conn $procmux$1418_Y[19] $0\H4[31:0][19]
|
||
|
|
.conn $procmux$1418_Y[20] $0\H4[31:0][20]
|
||
|
|
.conn $procmux$1418_Y[21] $0\H4[31:0][21]
|
||
|
|
.conn $procmux$1418_Y[22] $0\H4[31:0][22]
|
||
|
|
.conn $procmux$1418_Y[23] $0\H4[31:0][23]
|
||
|
|
.conn $procmux$1418_Y[24] $0\H4[31:0][24]
|
||
|
|
.conn $procmux$1418_Y[25] $0\H4[31:0][25]
|
||
|
|
.conn $procmux$1418_Y[26] $0\H4[31:0][26]
|
||
|
|
.conn $procmux$1418_Y[27] $0\H4[31:0][27]
|
||
|
|
.conn $procmux$1418_Y[28] $0\H4[31:0][28]
|
||
|
|
.conn $procmux$1418_Y[29] $0\H4[31:0][29]
|
||
|
|
.conn $procmux$1418_Y[30] $0\H4[31:0][30]
|
||
|
|
.conn $procmux$1418_Y[31] $0\H4[31:0][31]
|
||
|
|
.conn cmd[2] $procmux$1503_CMP
|
||
|
|
.conn cmd[1] $procmux$1506_CMP
|
||
|
|
.conn rst_i $procmux$1511_CMP
|
||
|
|
.conn $procmux$1510_Y[0] $0\H3[31:0][0]
|
||
|
|
.conn $procmux$1510_Y[1] $0\H3[31:0][1]
|
||
|
|
.conn $procmux$1510_Y[2] $0\H3[31:0][2]
|
||
|
|
.conn $procmux$1510_Y[3] $0\H3[31:0][3]
|
||
|
|
.conn $procmux$1510_Y[4] $0\H3[31:0][4]
|
||
|
|
.conn $procmux$1510_Y[5] $0\H3[31:0][5]
|
||
|
|
.conn $procmux$1510_Y[6] $0\H3[31:0][6]
|
||
|
|
.conn $procmux$1510_Y[7] $0\H3[31:0][7]
|
||
|
|
.conn $procmux$1510_Y[8] $0\H3[31:0][8]
|
||
|
|
.conn $procmux$1510_Y[9] $0\H3[31:0][9]
|
||
|
|
.conn $procmux$1510_Y[10] $0\H3[31:0][10]
|
||
|
|
.conn $procmux$1510_Y[11] $0\H3[31:0][11]
|
||
|
|
.conn $procmux$1510_Y[12] $0\H3[31:0][12]
|
||
|
|
.conn $procmux$1510_Y[13] $0\H3[31:0][13]
|
||
|
|
.conn $procmux$1510_Y[14] $0\H3[31:0][14]
|
||
|
|
.conn $procmux$1510_Y[15] $0\H3[31:0][15]
|
||
|
|
.conn $procmux$1510_Y[16] $0\H3[31:0][16]
|
||
|
|
.conn $procmux$1510_Y[17] $0\H3[31:0][17]
|
||
|
|
.conn $procmux$1510_Y[18] $0\H3[31:0][18]
|
||
|
|
.conn $procmux$1510_Y[19] $0\H3[31:0][19]
|
||
|
|
.conn $procmux$1510_Y[20] $0\H3[31:0][20]
|
||
|
|
.conn $procmux$1510_Y[21] $0\H3[31:0][21]
|
||
|
|
.conn $procmux$1510_Y[22] $0\H3[31:0][22]
|
||
|
|
.conn $procmux$1510_Y[23] $0\H3[31:0][23]
|
||
|
|
.conn $procmux$1510_Y[24] $0\H3[31:0][24]
|
||
|
|
.conn $procmux$1510_Y[25] $0\H3[31:0][25]
|
||
|
|
.conn $procmux$1510_Y[26] $0\H3[31:0][26]
|
||
|
|
.conn $procmux$1510_Y[27] $0\H3[31:0][27]
|
||
|
|
.conn $procmux$1510_Y[28] $0\H3[31:0][28]
|
||
|
|
.conn $procmux$1510_Y[29] $0\H3[31:0][29]
|
||
|
|
.conn $procmux$1510_Y[30] $0\H3[31:0][30]
|
||
|
|
.conn $procmux$1510_Y[31] $0\H3[31:0][31]
|
||
|
|
.conn cmd[2] $procmux$1595_CMP
|
||
|
|
.conn cmd[1] $procmux$1598_CMP
|
||
|
|
.conn rst_i $procmux$1603_CMP
|
||
|
|
.conn $procmux$1602_Y[0] $0\H2[31:0][0]
|
||
|
|
.conn $procmux$1602_Y[1] $0\H2[31:0][1]
|
||
|
|
.conn $procmux$1602_Y[2] $0\H2[31:0][2]
|
||
|
|
.conn $procmux$1602_Y[3] $0\H2[31:0][3]
|
||
|
|
.conn $procmux$1602_Y[4] $0\H2[31:0][4]
|
||
|
|
.conn $procmux$1602_Y[5] $0\H2[31:0][5]
|
||
|
|
.conn $procmux$1602_Y[6] $0\H2[31:0][6]
|
||
|
|
.conn $procmux$1602_Y[7] $0\H2[31:0][7]
|
||
|
|
.conn $procmux$1602_Y[8] $0\H2[31:0][8]
|
||
|
|
.conn $procmux$1602_Y[9] $0\H2[31:0][9]
|
||
|
|
.conn $procmux$1602_Y[10] $0\H2[31:0][10]
|
||
|
|
.conn $procmux$1602_Y[11] $0\H2[31:0][11]
|
||
|
|
.conn $procmux$1602_Y[12] $0\H2[31:0][12]
|
||
|
|
.conn $procmux$1602_Y[13] $0\H2[31:0][13]
|
||
|
|
.conn $procmux$1602_Y[14] $0\H2[31:0][14]
|
||
|
|
.conn $procmux$1602_Y[15] $0\H2[31:0][15]
|
||
|
|
.conn $procmux$1602_Y[16] $0\H2[31:0][16]
|
||
|
|
.conn $procmux$1602_Y[17] $0\H2[31:0][17]
|
||
|
|
.conn $procmux$1602_Y[18] $0\H2[31:0][18]
|
||
|
|
.conn $procmux$1602_Y[19] $0\H2[31:0][19]
|
||
|
|
.conn $procmux$1602_Y[20] $0\H2[31:0][20]
|
||
|
|
.conn $procmux$1602_Y[21] $0\H2[31:0][21]
|
||
|
|
.conn $procmux$1602_Y[22] $0\H2[31:0][22]
|
||
|
|
.conn $procmux$1602_Y[23] $0\H2[31:0][23]
|
||
|
|
.conn $procmux$1602_Y[24] $0\H2[31:0][24]
|
||
|
|
.conn $procmux$1602_Y[25] $0\H2[31:0][25]
|
||
|
|
.conn $procmux$1602_Y[26] $0\H2[31:0][26]
|
||
|
|
.conn $procmux$1602_Y[27] $0\H2[31:0][27]
|
||
|
|
.conn $procmux$1602_Y[28] $0\H2[31:0][28]
|
||
|
|
.conn $procmux$1602_Y[29] $0\H2[31:0][29]
|
||
|
|
.conn $procmux$1602_Y[30] $0\H2[31:0][30]
|
||
|
|
.conn $procmux$1602_Y[31] $0\H2[31:0][31]
|
||
|
|
.conn cmd[2] $procmux$1687_CMP
|
||
|
|
.conn cmd[1] $procmux$1690_CMP
|
||
|
|
.conn rst_i $procmux$1695_CMP
|
||
|
|
.conn $procmux$1694_Y[0] $0\H1[31:0][0]
|
||
|
|
.conn $procmux$1694_Y[1] $0\H1[31:0][1]
|
||
|
|
.conn $procmux$1694_Y[2] $0\H1[31:0][2]
|
||
|
|
.conn $procmux$1694_Y[3] $0\H1[31:0][3]
|
||
|
|
.conn $procmux$1694_Y[4] $0\H1[31:0][4]
|
||
|
|
.conn $procmux$1694_Y[5] $0\H1[31:0][5]
|
||
|
|
.conn $procmux$1694_Y[6] $0\H1[31:0][6]
|
||
|
|
.conn $procmux$1694_Y[7] $0\H1[31:0][7]
|
||
|
|
.conn $procmux$1694_Y[8] $0\H1[31:0][8]
|
||
|
|
.conn $procmux$1694_Y[9] $0\H1[31:0][9]
|
||
|
|
.conn $procmux$1694_Y[10] $0\H1[31:0][10]
|
||
|
|
.conn $procmux$1694_Y[11] $0\H1[31:0][11]
|
||
|
|
.conn $procmux$1694_Y[12] $0\H1[31:0][12]
|
||
|
|
.conn $procmux$1694_Y[13] $0\H1[31:0][13]
|
||
|
|
.conn $procmux$1694_Y[14] $0\H1[31:0][14]
|
||
|
|
.conn $procmux$1694_Y[15] $0\H1[31:0][15]
|
||
|
|
.conn $procmux$1694_Y[16] $0\H1[31:0][16]
|
||
|
|
.conn $procmux$1694_Y[17] $0\H1[31:0][17]
|
||
|
|
.conn $procmux$1694_Y[18] $0\H1[31:0][18]
|
||
|
|
.conn $procmux$1694_Y[19] $0\H1[31:0][19]
|
||
|
|
.conn $procmux$1694_Y[20] $0\H1[31:0][20]
|
||
|
|
.conn $procmux$1694_Y[21] $0\H1[31:0][21]
|
||
|
|
.conn $procmux$1694_Y[22] $0\H1[31:0][22]
|
||
|
|
.conn $procmux$1694_Y[23] $0\H1[31:0][23]
|
||
|
|
.conn $procmux$1694_Y[24] $0\H1[31:0][24]
|
||
|
|
.conn $procmux$1694_Y[25] $0\H1[31:0][25]
|
||
|
|
.conn $procmux$1694_Y[26] $0\H1[31:0][26]
|
||
|
|
.conn $procmux$1694_Y[27] $0\H1[31:0][27]
|
||
|
|
.conn $procmux$1694_Y[28] $0\H1[31:0][28]
|
||
|
|
.conn $procmux$1694_Y[29] $0\H1[31:0][29]
|
||
|
|
.conn $procmux$1694_Y[30] $0\H1[31:0][30]
|
||
|
|
.conn $procmux$1694_Y[31] $0\H1[31:0][31]
|
||
|
|
.conn cmd[2] $procmux$1779_CMP
|
||
|
|
.conn cmd[1] $procmux$1782_CMP
|
||
|
|
.conn rst_i $procmux$1787_CMP
|
||
|
|
.conn $procmux$1786_Y[0] $0\H0[31:0][0]
|
||
|
|
.conn $procmux$1786_Y[1] $0\H0[31:0][1]
|
||
|
|
.conn $procmux$1786_Y[2] $0\H0[31:0][2]
|
||
|
|
.conn $procmux$1786_Y[3] $0\H0[31:0][3]
|
||
|
|
.conn $procmux$1786_Y[4] $0\H0[31:0][4]
|
||
|
|
.conn $procmux$1786_Y[5] $0\H0[31:0][5]
|
||
|
|
.conn $procmux$1786_Y[6] $0\H0[31:0][6]
|
||
|
|
.conn $procmux$1786_Y[7] $0\H0[31:0][7]
|
||
|
|
.conn $procmux$1786_Y[8] $0\H0[31:0][8]
|
||
|
|
.conn $procmux$1786_Y[9] $0\H0[31:0][9]
|
||
|
|
.conn $procmux$1786_Y[10] $0\H0[31:0][10]
|
||
|
|
.conn $procmux$1786_Y[11] $0\H0[31:0][11]
|
||
|
|
.conn $procmux$1786_Y[12] $0\H0[31:0][12]
|
||
|
|
.conn $procmux$1786_Y[13] $0\H0[31:0][13]
|
||
|
|
.conn $procmux$1786_Y[14] $0\H0[31:0][14]
|
||
|
|
.conn $procmux$1786_Y[15] $0\H0[31:0][15]
|
||
|
|
.conn $procmux$1786_Y[16] $0\H0[31:0][16]
|
||
|
|
.conn $procmux$1786_Y[17] $0\H0[31:0][17]
|
||
|
|
.conn $procmux$1786_Y[18] $0\H0[31:0][18]
|
||
|
|
.conn $procmux$1786_Y[19] $0\H0[31:0][19]
|
||
|
|
.conn $procmux$1786_Y[20] $0\H0[31:0][20]
|
||
|
|
.conn $procmux$1786_Y[21] $0\H0[31:0][21]
|
||
|
|
.conn $procmux$1786_Y[22] $0\H0[31:0][22]
|
||
|
|
.conn $procmux$1786_Y[23] $0\H0[31:0][23]
|
||
|
|
.conn $procmux$1786_Y[24] $0\H0[31:0][24]
|
||
|
|
.conn $procmux$1786_Y[25] $0\H0[31:0][25]
|
||
|
|
.conn $procmux$1786_Y[26] $0\H0[31:0][26]
|
||
|
|
.conn $procmux$1786_Y[27] $0\H0[31:0][27]
|
||
|
|
.conn $procmux$1786_Y[28] $0\H0[31:0][28]
|
||
|
|
.conn $procmux$1786_Y[29] $0\H0[31:0][29]
|
||
|
|
.conn $procmux$1786_Y[30] $0\H0[31:0][30]
|
||
|
|
.conn $procmux$1786_Y[31] $0\H0[31:0][31]
|
||
|
|
.conn cmd[1] $procmux$1872_CMP
|
||
|
|
.conn rst_i $procmux$1876_CMP
|
||
|
|
.conn $procmux$1875_Y[0] $0\round[6:0][0]
|
||
|
|
.conn $procmux$1875_Y[1] $0\round[6:0][1]
|
||
|
|
.conn $procmux$1875_Y[2] $0\round[6:0][2]
|
||
|
|
.conn $procmux$1875_Y[3] $0\round[6:0][3]
|
||
|
|
.conn $procmux$1875_Y[4] $0\round[6:0][4]
|
||
|
|
.conn $procmux$1875_Y[5] $0\round[6:0][5]
|
||
|
|
.conn $procmux$1875_Y[6] $0\round[6:0][6]
|
||
|
|
.conn cmd[1] $procmux$1964_CMP
|
||
|
|
.conn rst_i $procmux$1968_CMP
|
||
|
|
.conn $procmux$1967_Y[0] $0\E[31:0][0]
|
||
|
|
.conn $procmux$1967_Y[1] $0\E[31:0][1]
|
||
|
|
.conn $procmux$1967_Y[2] $0\E[31:0][2]
|
||
|
|
.conn $procmux$1967_Y[3] $0\E[31:0][3]
|
||
|
|
.conn $procmux$1967_Y[4] $0\E[31:0][4]
|
||
|
|
.conn $procmux$1967_Y[5] $0\E[31:0][5]
|
||
|
|
.conn $procmux$1967_Y[6] $0\E[31:0][6]
|
||
|
|
.conn $procmux$1967_Y[7] $0\E[31:0][7]
|
||
|
|
.conn $procmux$1967_Y[8] $0\E[31:0][8]
|
||
|
|
.conn $procmux$1967_Y[9] $0\E[31:0][9]
|
||
|
|
.conn $procmux$1967_Y[10] $0\E[31:0][10]
|
||
|
|
.conn $procmux$1967_Y[11] $0\E[31:0][11]
|
||
|
|
.conn $procmux$1967_Y[12] $0\E[31:0][12]
|
||
|
|
.conn $procmux$1967_Y[13] $0\E[31:0][13]
|
||
|
|
.conn $procmux$1967_Y[14] $0\E[31:0][14]
|
||
|
|
.conn $procmux$1967_Y[15] $0\E[31:0][15]
|
||
|
|
.conn $procmux$1967_Y[16] $0\E[31:0][16]
|
||
|
|
.conn $procmux$1967_Y[17] $0\E[31:0][17]
|
||
|
|
.conn $procmux$1967_Y[18] $0\E[31:0][18]
|
||
|
|
.conn $procmux$1967_Y[19] $0\E[31:0][19]
|
||
|
|
.conn $procmux$1967_Y[20] $0\E[31:0][20]
|
||
|
|
.conn $procmux$1967_Y[21] $0\E[31:0][21]
|
||
|
|
.conn $procmux$1967_Y[22] $0\E[31:0][22]
|
||
|
|
.conn $procmux$1967_Y[23] $0\E[31:0][23]
|
||
|
|
.conn $procmux$1967_Y[24] $0\E[31:0][24]
|
||
|
|
.conn $procmux$1967_Y[25] $0\E[31:0][25]
|
||
|
|
.conn $procmux$1967_Y[26] $0\E[31:0][26]
|
||
|
|
.conn $procmux$1967_Y[27] $0\E[31:0][27]
|
||
|
|
.conn $procmux$1967_Y[28] $0\E[31:0][28]
|
||
|
|
.conn $procmux$1967_Y[29] $0\E[31:0][29]
|
||
|
|
.conn $procmux$1967_Y[30] $0\E[31:0][30]
|
||
|
|
.conn $procmux$1967_Y[31] $0\E[31:0][31]
|
||
|
|
.conn cmd[1] $procmux$2056_CMP
|
||
|
|
.conn rst_i $procmux$2060_CMP
|
||
|
|
.conn $procmux$2059_Y[0] $0\D[31:0][0]
|
||
|
|
.conn $procmux$2059_Y[1] $0\D[31:0][1]
|
||
|
|
.conn $procmux$2059_Y[2] $0\D[31:0][2]
|
||
|
|
.conn $procmux$2059_Y[3] $0\D[31:0][3]
|
||
|
|
.conn $procmux$2059_Y[4] $0\D[31:0][4]
|
||
|
|
.conn $procmux$2059_Y[5] $0\D[31:0][5]
|
||
|
|
.conn $procmux$2059_Y[6] $0\D[31:0][6]
|
||
|
|
.conn $procmux$2059_Y[7] $0\D[31:0][7]
|
||
|
|
.conn $procmux$2059_Y[8] $0\D[31:0][8]
|
||
|
|
.conn $procmux$2059_Y[9] $0\D[31:0][9]
|
||
|
|
.conn $procmux$2059_Y[10] $0\D[31:0][10]
|
||
|
|
.conn $procmux$2059_Y[11] $0\D[31:0][11]
|
||
|
|
.conn $procmux$2059_Y[12] $0\D[31:0][12]
|
||
|
|
.conn $procmux$2059_Y[13] $0\D[31:0][13]
|
||
|
|
.conn $procmux$2059_Y[14] $0\D[31:0][14]
|
||
|
|
.conn $procmux$2059_Y[15] $0\D[31:0][15]
|
||
|
|
.conn $procmux$2059_Y[16] $0\D[31:0][16]
|
||
|
|
.conn $procmux$2059_Y[17] $0\D[31:0][17]
|
||
|
|
.conn $procmux$2059_Y[18] $0\D[31:0][18]
|
||
|
|
.conn $procmux$2059_Y[19] $0\D[31:0][19]
|
||
|
|
.conn $procmux$2059_Y[20] $0\D[31:0][20]
|
||
|
|
.conn $procmux$2059_Y[21] $0\D[31:0][21]
|
||
|
|
.conn $procmux$2059_Y[22] $0\D[31:0][22]
|
||
|
|
.conn $procmux$2059_Y[23] $0\D[31:0][23]
|
||
|
|
.conn $procmux$2059_Y[24] $0\D[31:0][24]
|
||
|
|
.conn $procmux$2059_Y[25] $0\D[31:0][25]
|
||
|
|
.conn $procmux$2059_Y[26] $0\D[31:0][26]
|
||
|
|
.conn $procmux$2059_Y[27] $0\D[31:0][27]
|
||
|
|
.conn $procmux$2059_Y[28] $0\D[31:0][28]
|
||
|
|
.conn $procmux$2059_Y[29] $0\D[31:0][29]
|
||
|
|
.conn $procmux$2059_Y[30] $0\D[31:0][30]
|
||
|
|
.conn $procmux$2059_Y[31] $0\D[31:0][31]
|
||
|
|
.conn cmd[1] $procmux$2148_CMP
|
||
|
|
.conn rst_i $procmux$2152_CMP
|
||
|
|
.conn $procmux$2151_Y[0] $0\C[31:0][0]
|
||
|
|
.conn $procmux$2151_Y[1] $0\C[31:0][1]
|
||
|
|
.conn $procmux$2151_Y[2] $0\C[31:0][2]
|
||
|
|
.conn $procmux$2151_Y[3] $0\C[31:0][3]
|
||
|
|
.conn $procmux$2151_Y[4] $0\C[31:0][4]
|
||
|
|
.conn $procmux$2151_Y[5] $0\C[31:0][5]
|
||
|
|
.conn $procmux$2151_Y[6] $0\C[31:0][6]
|
||
|
|
.conn $procmux$2151_Y[7] $0\C[31:0][7]
|
||
|
|
.conn $procmux$2151_Y[8] $0\C[31:0][8]
|
||
|
|
.conn $procmux$2151_Y[9] $0\C[31:0][9]
|
||
|
|
.conn $procmux$2151_Y[10] $0\C[31:0][10]
|
||
|
|
.conn $procmux$2151_Y[11] $0\C[31:0][11]
|
||
|
|
.conn $procmux$2151_Y[12] $0\C[31:0][12]
|
||
|
|
.conn $procmux$2151_Y[13] $0\C[31:0][13]
|
||
|
|
.conn $procmux$2151_Y[14] $0\C[31:0][14]
|
||
|
|
.conn $procmux$2151_Y[15] $0\C[31:0][15]
|
||
|
|
.conn $procmux$2151_Y[16] $0\C[31:0][16]
|
||
|
|
.conn $procmux$2151_Y[17] $0\C[31:0][17]
|
||
|
|
.conn $procmux$2151_Y[18] $0\C[31:0][18]
|
||
|
|
.conn $procmux$2151_Y[19] $0\C[31:0][19]
|
||
|
|
.conn $procmux$2151_Y[20] $0\C[31:0][20]
|
||
|
|
.conn $procmux$2151_Y[21] $0\C[31:0][21]
|
||
|
|
.conn $procmux$2151_Y[22] $0\C[31:0][22]
|
||
|
|
.conn $procmux$2151_Y[23] $0\C[31:0][23]
|
||
|
|
.conn $procmux$2151_Y[24] $0\C[31:0][24]
|
||
|
|
.conn $procmux$2151_Y[25] $0\C[31:0][25]
|
||
|
|
.conn $procmux$2151_Y[26] $0\C[31:0][26]
|
||
|
|
.conn $procmux$2151_Y[27] $0\C[31:0][27]
|
||
|
|
.conn $procmux$2151_Y[28] $0\C[31:0][28]
|
||
|
|
.conn $procmux$2151_Y[29] $0\C[31:0][29]
|
||
|
|
.conn $procmux$2151_Y[30] $0\C[31:0][30]
|
||
|
|
.conn $procmux$2151_Y[31] $0\C[31:0][31]
|
||
|
|
.conn cmd[1] $procmux$2240_CMP
|
||
|
|
.conn rst_i $procmux$2244_CMP
|
||
|
|
.conn $procmux$2243_Y[0] $0\B[31:0][0]
|
||
|
|
.conn $procmux$2243_Y[1] $0\B[31:0][1]
|
||
|
|
.conn $procmux$2243_Y[2] $0\B[31:0][2]
|
||
|
|
.conn $procmux$2243_Y[3] $0\B[31:0][3]
|
||
|
|
.conn $procmux$2243_Y[4] $0\B[31:0][4]
|
||
|
|
.conn $procmux$2243_Y[5] $0\B[31:0][5]
|
||
|
|
.conn $procmux$2243_Y[6] $0\B[31:0][6]
|
||
|
|
.conn $procmux$2243_Y[7] $0\B[31:0][7]
|
||
|
|
.conn $procmux$2243_Y[8] $0\B[31:0][8]
|
||
|
|
.conn $procmux$2243_Y[9] $0\B[31:0][9]
|
||
|
|
.conn $procmux$2243_Y[10] $0\B[31:0][10]
|
||
|
|
.conn $procmux$2243_Y[11] $0\B[31:0][11]
|
||
|
|
.conn $procmux$2243_Y[12] $0\B[31:0][12]
|
||
|
|
.conn $procmux$2243_Y[13] $0\B[31:0][13]
|
||
|
|
.conn $procmux$2243_Y[14] $0\B[31:0][14]
|
||
|
|
.conn $procmux$2243_Y[15] $0\B[31:0][15]
|
||
|
|
.conn $procmux$2243_Y[16] $0\B[31:0][16]
|
||
|
|
.conn $procmux$2243_Y[17] $0\B[31:0][17]
|
||
|
|
.conn $procmux$2243_Y[18] $0\B[31:0][18]
|
||
|
|
.conn $procmux$2243_Y[19] $0\B[31:0][19]
|
||
|
|
.conn $procmux$2243_Y[20] $0\B[31:0][20]
|
||
|
|
.conn $procmux$2243_Y[21] $0\B[31:0][21]
|
||
|
|
.conn $procmux$2243_Y[22] $0\B[31:0][22]
|
||
|
|
.conn $procmux$2243_Y[23] $0\B[31:0][23]
|
||
|
|
.conn $procmux$2243_Y[24] $0\B[31:0][24]
|
||
|
|
.conn $procmux$2243_Y[25] $0\B[31:0][25]
|
||
|
|
.conn $procmux$2243_Y[26] $0\B[31:0][26]
|
||
|
|
.conn $procmux$2243_Y[27] $0\B[31:0][27]
|
||
|
|
.conn $procmux$2243_Y[28] $0\B[31:0][28]
|
||
|
|
.conn $procmux$2243_Y[29] $0\B[31:0][29]
|
||
|
|
.conn $procmux$2243_Y[30] $0\B[31:0][30]
|
||
|
|
.conn $procmux$2243_Y[31] $0\B[31:0][31]
|
||
|
|
.conn cmd[1] $procmux$2332_CMP
|
||
|
|
.conn rst_i $procmux$2336_CMP
|
||
|
|
.conn $procmux$2335_Y[0] $0\A[31:0][0]
|
||
|
|
.conn $procmux$2335_Y[1] $0\A[31:0][1]
|
||
|
|
.conn $procmux$2335_Y[2] $0\A[31:0][2]
|
||
|
|
.conn $procmux$2335_Y[3] $0\A[31:0][3]
|
||
|
|
.conn $procmux$2335_Y[4] $0\A[31:0][4]
|
||
|
|
.conn $procmux$2335_Y[5] $0\A[31:0][5]
|
||
|
|
.conn $procmux$2335_Y[6] $0\A[31:0][6]
|
||
|
|
.conn $procmux$2335_Y[7] $0\A[31:0][7]
|
||
|
|
.conn $procmux$2335_Y[8] $0\A[31:0][8]
|
||
|
|
.conn $procmux$2335_Y[9] $0\A[31:0][9]
|
||
|
|
.conn $procmux$2335_Y[10] $0\A[31:0][10]
|
||
|
|
.conn $procmux$2335_Y[11] $0\A[31:0][11]
|
||
|
|
.conn $procmux$2335_Y[12] $0\A[31:0][12]
|
||
|
|
.conn $procmux$2335_Y[13] $0\A[31:0][13]
|
||
|
|
.conn $procmux$2335_Y[14] $0\A[31:0][14]
|
||
|
|
.conn $procmux$2335_Y[15] $0\A[31:0][15]
|
||
|
|
.conn $procmux$2335_Y[16] $0\A[31:0][16]
|
||
|
|
.conn $procmux$2335_Y[17] $0\A[31:0][17]
|
||
|
|
.conn $procmux$2335_Y[18] $0\A[31:0][18]
|
||
|
|
.conn $procmux$2335_Y[19] $0\A[31:0][19]
|
||
|
|
.conn $procmux$2335_Y[20] $0\A[31:0][20]
|
||
|
|
.conn $procmux$2335_Y[21] $0\A[31:0][21]
|
||
|
|
.conn $procmux$2335_Y[22] $0\A[31:0][22]
|
||
|
|
.conn $procmux$2335_Y[23] $0\A[31:0][23]
|
||
|
|
.conn $procmux$2335_Y[24] $0\A[31:0][24]
|
||
|
|
.conn $procmux$2335_Y[25] $0\A[31:0][25]
|
||
|
|
.conn $procmux$2335_Y[26] $0\A[31:0][26]
|
||
|
|
.conn $procmux$2335_Y[27] $0\A[31:0][27]
|
||
|
|
.conn $procmux$2335_Y[28] $0\A[31:0][28]
|
||
|
|
.conn $procmux$2335_Y[29] $0\A[31:0][29]
|
||
|
|
.conn $procmux$2335_Y[30] $0\A[31:0][30]
|
||
|
|
.conn $procmux$2335_Y[31] $0\A[31:0][31]
|
||
|
|
.conn cmd_w_i $procmux$2339_CMP
|
||
|
|
.conn rst_i $procmux$2342_CMP
|
||
|
|
.conn $procmux$2341_Y $0\cmd[3:0][2]
|
||
|
|
.conn $not$/project/trees/vtr/vtr_flow/benchmarks/verilog/sha.v:116$2_Y $procmux$2345_CMP
|
||
|
|
.conn cmd_w_i $procmux$2348_CMP
|
||
|
|
.conn rst_i $procmux$2351_CMP
|
||
|
|
.conn $procmux$2350_Y[0] $0\cmd[3:0][0]
|
||
|
|
.conn $procmux$2350_Y[1] $0\cmd[3:0][1]
|
||
|
|
.conn cmd_w_i $procmux$2354_CMP
|
||
|
|
.conn rst_i $procmux$2357_CMP
|
||
|
|
.conn $procmux$2356_Y $0\cmd[3:0][3]
|
||
|
|
.end
|