2021-04-16 21:00:30 -05:00
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# Yosys synthesis script for ${TOP_MODULE}
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# Read verilog files
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${READ_VERILOG_FILE}
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# Read technology library
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read_verilog -lib -specify ${YOSYS_CELL_SIM_VERILOG}
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# Technology mapping
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hierarchy -top ${TOP_MODULE}
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proc
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techmap -D NO_LUT -map ${YOSYS_DFF_MAP_VERILOG}
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# Synthesis
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2021-10-30 17:12:34 -05:00
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flatten
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2021-10-30 16:56:54 -05:00
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opt_expr
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opt_clean
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check
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opt -nodffe -nosdff
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fsm
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opt -nodffe -nosdff
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wreduce
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peepopt
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opt_clean
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opt -nodffe -nosdff
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memory -nomap
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opt_clean
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opt -fast -full -nodffe -nosdff
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memory_map
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opt -full -nodffe -nosdff
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techmap
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opt -fast -nodffe -nosdff
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2021-04-16 21:00:30 -05:00
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clean
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# LUT mapping
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abc -lut ${LUT_SIZE}
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2021-04-16 21:47:18 -05:00
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# FF mapping
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techmap -D NO_LUT -map ${YOSYS_DFF_MAP_VERILOG}
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2021-04-16 21:00:30 -05:00
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# Check
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synth -run check
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# Clean and output blif
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opt_clean -purge
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write_blif ${OUTPUT_BLIF}
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