236 lines
10 KiB
XML
236 lines
10 KiB
XML
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<architecture>
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<models/>
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<tiles>
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<tile name="io" capacity="8">
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<equivalent_sites>
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<site pb_type="io"/>
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</equivalent_sites>
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<input name="outpad" num_pins="1"/>
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<output name="inpad" num_pins="1"/>
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<clock name="clock" num_pins="1"/>
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<fc in_type="frac" in_val="0.15" out_type="frac" out_val="0.10"/>
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<pinlocations pattern="custom">
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<loc side="left">io.outpad io.inpad io.clock</loc>
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<loc side="top">io.outpad io.inpad io.clock</loc>
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<loc side="right">io.outpad io.inpad io.clock</loc>
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<loc side="bottom">io.outpad io.inpad io.clock</loc>
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</pinlocations>
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</tile>
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<tile name="clb">
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<equivalent_sites>
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<site pb_type="clb"/>
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</equivalent_sites>
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<input name="I" num_pins="33" equivalent="full"/>
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<output name="O" num_pins="20" equivalent="none"/>
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<clock name="clk" num_pins="1"/>
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<fc in_type="frac" in_val="0.15" out_type="frac" out_val="0.10"/>
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<pinlocations pattern="spread"/>
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</tile>
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</tiles>
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<layout>
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<auto_layout aspect_ratio="1.0">
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<perimeter type="io" priority="100">
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<metadata>
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<meta name="type">io</meta>
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</metadata>
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</perimeter>
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<single type="clb" priority="1" x="5" y="5">
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<metadata>
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<meta name="single">clb</meta>
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</metadata>
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</single>
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<corners type="EMPTY" priority="101"/>
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<fill type="clb" priority="10"/>
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<col type="EMPTY" startx="6" repeatx="8" starty="1" priority="19"/>
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<col type="EMPTY" startx="2" repeatx="8" starty="1" priority="19"/>
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</auto_layout>
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</layout>
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<device>
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<sizing R_minW_nmos="8926" R_minW_pmos="16067"/>
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<area grid_logic_tile_area="53894"/>
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<chan_width_distr>
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<x distr="uniform" peak="1.000000"/>
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<y distr="uniform" peak="1.000000"/>
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</chan_width_distr>
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<switch_block type="wilton" fs="3"/>
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<connection_block input_switch_name="ipin_cblock"/>
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</device>
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<switchlist>
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<switch type="mux" name="0" R="551" Cin=".77e-15" Cout="4e-15" Tdel="58e-12" mux_trans_size="2.630740" buf_size="27.645901"/>
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<switch type="mux" name="ipin_cblock" R="2231.5" Cout="0." Cin="1.47e-15" Tdel="7.247000e-11" mux_trans_size="1.222260" buf_size="auto"/>
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</switchlist>
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<segmentlist>
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<segment freq="1.000000" length="4" type="unidir" Rmetal="101" Cmetal="22.5e-15">
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<mux name="0"/>
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<sb type="pattern">1 1 1 1 1</sb>
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<cb type="pattern">1 1 1 1</cb>
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</segment>
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</segmentlist>
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<complexblocklist>
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<pb_type name="io">
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<metadata>
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<meta name="pb_type_type">pb_type = io</meta>
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</metadata>
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<input name="outpad" num_pins="1"/>
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<output name="inpad" num_pins="1"/>
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<clock name="clock" num_pins="1"/>
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<mode name="inpad">
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<metadata>
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<meta name="mode">inpad</meta>
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</metadata>
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<pb_type name="inpad" blif_model=".input" num_pb="1">
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<output name="inpad" num_pins="1"/>
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</pb_type>
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<interconnect>
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<direct name="inpad" input="inpad.inpad" output="io.inpad">
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<delay_constant max="4.243e-11" in_port="inpad.inpad" out_port="io.inpad"/>
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<metadata>
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<meta name="interconnect">inpad_iconnect</meta>
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</metadata>
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</direct>
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</interconnect>
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</mode>
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<mode name="outpad">
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<pb_type name="outpad" blif_model=".output" num_pb="1">
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<input name="outpad" num_pins="1"/>
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</pb_type>
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<interconnect>
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<direct name="outpad" input="io.outpad" output="outpad.outpad">
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<delay_constant max="1.394e-11" in_port="io.outpad" out_port="outpad.outpad"/>
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</direct>
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</interconnect>
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</mode>
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<!-- Every input pin is driven by 15% of the tracks in a channel, every output pin is driven by 10% of the tracks in a channel -->
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<!-- IOs go on the periphery of the FPGA, for consistency,
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make it physically equivalent on all sides so that only one definition of I/Os is needed.
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If I do not make a physically equivalent definition, then I need to define 4 different I/Os, one for each side of the FPGA
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-->
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<!-- Place I/Os on the sides of the FPGA -->
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<power method="ignore"/>
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</pb_type>
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<pb_type name="clb">
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<input name="I" num_pins="33" equivalent="full"/>
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<output name="O" num_pins="20" equivalent="none"/>
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<clock name="clk" num_pins="1"/>
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<pb_type name="fle" num_pb="10">
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<input name="in" num_pins="6"/>
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<output name="out" num_pins="2"/>
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<clock name="clk" num_pins="1"/>
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<mode name="n2_lut5">
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<pb_type name="lut5inter" num_pb="1">
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<input name="in" num_pins="5"/>
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<output name="out" num_pins="2"/>
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<clock name="clk" num_pins="1"/>
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<pb_type name="ble5" num_pb="2">
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<input name="in" num_pins="5"/>
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<output name="out" num_pins="1"/>
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<clock name="clk" num_pins="1"/>
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<pb_type name="lut5" blif_model=".names" num_pb="1" class="lut">
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<input name="in" num_pins="5" port_class="lut_in"/>
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<output name="out" num_pins="1" port_class="lut_out"/>
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<delay_matrix type="max" in_port="lut5.in" out_port="lut5.out">
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235e-12
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235e-12
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235e-12
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235e-12
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235e-12
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</delay_matrix>
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</pb_type>
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<pb_type name="ff" blif_model=".latch" num_pb="1" class="flipflop">
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<input name="D" num_pins="1" port_class="D"/>
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<output name="Q" num_pins="1" port_class="Q"/>
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<clock name="clk" num_pins="1" port_class="clock"/>
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<T_setup value="66e-12" port="ff.D" clock="clk"/>
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<T_clock_to_Q max="124e-12" port="ff.Q" clock="clk"/>
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</pb_type>
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<interconnect>
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<direct name="direct1" input="ble5.in[4:0]" output="lut5[0:0].in[4:0]"/>
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<direct name="direct2" input="lut5[0:0].out" output="ff[0:0].D">
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<!-- Advanced user option that tells CAD tool to find LUT+FF pairs in netlist -->
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<pack_pattern name="ble5" in_port="lut5[0:0].out" out_port="ff[0:0].D"/>
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</direct>
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<direct name="direct3" input="ble5.clk" output="ff[0:0].clk"/>
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<mux name="mux1" input="ff[0:0].Q lut5.out[0:0]" output="ble5.out[0:0]">
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<!-- LUT to output is faster than FF to output on a Stratix IV -->
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<delay_constant max="25e-12" in_port="lut5.out[0:0]" out_port="ble5.out[0:0]"/>
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<delay_constant max="45e-12" in_port="ff[0:0].Q" out_port="ble5.out[0:0]"/>
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</mux>
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</interconnect>
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</pb_type>
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<interconnect>
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<direct name="direct1" input="lut5inter.in" output="ble5[0:0].in"/>
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<direct name="direct2" input="lut5inter.in" output="ble5[1:1].in"/>
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<direct name="direct3" input="ble5[1:0].out" output="lut5inter.out"/>
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<complete name="complete1" input="lut5inter.clk" output="ble5[1:0].clk"/>
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</interconnect>
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</pb_type>
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<interconnect>
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<direct name="direct1" input="fle.in[4:0]" output="lut5inter.in"/>
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<direct name="direct2" input="lut5inter.out" output="fle.out"/>
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<direct name="direct3" input="fle.clk" output="lut5inter.clk"/>
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</interconnect>
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</mode>
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<mode name="n1_lut6">
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<pb_type name="ble6" num_pb="1">
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<input name="in" num_pins="6"/>
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<output name="out" num_pins="1"/>
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<clock name="clk" num_pins="1"/>
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<pb_type name="lut6" blif_model=".names" num_pb="1" class="lut">
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<input name="in" num_pins="6" port_class="lut_in"/>
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<output name="out" num_pins="1" port_class="lut_out"/>
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<delay_matrix type="max" in_port="lut6.in" out_port="lut6.out">
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261e-12
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261e-12
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261e-12
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261e-12
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261e-12
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261e-12
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</delay_matrix>
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</pb_type>
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<!-- Define flip-flop -->
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<pb_type name="ff" blif_model=".latch" num_pb="1" class="flipflop">
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<input name="D" num_pins="1" port_class="D"/>
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<output name="Q" num_pins="1" port_class="Q"/>
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<clock name="clk" num_pins="1" port_class="clock"/>
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<T_setup value="66e-12" port="ff.D" clock="clk"/>
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<T_clock_to_Q max="124e-12" port="ff.Q" clock="clk"/>
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</pb_type>
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<interconnect>
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<direct name="direct1" input="ble6.in" output="lut6[0:0].in"/>
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<direct name="direct2" input="lut6.out" output="ff.D">
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<pack_pattern name="ble6" in_port="lut6.out" out_port="ff.D"/>
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</direct>
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<direct name="direct3" input="ble6.clk" output="ff.clk"/>
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<mux name="mux1" input="ff.Q lut6.out" output="ble6.out">
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<delay_constant max="25e-12" in_port="lut6.out" out_port="ble6.out"/>
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<delay_constant max="45e-12" in_port="ff.Q" out_port="ble6.out"/>
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</mux>
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</interconnect>
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</pb_type>
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<interconnect>
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<direct name="direct1" input="fle.in" output="ble6.in"/>
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<direct name="direct2" input="ble6.out" output="fle.out[0:0]"/>
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<direct name="direct3" input="fle.clk" output="ble6.clk"/>
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</interconnect>
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</mode>
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</pb_type>
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<interconnect>
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<complete name="crossbar" input="clb.I fle[9:0].out" output="fle[9:0].in">
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<delay_constant max="95e-12" in_port="clb.I" out_port="fle[9:0].in"/>
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<delay_constant max="75e-12" in_port="fle[9:0].out" out_port="fle[9:0].in"/>
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</complete>
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<complete name="clks" input="clb.clk" output="fle[9:0].clk">
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</complete>
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<direct name="clbouts1" input="fle[9:0].out[0:0]" output="clb.O[9:0]"/>
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<direct name="clbouts2" input="fle[9:0].out[1:1]" output="clb.O[19:10]"/>
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</interconnect>
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</pb_type>
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</complexblocklist>
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<power>
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<local_interconnect C_wire="2.5e-10"/>
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</power>
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<clocks>
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<clock buffer_size="auto" C_wire="2.5e-10"/>
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</clocks>
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</architecture>
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