2020-07-28 14:44:06 -05:00
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# Regression tests for OpenFPGA
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The regression tests are grouped in category of OpenFPGA tools as well as integrated flows.
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The principle is that each OpenFPGA tool should have a set of regression tests.
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- compilation\_verfication: a quicktest after compilation
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- Basic regression tests should focus on fundamental flow integration, such as
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- Yosys + VPR + OpenFPGA for a Verilog-to-Verification flow-run
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- FPGA-Verilog regression tests should focus on testing fabric correctness, such as
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- VPR + OpenFPGA integration for a BLIF-to-Verification flow-run
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- FPGA-Bitstream regression tests should focus on testing bitstream correctness and runtime on large devices and benchmark suites
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- FPGA-SDC regression test should focus on SDC file generation and necessary syntax check
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- FPGA-SPICE regression test should focus on SPICE netlist generation / compilation and SPICE simulations qwith QoR checks.
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2021-02-22 11:17:02 -06:00
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- Quicklogic regression test is to ensure working flows for QuickLogic's devices and variants
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- Benchmark sweep regression test should focus on testing mainly the bitstream generation for a wide range of benchmark suites
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2020-07-28 14:44:06 -05:00
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Please keep this README up-to-date on the OpenFPGA tools
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