178 lines
5.4 KiB
C++
178 lines
5.4 KiB
C++
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/*
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* yosys -- Yosys Open SYnthesis Suite
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*
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* Copyright (C) 2012 Clifford Wolf <clifford@clifford.at>
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*
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* Permission to use, copy, modify, and/or distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*
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*/
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#include "kernel/yosys.h"
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#include "kernel/sigtools.h"
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USING_YOSYS_NAMESPACE
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PRIVATE_NAMESPACE_BEGIN
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struct EquivAddPass : public Pass {
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EquivAddPass() : Pass("equiv_add", "add a $equiv cell") { }
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virtual void help()
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{
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// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
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log("\n");
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log(" equiv_add [-try] gold_sig gate_sig\n");
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log("\n");
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log("This command adds an $equiv cell for the specified signals.\n");
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log("\n");
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log("\n");
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log(" equiv_add [-try] -cell gold_cell gate_cell\n");
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log("\n");
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log("This command adds $equiv cells for the ports of the specified cells.\n");
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log("\n");
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}
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virtual void execute(std::vector<std::string> args, Design *design)
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{
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bool try_mode = false;
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if (design->selected_active_module.empty())
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log_cmd_error("This command must be executed in module context!\n");
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Module *module = design->module(design->selected_active_module);
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log_assert(module != nullptr);
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if (GetSize(args) > 1 && args[1] == "-try") {
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args.erase(args.begin() + 1);
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try_mode = true;
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}
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if (GetSize(args) == 4 && args[1] == "-cell")
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{
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Cell *gold_cell = module->cell(RTLIL::escape_id(args[2]));
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Cell *gate_cell = module->cell(RTLIL::escape_id(args[3]));
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if (gold_cell == nullptr) {
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if (try_mode) {
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log_warning("Can't find gold cell '%s'.\n", args[2].c_str());
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return;
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}
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log_cmd_error("Can't find gold cell '%s'.\n", args[2].c_str());
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}
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if (gate_cell == nullptr) {
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if (try_mode) {
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log_warning("Can't find gate cell '%s'.\n", args[3].c_str());
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return;
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}
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log_cmd_error("Can't find gate cell '%s'.\n", args[3].c_str());
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}
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for (auto conn : gold_cell->connections())
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{
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auto port = conn.first;
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SigSpec gold_sig = gold_cell->getPort(port);
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SigSpec gate_sig = gate_cell->getPort(port);
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int width = min(GetSize(gold_sig), GetSize(gate_sig));
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if (gold_cell->input(port) && gate_cell->input(port))
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{
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SigSpec combined_sig = module->addWire(NEW_ID, width);
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for (int i = 0; i < width; i++) {
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module->addEquiv(NEW_ID, gold_sig[i], gate_sig[i], combined_sig[i]);
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gold_sig[i] = gate_sig[i] = combined_sig[i];
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}
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gold_cell->setPort(port, gold_sig);
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gate_cell->setPort(port, gate_sig);
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continue;
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}
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if (gold_cell->output(port) && gate_cell->output(port))
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{
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SigSpec new_gold_wire = module->addWire(NEW_ID, width);
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SigSpec new_gate_wire = module->addWire(NEW_ID, width);
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SigSig gg_conn;
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for (int i = 0; i < width; i++) {
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module->addEquiv(NEW_ID, new_gold_wire[i], new_gold_wire[i], gold_sig[i]);
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gg_conn.first.append(gate_sig[i]);
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gg_conn.second.append(gold_sig[i]);
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gold_sig[i] = new_gold_wire[i];
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gate_sig[i] = new_gate_wire[i];
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}
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module->connect(gg_conn);
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gold_cell->setPort(port, gold_sig);
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gate_cell->setPort(port, gate_sig);
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continue;
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}
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}
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}
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else
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{
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if (GetSize(args) != 3)
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cmd_error(args, GetSize(args)-1, "Invalid number of arguments.");
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SigSpec gold_signal, gate_signal;
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if (!SigSpec::parse(gate_signal, module, args[2])) {
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if (try_mode) {
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log_warning("Error in gate signal: %s\n", args[2].c_str());
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return;
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}
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log_cmd_error("Error in gate signal: %s\n", args[2].c_str());
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}
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if (!SigSpec::parse_rhs(gate_signal, gold_signal, module, args[1])) {
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if (try_mode) {
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log_warning("Error in gold signal: %s\n", args[1].c_str());
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return;
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}
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log_cmd_error("Error in gold signal: %s\n", args[1].c_str());
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}
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log_assert(GetSize(gold_signal) == GetSize(gate_signal));
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SigSpec equiv_signal = module->addWire(NEW_ID, GetSize(gold_signal));
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SigMap sigmap(module);
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sigmap.apply(gold_signal);
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sigmap.apply(gate_signal);
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dict<SigBit, SigBit> to_equiv_bits;
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pool<Cell*> added_equiv_cells;
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for (int i = 0; i < GetSize(gold_signal); i++) {
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Cell *equiv_cell = module->addEquiv(NEW_ID, gold_signal[i], gate_signal[i], equiv_signal[i]);
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equiv_cell->set_bool_attribute("\\keep");
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to_equiv_bits[gold_signal[i]] = equiv_signal[i];
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to_equiv_bits[gate_signal[i]] = equiv_signal[i];
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added_equiv_cells.insert(equiv_cell);
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}
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for (auto cell : module->cells())
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for (auto conn : cell->connections())
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if (!added_equiv_cells.count(cell) && cell->input(conn.first)) {
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SigSpec new_sig;
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for (auto bit : conn.second)
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if (to_equiv_bits.count(sigmap(bit)))
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new_sig.append(to_equiv_bits.at(sigmap(bit)));
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else
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new_sig.append(bit);
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if (conn.second != new_sig)
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cell->setPort(conn.first, new_sig);
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}
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}
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}
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} EquivAddPass;
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PRIVATE_NAMESPACE_END
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