550 lines
14 KiB
Coq
550 lines
14 KiB
Coq
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/////////////////////////////////////////////////////////////////////
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//// ////
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//// WISHBONE Memory Controller Top Level ////
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//// ////
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//// ////
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//// Author: Rudolf Usselmann ////
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//// rudi@asics.ws ////
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//// ////
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//// ////
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//// Downloaded from: http://www.opencores.org/cores/mem_ctrl/ ////
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//// ////
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/////////////////////////////////////////////////////////////////////
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//// ////
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//// Copyright (C) 2000-2002 Rudolf Usselmann ////
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//// www.asics.ws ////
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//// rudi@asics.ws ////
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//// ////
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//// This source file may be used and distributed without ////
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//// restriction provided that this copyright statement is not ////
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//// removed from the file and that any derivative work contains ////
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//// the original copyright notice and the associated disclaimer.////
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//// ////
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//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ////
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//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ////
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//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ////
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//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ////
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//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ////
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//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ////
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//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ////
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//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ////
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//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ////
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//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ////
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//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ////
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//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ////
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//// POSSIBILITY OF SUCH DAMAGE. ////
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//// ////
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/////////////////////////////////////////////////////////////////////
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// CVS Log
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//
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// $Id: mc_top.v,v 1.7 2002/01/21 13:08:52 rudi Exp $
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//
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// $Date: 2002/01/21 13:08:52 $
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// $Revision: 1.7 $
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// $Author: rudi $
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// $Locker: $
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// $State: Exp $
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//
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// Change History:
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// $Log: mc_top.v,v $
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// Revision 1.7 2002/01/21 13:08:52 rudi
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//
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// Fixed several minor bugs, cleaned up the code further ...
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//
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// Revision 1.6 2001/12/21 05:09:30 rudi
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//
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// - Fixed combinatorial loops in synthesis
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// - Fixed byte select bug
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//
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// Revision 1.5 2001/11/29 02:16:28 rudi
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//
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//
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// - More Synthesis cleanup, mostly for speed
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// - Several bug fixes
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// - Changed code to avoid auto-precharge and
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// burst-terminate combinations (apparently illegal ?)
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// Now we will do a manual precharge ...
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//
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// Revision 1.4 2001/09/10 13:44:17 rudi
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// *** empty log message ***
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//
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// Revision 1.3 2001/09/02 02:28:28 rudi
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//
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// Many fixes for minor bugs that showed up in gate level simulations.
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//
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// Revision 1.2 2001/08/10 08:16:21 rudi
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//
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// - Changed IO names to be more clear.
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// - Uniquifyed define names to be core specific.
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// - Removed "Refresh Early" configuration
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//
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// Revision 1.1 2001/07/29 07:34:41 rudi
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//
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//
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// 1) Changed Directory Structure
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// 2) Fixed several minor bugs
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//
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// Revision 1.3 2001/06/12 15:19:49 rudi
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//
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//
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// Minor changes after running lint, and a small bug fix reading csr and ba_mask registers.
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//
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// Revision 1.2 2001/06/03 11:37:17 rudi
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//
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//
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// 1) Fixed Chip Select Mask Register
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// - Power On Value is now all ones
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// - Comparison Logic is now correct
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//
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// 2) All resets are now asynchronous
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//
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// 3) Converted Power On Delay to an configurable item
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//
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// 4) Added reset to Chip Select Output Registers
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//
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// 5) Forcing all outputs to Hi-Z state during reset
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//
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// Revision 1.1.1.1 2001/05/13 09:39:39 rudi
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// Created Directory Structure
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//
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//
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//
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//
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`include "mc_defines.v"
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module mc_top(clk_i, rst_i,
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wb_data_i, wb_data_o, wb_addr_i, wb_sel_i, wb_we_i, wb_cyc_i,
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wb_stb_i, wb_ack_o, wb_err_o,
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susp_req_i, resume_req_i, suspended_o, poc_o,
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mc_clk_i, mc_br_pad_i, mc_bg_pad_o, mc_ack_pad_i,
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mc_addr_pad_o, mc_data_pad_i, mc_data_pad_o, mc_dp_pad_i,
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mc_dp_pad_o, mc_doe_pad_doe_o, mc_dqm_pad_o, mc_oe_pad_o_,
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mc_we_pad_o_, mc_cas_pad_o_, mc_ras_pad_o_, mc_cke_pad_o_,
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mc_cs_pad_o_, mc_sts_pad_i, mc_rp_pad_o_, mc_vpen_pad_o,
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mc_adsc_pad_o_, mc_adv_pad_o_, mc_zz_pad_o, mc_coe_pad_coe_o
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);
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input clk_i, rst_i;
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// --------------------------------------
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// WISHBONE SLAVE INTERFACE
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input [31:0] wb_data_i;
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output [31:0] wb_data_o;
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input [31:0] wb_addr_i;
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input [3:0] wb_sel_i;
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input wb_we_i;
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input wb_cyc_i;
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input wb_stb_i;
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output wb_ack_o;
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output wb_err_o;
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// --------------------------------------
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// Suspend Resume Interface
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input susp_req_i;
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input resume_req_i;
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output suspended_o;
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// POC
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output [31:0] poc_o;
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// --------------------------------------
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// Memory Bus Signals
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input mc_clk_i;
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input mc_br_pad_i;
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output mc_bg_pad_o;
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input mc_ack_pad_i;
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output [23:0] mc_addr_pad_o;
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input [31:0] mc_data_pad_i;
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output [31:0] mc_data_pad_o;
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input [3:0] mc_dp_pad_i;
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output [3:0] mc_dp_pad_o;
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output mc_doe_pad_doe_o;
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output [3:0] mc_dqm_pad_o;
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output mc_oe_pad_o_;
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output mc_we_pad_o_;
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output mc_cas_pad_o_;
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output mc_ras_pad_o_;
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output mc_cke_pad_o_;
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output [7:0] mc_cs_pad_o_;
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input mc_sts_pad_i;
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output mc_rp_pad_o_;
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output mc_vpen_pad_o;
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output mc_adsc_pad_o_;
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output mc_adv_pad_o_;
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output mc_zz_pad_o;
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output mc_coe_pad_coe_o;
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////////////////////////////////////////////////////////////////////
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//
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// Local Wires
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//
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// WISHBONE Interface Interconnects
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wire wb_read_go;
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wire wb_write_go;
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wire wb_first;
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wire wb_wait;
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wire mem_ack;
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// Suspend Resume Interface
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wire susp_sel;
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// Register File Interconnects
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wire [31:0] rf_dout;
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wire [31:0] csc;
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wire [31:0] tms;
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wire [31:0] sp_csc;
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wire [31:0] sp_tms;
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wire [7:0] cs;
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wire fs;
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wire cs_le;
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wire [7:0] cs_need_rfr;
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wire [2:0] ref_int;
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wire [31:0] mem_dout;
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wire wp_err;
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// Address Select Signals
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wire [12:0] row_adr;
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wire [1:0] bank_adr;
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wire cmd_a10;
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wire row_sel;
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wire next_adr;
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wire [10:0] page_size;
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wire lmr_sel;
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wire wr_hold;
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// OBCT Signals
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wire bank_set;
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wire bank_clr;
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wire bank_clr_all;
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wire bank_open;
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wire row_same;
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wire [7:0] obct_cs;
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wire any_bank_open;
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// Data path Controller Signals
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wire dv;
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wire pack_le0, pack_le1, pack_le2; // Pack Latch Enable
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wire par_err;
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wire [31:0] mc_data_od;
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wire [3:0] mc_dp_od;
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wire [23:0] mc_addr_d;
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wire [35:0] mc_data_ir;
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// Refresh Counter Signals
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wire rfr_req;
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wire rfr_ack;
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wire [7:0] rfr_ps_val;
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// Memory Timing Block Signals
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wire data_oe;
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wire oe_;
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wire we_;
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wire cas_;
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wire ras_;
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wire cke_;
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wire lmr_req;
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wire lmr_ack;
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wire init_req;
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wire init_ack;
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wire [7:0] spec_req_cs;
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wire cs_en;
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wire wb_cycle, wr_cycle;
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wire [31:0] tms_s;
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wire [31:0] csc_s;
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wire mc_c_oe_d;
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wire mc_br_r;
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wire mc_bg_d;
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wire mc_adsc_d;
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wire mc_adv_d;
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wire mc_ack_r;
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wire err;
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wire mc_sts_i;
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////////////////////////////////////////////////////////////////////
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//
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// Misc Logic
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//
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assign obct_cs = (rfr_ack | susp_sel) ? cs_need_rfr :
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(lmr_ack | init_ack) ? spec_req_cs : cs;
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assign lmr_sel = lmr_ack | init_ack;
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assign tms_s = lmr_sel ? sp_tms : tms;
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assign csc_s = lmr_sel ? sp_csc : csc;
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wire not_mem_cyc;
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assign not_mem_cyc = wb_cyc_i & wb_stb_i & !( `MC_MEM_SEL );
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reg mem_ack_r;
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always @(posedge clk_i)
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mem_ack_r <= #1 mem_ack;
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////////////////////////////////////////////////////////////////////
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//
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// Modules
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//
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mc_rf u0(
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.clk( clk_i ),
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.rst( rst_i ),
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.wb_data_i( wb_data_i ),
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.rf_dout( rf_dout ),
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.wb_addr_i( wb_addr_i ),
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.wb_we_i( wb_we_i ),
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.wb_cyc_i( wb_cyc_i ),
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.wb_stb_i( wb_stb_i ),
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.wb_ack_o( ),
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.wp_err( wp_err ),
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.csc( csc ),
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.tms( tms ),
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.poc( poc_o ),
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.sp_csc( sp_csc ),
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.sp_tms( sp_tms ),
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.cs( cs ),
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.mc_data_i( mc_data_ir[31:0]),
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.mc_sts( mc_sts_ir ),
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.mc_vpen( mc_vpen_pad_o ),
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.fs( fs ),
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.cs_le( cs_le ),
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.cs_le_d( cs_le_d ),
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.cs_need_rfr( cs_need_rfr ),
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.ref_int( ref_int ),
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.rfr_ps_val( rfr_ps_val ),
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.spec_req_cs( spec_req_cs ),
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.init_req( init_req ),
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.init_ack( init_ack ),
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.lmr_req( lmr_req ),
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.lmr_ack( lmr_ack )
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);
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mc_adr_sel u1(
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.clk( clk_i ),
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.csc( csc_s ),
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.tms( tms_s ),
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.wb_stb_i( wb_stb_i ),
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//.wb_ack_o( wb_ack_o ),
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.wb_ack_o( mem_ack_r ),
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.wb_addr_i( wb_addr_i ),
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.wb_we_i( wb_we_i ),
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.wb_write_go( wb_write_go ),
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.wr_hold( wr_hold ),
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.cas_( cas_ ),
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.mc_addr( mc_addr_d ),
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.row_adr( row_adr ),
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.bank_adr( bank_adr ),
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.rfr_ack( rfr_ack ),
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.cs_le( cs_le ),
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.cmd_a10( cmd_a10 ),
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.row_sel( row_sel ),
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.lmr_sel( lmr_sel ),
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.next_adr( next_adr ),
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.wr_cycle( wr_cycle ),
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.page_size( page_size )
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);
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mc_obct_top u2(
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.clk( clk_i ),
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.rst( rst_i ),
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.cs( obct_cs ),
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.row_adr( row_adr ),
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.bank_adr( bank_adr ),
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||
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.bank_set( bank_set ),
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.bank_clr( bank_clr ),
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.bank_clr_all( bank_clr_all ),
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||
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.bank_open( bank_open ),
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||
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.any_bank_open( any_bank_open ),
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||
|
|
.row_same( row_same ),
|
||
|
|
.rfr_ack( rfr_ack )
|
||
|
|
);
|
||
|
|
|
||
|
|
mc_dp u3(
|
||
|
|
.clk( clk_i ),
|
||
|
|
.rst( rst_i ),
|
||
|
|
.csc( csc ),
|
||
|
|
.wb_cyc_i( wb_cyc_i ),
|
||
|
|
.wb_stb_i( wb_stb_i ),
|
||
|
|
.mem_ack( mem_ack ),
|
||
|
|
//.wb_ack_o( wb_ack_o ),
|
||
|
|
.wb_ack_o( mem_ack_r ),
|
||
|
|
.wb_we_i( wb_we_i ),
|
||
|
|
.wb_data_i( wb_data_i ),
|
||
|
|
.wb_data_o( mem_dout ),
|
||
|
|
.wb_read_go( wb_read_go ),
|
||
|
|
.mc_clk( mc_clk_i ),
|
||
|
|
.mc_data_del( mc_data_ir ),
|
||
|
|
.mc_dp_i( mc_dp_pad_i ),
|
||
|
|
.mc_data_o( mc_data_od ),
|
||
|
|
.mc_dp_o( mc_dp_od ),
|
||
|
|
.dv( dv ),
|
||
|
|
.pack_le0( pack_le0 ),
|
||
|
|
.pack_le1( pack_le1 ),
|
||
|
|
.pack_le2( pack_le2 ),
|
||
|
|
.byte_en( wb_sel_i ),
|
||
|
|
.par_err( par_err )
|
||
|
|
);
|
||
|
|
|
||
|
|
mc_refresh u4(
|
||
|
|
.clk( clk_i ),
|
||
|
|
.rst( rst_i ),
|
||
|
|
.cs_need_rfr( cs_need_rfr ),
|
||
|
|
.ref_int( ref_int ),
|
||
|
|
.rfr_req( rfr_req ),
|
||
|
|
.rfr_ack( rfr_ack ),
|
||
|
|
.rfr_ps_val( rfr_ps_val )
|
||
|
|
);
|
||
|
|
|
||
|
|
mc_timing u5(
|
||
|
|
.clk( clk_i ),
|
||
|
|
.mc_clk( mc_clk_i ),
|
||
|
|
.rst( rst_i ),
|
||
|
|
.wb_cyc_i( wb_cyc_i ),
|
||
|
|
.wb_stb_i( wb_stb_i ),
|
||
|
|
.wb_we_i( wb_we_i ),
|
||
|
|
.wb_read_go( wb_read_go ),
|
||
|
|
.wb_write_go( wb_write_go ),
|
||
|
|
.wb_first( wb_first ),
|
||
|
|
.wb_wait( wb_wait ),
|
||
|
|
.mem_ack( mem_ack ),
|
||
|
|
.err( err ),
|
||
|
|
.susp_req( susp_req_i ),
|
||
|
|
.resume_req( resume_req_i ),
|
||
|
|
.suspended( suspended_o ),
|
||
|
|
.susp_sel( susp_sel ),
|
||
|
|
.mc_br( mc_br_r ),
|
||
|
|
.mc_bg( mc_bg_d ),
|
||
|
|
.mc_ack( mc_ack_r ),
|
||
|
|
.not_mem_cyc( not_mem_cyc ),
|
||
|
|
.data_oe( data_oe ),
|
||
|
|
.oe_( oe_ ),
|
||
|
|
.we_( we_ ),
|
||
|
|
.cas_( cas_ ),
|
||
|
|
.ras_( ras_ ),
|
||
|
|
.cke_( cke_ ),
|
||
|
|
.cs_en( cs_en ),
|
||
|
|
.mc_adsc( mc_adsc_d ),
|
||
|
|
.mc_adv( mc_adv_d ),
|
||
|
|
.mc_c_oe( mc_c_oe_d ),
|
||
|
|
.wb_cycle( wb_cycle ),
|
||
|
|
.wr_cycle( wr_cycle ),
|
||
|
|
.csc( csc_s ),
|
||
|
|
.tms( tms_s ),
|
||
|
|
.cs( obct_cs ),
|
||
|
|
.lmr_req( lmr_req ),
|
||
|
|
.lmr_ack( lmr_ack ),
|
||
|
|
.cs_le( cs_le ),
|
||
|
|
.cs_le_d( cs_le_d ),
|
||
|
|
.cmd_a10( cmd_a10 ),
|
||
|
|
.row_sel( row_sel ),
|
||
|
|
.next_adr( next_adr ),
|
||
|
|
.page_size( page_size ),
|
||
|
|
.bank_set( bank_set ),
|
||
|
|
.bank_clr( bank_clr ),
|
||
|
|
.bank_clr_all( bank_clr_all ),
|
||
|
|
.bank_open( bank_open ),
|
||
|
|
.any_bank_open( any_bank_open ),
|
||
|
|
.row_same( row_same ),
|
||
|
|
.dv( dv ),
|
||
|
|
.pack_le0( pack_le0 ),
|
||
|
|
.pack_le1( pack_le1 ),
|
||
|
|
.pack_le2( pack_le2 ),
|
||
|
|
.par_err( par_err ),
|
||
|
|
.rfr_req( rfr_req ),
|
||
|
|
.rfr_ack( rfr_ack ),
|
||
|
|
.init_req( init_req ),
|
||
|
|
.init_ack( init_ack )
|
||
|
|
);
|
||
|
|
|
||
|
|
mc_wb_if u6(
|
||
|
|
.clk( clk_i ),
|
||
|
|
.rst( rst_i ),
|
||
|
|
.wb_addr_i( wb_addr_i ),
|
||
|
|
.wb_cyc_i( wb_cyc_i ),
|
||
|
|
.wb_stb_i( wb_stb_i ),
|
||
|
|
.wb_we_i( wb_we_i ),
|
||
|
|
.wb_ack_o( wb_ack_o ),
|
||
|
|
.wb_err( wb_err_o ),
|
||
|
|
.wb_read_go( wb_read_go ),
|
||
|
|
.wb_write_go( wb_write_go ),
|
||
|
|
.wb_first( wb_first ),
|
||
|
|
.wb_wait( wb_wait ),
|
||
|
|
.mem_ack( mem_ack ),
|
||
|
|
.wr_hold( wr_hold ),
|
||
|
|
.err( err ),
|
||
|
|
.par_err( par_err ),
|
||
|
|
.wp_err( wp_err ),
|
||
|
|
.wb_data_o( wb_data_o ),
|
||
|
|
.mem_dout( mem_dout ),
|
||
|
|
.rf_dout( rf_dout )
|
||
|
|
);
|
||
|
|
|
||
|
|
mc_mem_if u7(
|
||
|
|
.clk( clk_i ),
|
||
|
|
.rst( rst_i ),
|
||
|
|
.mc_rp( mc_rp_pad_o_ ),
|
||
|
|
.mc_clk( mc_clk_i ),
|
||
|
|
.mc_br( mc_br_pad_i ),
|
||
|
|
.mc_bg( mc_bg_pad_o ),
|
||
|
|
.mc_addr( mc_addr_pad_o ),
|
||
|
|
.mc_data_o( mc_data_pad_o ),
|
||
|
|
.mc_dp_o( mc_dp_pad_o ),
|
||
|
|
.mc_data_oe( mc_doe_pad_doe_o),
|
||
|
|
.mc_dqm( mc_dqm_pad_o ),
|
||
|
|
.mc_oe_( mc_oe_pad_o_ ),
|
||
|
|
.mc_we_( mc_we_pad_o_ ),
|
||
|
|
.mc_cas_( mc_cas_pad_o_ ),
|
||
|
|
.mc_ras_( mc_ras_pad_o_ ),
|
||
|
|
.mc_cke_( mc_cke_pad_o_ ),
|
||
|
|
.mc_cs_( mc_cs_pad_o_ ),
|
||
|
|
.mc_adsc_( mc_adsc_pad_o_ ),
|
||
|
|
.mc_adv_( mc_adv_pad_o_ ),
|
||
|
|
.mc_br_r( mc_br_r ),
|
||
|
|
.mc_bg_d( mc_bg_d ),
|
||
|
|
.mc_data_od( mc_data_od ),
|
||
|
|
.mc_dp_od( mc_dp_od ),
|
||
|
|
.mc_addr_d( mc_addr_d ),
|
||
|
|
.mc_ack( mc_ack_pad_i ),
|
||
|
|
.mc_zz_o( mc_zz_pad_o ),
|
||
|
|
.we_( we_ ),
|
||
|
|
.ras_( ras_ ),
|
||
|
|
.cas_( cas_ ),
|
||
|
|
.cke_( cke_ ),
|
||
|
|
.mc_adsc_d( mc_adsc_d ),
|
||
|
|
.mc_adv_d( mc_adv_d ),
|
||
|
|
.cs_en( cs_en ),
|
||
|
|
.rfr_ack( rfr_ack ),
|
||
|
|
.cs_need_rfr( cs_need_rfr ),
|
||
|
|
.lmr_sel( lmr_sel ),
|
||
|
|
.spec_req_cs( spec_req_cs ),
|
||
|
|
.cs( cs ),
|
||
|
|
.fs( fs ),
|
||
|
|
.data_oe( data_oe ),
|
||
|
|
.susp_sel( susp_sel ),
|
||
|
|
.suspended_o( suspended_o ),
|
||
|
|
.mc_c_oe( mc_coe_pad_coe_o),
|
||
|
|
.mc_c_oe_d( mc_c_oe_d ),
|
||
|
|
.mc_ack_r( mc_ack_r ),
|
||
|
|
.oe_( oe_ ),
|
||
|
|
.wb_cyc_i( wb_cyc_i ),
|
||
|
|
.wb_stb_i( wb_stb_i ),
|
||
|
|
.wb_sel_i( wb_sel_i ),
|
||
|
|
.wb_cycle( wb_cycle ),
|
||
|
|
.wr_cycle( wr_cycle ),
|
||
|
|
.mc_data_i( mc_data_pad_i ),
|
||
|
|
.mc_dp_i( mc_dp_pad_i ),
|
||
|
|
.mc_data_ir( mc_data_ir ),
|
||
|
|
.mc_sts_i( mc_sts_pad_i ),
|
||
|
|
.mc_sts_ir( mc_sts_ir )
|
||
|
|
);
|
||
|
|
|
||
|
|
endmodule
|