To support FPGA fabrics with multiple clocks, OpenFPGA allows users to define a default operating clock frequency as well as a set of clock ports using different frequencies.
..note:: The frequency is considered as a default operating clock frequency, which will be used when a clock pin of a multi-clock FPGA fabric lacks explicit clock definition.
can be either ``auto`` or an integer. When set to ``auto``, OpenFPGA will infer the number of clock cycles from the average/median of all the signal activities.
When set to an integer, OpenFPGA will use the given number of clock cycles in HDL and SPICE simulations.
-``slack="<float>"``
add a margin to the critical path delay in the HDL and SPICE simulations.
This parameter is applied to the critical path delay provided by VPR STA engine.
So it is only valid when option ``frequency`` is set to ``auto``.
This aims to compensate any inaccuracy in STA results.
Typically, the slack value is between ``0`` and ``1``.
For example, ``slack=0.2`` implies that the actual clock period in simulations is 120% of the critical path delay reported by VPR.
..note:: Only valid when option ``frequency`` is set to ``auto``
..warning:: Avoid to use a negative slack! This may cause your simulation to fail!
Specify a unique name for a clock signal. The name will be used in generating clock stimulus in testbenches.
-``port="<string>``
Specify the clock port which the clock signal should be applied to. The clock port must be a valid clock port defined in OpenFPGA architecture description. Explicit index is required, e.g., ``clk[1:1]``. Otherwise, default index ``0`` will be considered, e.g., ``clk`` will be translated as ``clk[0:0]``.
..note:: You can define clock ports either through the tile annotation in :ref:`annotate_vpr_arch_physical_tile_annotation` or :ref:`circuit_library_circuit_port`.
-``frequency="<float>``
Specify frequency of a clock signal in the unit of ``[Hz]``
..warning:: Currently, we only allow operating clocks to be overwritten!!!
Specify a unique name for a clock signal. The name should match a reserved word of programming clock, i.e., ``bl_sr_clock`` and ``wl_sr_clock``.
..note:: The ``bl_sr_clock`` represents the clock signal driving the BL shift register chains, while the ``wl_sr_clock`` represents the clock signal driving the WL shift register chains
-``port="<string>``
Specify the clock port which the clock signal should be applied to. The clock port must be a valid clock port defined in OpenFPGA architecture description. Explicit index is required, e.g., ``clk[1:1]``. Otherwise, default index ``0`` will be considered, e.g., ``clk`` will be translated as ``clk[0:0]``.
-``frequency="auto|<float>``
Specify frequency of a clock signal in the unit of ``[Hz]``. If ``auto`` is used, the programming clock frequency will be inferred by OpenFPGA.
-``is_shift_register="<bool>``
Specify if this clock signal is used to drive shift register chains in BL/WL protocols
..note:: Programming clock frequency is typically much slower than the operating clock and strongly depends on the process technology. Suggest to characterize the speed of your configuration protocols before specifying a value!
Specify the options in outputting simulation results to log files
-``verbose="true|false"``
Specify if the simulation waveforms should be printed out after SPICE simulations. If turned on, it will show in all the SPICE netlists
..code-block:: python
.option POST
..note:: when the SPICE netlists are large or a long simulation duration is defined, the post option is recommended to be off. If not, huge disk space will be occupied by the waveform files.
Specify the transient step in SPICE simulation. Typically, the smaller the step is, the higher the accuracy that can be reached while the long simulation runtime is. The recommended accuracy is between 0.1ps and 0.01ps, which generates good accuracy and runtime is not significantly long.
Define the starting and ending point in measuring the slew of a rising or a falling edge of a signal.
-``upper_thres_pct="<float>"`` the ending point in measuring the slew of a rising edge. It is expressed as a percentage of the maximum voltage of a signal. For example, the meaning of upper_thres_pct=0.95 is depicted in :numref:`fig_measure_edge`.
-``lower_thres_pct="<float>"`` the starting point in measuring the slew of a rising edge. It is expressed as a percentage of the maximum voltage of a signal. For example, the meaning of lower_thres_pct=0.05 is depicted in :numref:`fig_measure_edge`.
.._fig_measure_edge:
..figure:: figures/meas_edge.png
:scale:80%
:alt:map to buried traesure
An illustrative example on measuring the slew and delay of signals
Users can define the slew time of input and clock signals to be applied to FPGA I/Os in testbenches under XML node ``<clock>`` and ``<input>`` respectively.
This is used by FPGA-SPICE in generating testbenches
Specify the slew rate of an input or clock signal at rising or falling edge
-``slew_type="[abs|frac]"`` specify the type of slew time definition at the rising or falling edge of a lock/input port.
* The type of ``abs`` implies that the slew time is the absolute value. For example, ``slew_type="abs" slew_time="20e-12"`` means that the slew of a clock signal is 20ps.
* The type of ``frac`` means that the slew time is related to the period (frequency) of the clock signal. For example, ``slew_type="frac" slew_time="0.05"`` means that the slew of a clock signal takes 5% of the period of the clock.
-``slew_time="<float>"`` specify the slew rate of an input or clock signal at the rising/falling edge.
:numref:`fig_measure_edge` depicts the definition of the slew and delays of signals and the parameters that can be supported by FPGA-SPICE.
