244 lines
11 KiB
C++
244 lines
11 KiB
C++
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/***********************************************
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* This file includes functions to generate
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* Verilog submodules for multiplexers.
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* including both fundamental submodules
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* such as a branch in a multiplexer
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* and the full multiplexer
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**********************************************/
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#include <string>
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#include "util.h"
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#include "vtr_assert.h"
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/* Device-level header files */
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#include "mux_graph.h"
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#include "physical_types.h"
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#include "vpr_types.h"
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/* FPGA-X2P context header files */
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#include "spice_types.h"
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#include "fpga_x2p_naming.h"
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#include "fpga_x2p_utils.h"
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/* FPGA-Verilog context header files */
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#include "verilog_global.h"
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#include "verilog_writer_utils.h"
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#include "verilog_mux.h"
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/***********************************************
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* Generate Verilog codes modeling an branch circuit
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* for a multiplexer with the given size
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**********************************************/
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static
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void generate_verilog_cmos_mux_branch_module_structural(std::fstream& fp,
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const CircuitLibrary& circuit_lib,
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const CircuitModelId& circuit_model,
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const std::string& module_name,
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const MuxGraph& mux_graph) {
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/* Get the tgate model */
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CircuitModelId tgate_model = circuit_lib.pass_gate_logic_model(circuit_model);
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/* Skip output if the tgate model is a MUX2, it is handled by essential-gate generator */
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if (SPICE_MODEL_GATE == circuit_lib.model_type(tgate_model)) {
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VTR_ASSERT(SPICE_MODEL_GATE_MUX2 == circuit_lib.gate_type(tgate_model));
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return;
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}
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/* Get model ports of tgate */
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std::vector<CircuitPortId> tgate_input_ports = circuit_lib.model_ports_by_type(tgate_model, SPICE_MODEL_PORT_INPUT, true);
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std::vector<CircuitPortId> tgate_output_ports = circuit_lib.model_ports_by_type(tgate_model, SPICE_MODEL_PORT_OUTPUT, true);
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std::vector<CircuitPortId> tgate_global_ports = circuit_lib.model_global_ports_by_type(tgate_model, SPICE_MODEL_PORT_INPUT);
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VTR_ASSERT(3 == tgate_input_ports.size());
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VTR_ASSERT(1 == tgate_output_ports.size());
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/* Make sure we have a valid file handler*/
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check_file_handler(fp);
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/* Generate the Verilog netlist according to the mux_graph */
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/* Find out the number of inputs */
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size_t num_inputs = mux_graph.num_inputs();
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/* Find out the number of outputs */
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size_t num_outputs = mux_graph.num_outputs();
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/* Find out the number of memory bits */
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size_t num_mems = mux_graph.num_memory_bits();
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/* Check codes to ensure the port of Verilog netlists will match */
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/* MUX graph must have only 1 output */
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VTR_ASSERT(1 == num_outputs);
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/* MUX graph must have only 1 level*/
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VTR_ASSERT(1 == mux_graph.num_levels());
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/* Comment lines */
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fp << "//---- Structural Verilog for CMOS MUX basis module:" << module_name << "-----" << std::endl;
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/* Print the port list and definition */
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fp << "module " << module_name << "(" << std::endl;
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/* Create port information */
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BasicPort input_port;
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/* Configure each input port */
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input_port.set_name(std::string("in"));
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input_port.set_width(num_inputs);
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BasicPort output_port;
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/* Configure each input port */
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output_port.set_name(std::string("out"));
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output_port.set_width(num_outputs);
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BasicPort mem_port;
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/* Configure each input port */
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mem_port.set_name(std::string("mem"));
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mem_port.set_width(num_mems);
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BasicPort mem_inv_port;
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/* Configure each input port */
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mem_inv_port.set_name(std::string("mem_inv"));
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mem_inv_port.set_width(num_mems);
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/* TODO: Generate global ports */
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for (const auto& port : tgate_global_ports) {
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BasicPort basic_port;
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/* Configure each input port */
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basic_port.set_name(circuit_lib.port_prefix(port));
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basic_port.set_width(circuit_lib.port_size(port));
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/* Print port */
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fp << "\t" << generate_verilog_port(VERILOG_PORT_INPUT, basic_port) << "," << std::endl;
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}
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/* TODO: add a module to the Module Manager */
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/* Port list */
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fp << "\t" << generate_verilog_port(VERILOG_PORT_INPUT, input_port) << "," << std::endl;
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fp << "\t" << generate_verilog_port(VERILOG_PORT_OUTPUT, output_port) << "," << std::endl;
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fp << "\t" << generate_verilog_port(VERILOG_PORT_INPUT, mem_port) << "," << std::endl;
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fp << "\t" << generate_verilog_port(VERILOG_PORT_INPUT, mem_inv_port) << std::endl;
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fp << ");" << std::endl;
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/* Verilog Behavior description for a MUX */
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fp << "//---- Structure-level description -----" << std::endl;
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/* Special case: only one memory, switch case is simpler
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* When mem = 1, propagate input 0;
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* when mem = 0, propagate input 1;
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*/
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if (1 == num_mems) {
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/* Transmission gates are connected to each input and also the output*/
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fp << "\t" << circuit_lib.model_name(tgate_model) << " " << circuit_lib.model_prefix(tgate_model) << "_0 ";
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/* Dump explicit port map if required */
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/* TODO: add global port support for tgate model */
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if (true == circuit_lib.dump_explicit_port_map(tgate_model)) {
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fp << " (";
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fp << " ." << circuit_lib.port_lib_name(tgate_input_ports[0]) << "(" << "in[0]" << "),";
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fp << " ." << circuit_lib.port_lib_name(tgate_input_ports[1]) << "(" << generate_verilog_port(VERILOG_PORT_CONKT, mem_port) << "),";
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fp << " ." << circuit_lib.port_lib_name(tgate_input_ports[2]) << "(" << generate_verilog_port(VERILOG_PORT_CONKT, mem_inv_port) << "),";
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fp << " ." << circuit_lib.port_lib_name(tgate_output_ports[0]) << "(" << generate_verilog_port(VERILOG_PORT_CONKT, output_port) << ")";
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fp << ");" << std::endl;
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} else {
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fp << " (";
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fp << generate_verilog_port(VERILOG_PORT_CONKT, input_port);
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fp << ", " << generate_verilog_port(VERILOG_PORT_CONKT, mem_port);
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fp << ", " << generate_verilog_port(VERILOG_PORT_CONKT, mem_inv_port);
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fp << ", " << generate_verilog_port(VERILOG_PORT_CONKT, output_port);
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fp << ");" << std::endl;
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}
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/* Transmission gates are connected to each input and also the output*/
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fp << "\t" << circuit_lib.model_name(tgate_model) << " " << circuit_lib.model_prefix(tgate_model) << "_1 ";
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/* Dump explicit port map if required */
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if (true == circuit_lib.dump_explicit_port_map(tgate_model)) {
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fp << " (";
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fp << " ." << circuit_lib.port_lib_name(tgate_input_ports[0]) << "(" << "in[1]" << "),";
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fp << " ." << circuit_lib.port_lib_name(tgate_input_ports[1]) << "(" << generate_verilog_port(VERILOG_PORT_CONKT, mem_inv_port) << "),";
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fp << " ." << circuit_lib.port_lib_name(tgate_input_ports[2]) << "(" << generate_verilog_port(VERILOG_PORT_CONKT, mem_port) << "),";
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fp << " ." << circuit_lib.port_lib_name(tgate_output_ports[0]) << "(" << generate_verilog_port(VERILOG_PORT_CONKT, output_port) << ")";
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fp << ");" << std::endl;
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} else {
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fp << " (";
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fp << generate_verilog_port(VERILOG_PORT_CONKT, input_port);
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fp << ", " << generate_verilog_port(VERILOG_PORT_CONKT, mem_inv_port);
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fp << ", " << generate_verilog_port(VERILOG_PORT_CONKT, mem_port);
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fp << ", " << generate_verilog_port(VERILOG_PORT_CONKT, output_port);
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fp << ");" << std::endl;
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}
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} else {
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/* Other cases, we need to follow the rules:
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* When mem[k] is enabled, switch on input[k]
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* Only one memory bit is enabled!
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*/
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for (size_t i = 0; i < num_mems; i++) {
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fp << "\t" << circuit_lib.model_name(tgate_model) << " " << circuit_lib.model_prefix(tgate_model) << "_" << i << " ";
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if (true == circuit_lib.dump_explicit_port_map(tgate_model)) {
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fp << " (";
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fp << " ." << circuit_lib.port_lib_name(tgate_input_ports[0]) << "(" << "in[" << i << "]" << "),";
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fp << " ." << circuit_lib.port_lib_name(tgate_input_ports[1]) << "(" << "mem[" << i << "]" << "),";
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fp << " ." << circuit_lib.port_lib_name(tgate_input_ports[2]) << "(" << "mem_inv[" << i << "]" << "),";
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fp << " ." << circuit_lib.port_lib_name(tgate_output_ports[0]) << "(" << generate_verilog_port(VERILOG_PORT_CONKT, output_port) << ")";
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fp << ");" << std::endl;
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} else {
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fp << " (";
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fp << "in[" << i << "]";
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fp << ", " << "mem[" << i << "]";
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fp << ", " << "mem_inv[" << i << "]";
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fp << ", " << generate_verilog_port(VERILOG_PORT_CONKT, output_port);
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fp << ");" << std::endl;
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}
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}
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}
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/* Put an end to this module */
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fp << "endmodule" << std::endl;
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/* Comment lines */
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fp << "//---- END Structural Verilog CMOS MUX basis module: " << module_name << "-----" << std::endl << std::endl;
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return;
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}
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/***********************************************
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* Generate Verilog codes modeling an branch circuit
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* for a multiplexer with the given size
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**********************************************/
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void generate_verilog_mux_branch_module(std::fstream& fp,
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const CircuitLibrary& circuit_lib,
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const CircuitModelId& circuit_model,
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const size_t& mux_size,
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const MuxGraph& mux_graph) {
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std::string module_name = generate_verilog_mux_branch_subckt_name(circuit_lib, circuit_model, mux_size, verilog_mux_basis_posfix);
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/* Multiplexers built with different technology is in different organization */
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switch (circuit_lib.design_tech_type(circuit_model)) {
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case SPICE_MODEL_DESIGN_CMOS:
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if (true == circuit_lib.dump_structural_verilog(circuit_model)) {
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generate_verilog_cmos_mux_branch_module_structural(fp, circuit_lib, circuit_model, module_name, mux_graph);
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} else {
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/*
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dump_verilog_cmos_mux_one_basis_module(fp, mux_basis_subckt_name,
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mux_size,
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num_input_basis_subckt,
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cur_spice_model,
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special_basis);
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*/
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}
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break;
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case SPICE_MODEL_DESIGN_RRAM:
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/* If requested, we can dump structural verilog for basis module */
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/*
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if (true == circuit_lib.dump_structural_verilog(circuit_model)) {
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dump_verilog_rram_mux_one_basis_module_structural(fp, mux_basis_subckt_name,
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num_input_basis_subckt,
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cur_spice_model);
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} else {
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dump_verilog_rram_mux_one_basis_module(fp, mux_basis_subckt_name,
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num_input_basis_subckt,
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cur_spice_model);
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}
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*/
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break;
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default:
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vpr_printf(TIO_MESSAGE_ERROR,
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"(FILE:%s,LINE[%d]) Invalid design technology of multiplexer (name: %s)\n",
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__FILE__, __LINE__, circuit_lib.model_name(circuit_model));
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exit(1);
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}
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return;
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}
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