232 lines
10 KiB
C++
232 lines
10 KiB
C++
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/***************************************************************************************
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* This file includes functions to generate Verilog modules of decoders
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***************************************************************************************/
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/* TODO: merge verilog_decoder.c to this source file and rename to verilog_decoder.cpp */
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#include <string>
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/* Headers from vtrutil library */
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#include "vtr_assert.h"
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#include "vtr_log.h"
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/* Headers from openfpgautil library */
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#include "openfpga_digest.h"
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#include "openfpga_decode.h"
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#include "decoder_library_utils.h"
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#include "module_manager.h"
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#include "openfpga_naming.h"
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#include "verilog_constants.h"
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#include "verilog_writer_utils.h"
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#include "verilog_decoders.h"
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/* begin namespace openfpga */
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namespace openfpga {
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/***************************************************************************************
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* Create a Verilog module for a decoder with a given output size
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*
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* Inputs
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* | | ... |
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* v v v
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* +-----------+
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* / \
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* / Decoder \
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* +-----------------+
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* | | | ... | | |
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* v v v v v v
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* Outputs
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*
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* The outputs are assumes to be one-hot codes (at most only one '1' exist)
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* Considering this fact, there are only num_of_outputs conditions to be encoded.
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* Therefore, the number of inputs is ceil(log(num_of_outputs)/log(2))
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***************************************************************************************/
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static
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void print_verilog_mux_local_decoder_module(std::fstream& fp,
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ModuleManager& module_manager,
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const DecoderLibrary& decoder_lib,
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const DecoderId& decoder) {
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/* Get the number of inputs */
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size_t addr_size = decoder_lib.addr_size(decoder);
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size_t data_size = decoder_lib.data_size(decoder);
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/* Validate the FILE handler */
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VTR_ASSERT(true == valid_file_stream(fp));
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/* TODO: create a name for the local encoder */
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std::string module_name = generate_mux_local_decoder_subckt_name(addr_size, data_size);
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/* Create a Verilog Module based on the circuit model, and add to module manager */
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ModuleId module_id = module_manager.find_module(module_name);
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VTR_ASSERT(true == module_manager.valid_module_id(module_id));
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/* Add module ports */
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/* Add each input port */
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BasicPort addr_port(generate_mux_local_decoder_addr_port_name(), addr_size);
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/* Add each output port */
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BasicPort data_port(generate_mux_local_decoder_data_port_name(), data_size);
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/* Data port is registered. It should be outputted as
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* output reg [lsb:msb] data
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*/
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/* Add data_in port */
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BasicPort data_inv_port(generate_mux_local_decoder_data_inv_port_name(), data_size);
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VTR_ASSERT(true == decoder_lib.use_data_inv_port(decoder));
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/* dump module definition + ports */
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print_verilog_module_declaration(fp, module_manager, module_id);
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/* Finish dumping ports */
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print_verilog_comment(fp, std::string("----- BEGIN Verilog codes for Decoder convert " + std::to_string(addr_size) + "-bit addr to " + std::to_string(data_size) + "-bit data -----"));
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/* Print the truth table of this decoder */
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/* Internal logics */
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/* Early exit: Corner case for data size = 1 the logic is very simple:
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* data = addr;
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* data_inv = ~data_inv
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*/
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if (1 == data_size) {
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print_verilog_wire_connection(fp, data_port, addr_port, false);
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print_verilog_wire_connection(fp, data_inv_port, addr_port, true);
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print_verilog_comment(fp, std::string("----- END Verilog codes for Decoder convert " + std::to_string(addr_size) + "-bit addr to " + std::to_string(data_size) + "-bit data -----"));
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/* Put an end to the Verilog module */
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print_verilog_module_end(fp, module_name);
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return;
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}
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/* We use a magic number -1 as the addr=1 should be mapped to ...1
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* Otherwise addr will map addr=1 to ..10
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* Note that there should be a range for the shift operators
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* We should narrow the encoding to be applied to a given set of data
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* This will lead to that any addr which falls out of the op code of data
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* will give a all-zero code
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* For example:
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* data is 5-bit while addr is 3-bit
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* data=8'b0_0000 will be encoded to addr=3'b001;
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* data=8'b0_0001 will be encoded to addr=3'b010;
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* data=8'b0_0010 will be encoded to addr=3'b011;
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* data=8'b0_0100 will be encoded to addr=3'b100;
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* data=8'b0_1000 will be encoded to addr=3'b101;
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* data=8'b1_0000 will be encoded to addr=3'b110;
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* The rest of addr codes 3'b110, 3'b111 will be decoded to data=8'b0_0000;
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*/
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fp << "\t" << "always@(" << generate_verilog_port(VERILOG_PORT_CONKT, addr_port) << ")" << std::endl;
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fp << "\t" << "case (" << generate_verilog_port(VERILOG_PORT_CONKT, addr_port) << ")" << std::endl;
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/* Create a string for addr and data */
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for (size_t i = 0; i < data_size; ++i) {
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fp << "\t\t" << generate_verilog_constant_values(itobin_vec(i, addr_size));
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fp << " : ";
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fp << generate_verilog_port_constant_values(data_port, ito1hot_vec(i, data_size));
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fp << ";" << std::endl;
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}
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fp << "\t\t" << "default : ";
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fp << generate_verilog_port_constant_values(data_port, ito1hot_vec(data_size - 1, data_size));
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fp << ";" << std::endl;
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fp << "\t" << "endcase" << std::endl;
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print_verilog_wire_connection(fp, data_inv_port, data_port, true);
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print_verilog_comment(fp, std::string("----- END Verilog codes for Decoder convert " + std::to_string(addr_size) + "-bit addr to " + std::to_string(data_size) + "-bit data -----"));
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/* Put an end to the Verilog module */
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print_verilog_module_end(fp, module_name);
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}
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/***************************************************************************************
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* This function will generate all the unique Verilog modules of local decoders for
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* the multiplexers used in a FPGA fabric
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* It will reach the goal in two steps:
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* 1. Find the unique local decoders w.r.t. the number of inputs/outputs
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* We will generate the subgraphs from the multiplexing graph of each multiplexers
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* The number of memory bits is the number of outputs.
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* From that we can infer the number of inputs of each local decoders.
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* Here is an illustrative example of how local decoders are interfaced with multi-level MUXes
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*
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* +---------+ +---------+
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* | Local | | Local |
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* | Decoder | | Decoder |
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* | A | | B |
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* +---------+ +---------+
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* | ... | | ... |
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* v v v v
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* +--------------+ +--------------+
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* | MUX Level 0 |--->| MUX Level 1 |
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* +--------------+ +--------------+
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* 2. Generate local decoder Verilog modules using behavioral description.
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* Note that the implementation of local decoders can be dependent on the technology
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* and standard cell libraries.
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* Therefore, behavioral Verilog is used and the local decoders should be synthesized
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* before running the back-end flow for FPGA fabric
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* See more details in the function print_verilog_mux_local_decoder() for more details
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***************************************************************************************/
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void print_verilog_submodule_mux_local_decoders(ModuleManager& module_manager,
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std::vector<std::string>& netlist_names,
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const MuxLibrary& mux_lib,
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const CircuitLibrary& circuit_lib,
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const std::string& verilog_dir,
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const std::string& submodule_dir) {
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std::string verilog_fname(submodule_dir + std::string(LOCAL_ENCODER_VERILOG_FILE_NAME));
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/* Create the file stream */
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std::fstream fp;
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fp.open(verilog_fname, std::fstream::out | std::fstream::trunc);
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check_file_stream(verilog_fname.c_str(), fp);
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/* Print out debugging information for if the file is not opened/created properly */
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VTR_LOG("Writing Verilog netlist for local decoders for multiplexers '%s'...",
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verilog_fname.c_str());
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print_verilog_file_header(fp, "Local Decoders for Multiplexers");
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print_verilog_include_defines_preproc_file(fp, verilog_dir);
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/* Create a library for local encoders with different sizes */
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DecoderLibrary decoder_lib;
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/* Find unique local decoders for unique branches shared by the multiplexers */
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for (auto mux : mux_lib.muxes()) {
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/* Local decoders are need only when users specify them */
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CircuitModelId mux_circuit_model = mux_lib.mux_circuit_model(mux);
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/* If this MUX does not need local decoder, we skip it */
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if (false == circuit_lib.mux_use_local_encoder(mux_circuit_model)) {
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continue;
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}
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const MuxGraph& mux_graph = mux_lib.mux_graph(mux);
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/* Create a mux graph for the branch circuit */
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std::vector<MuxGraph> branch_mux_graphs = mux_graph.build_mux_branch_graphs();
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/* Add the decoder to the decoder library */
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for (auto branch_mux_graph : branch_mux_graphs) {
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/* The decoder size depends on the number of memories of a branch MUX.
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* Note that only when there are >=2 memories, a decoder is needed
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*/
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size_t decoder_data_size = branch_mux_graph.num_memory_bits();
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if (0 == decoder_data_size) {
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continue;
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}
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/* Try to find if the decoder already exists in the library,
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* If there is no such decoder, add it to the library
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*/
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add_mux_local_decoder_to_library(decoder_lib, decoder_data_size);
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}
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}
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/* Generate Verilog modules for the found unique local encoders */
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for (const auto& decoder : decoder_lib.decoders()) {
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print_verilog_mux_local_decoder_module(fp, module_manager, decoder_lib, decoder);
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}
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/* Close the file stream */
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fp.close();
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/* Add fname to the netlist name list */
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netlist_names.push_back(verilog_fname);
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VTR_LOG("Done\n");
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}
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} /* end namespace openfpga */
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