101 lines
3.9 KiB
C
101 lines
3.9 KiB
C
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/*********************************************************************
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* The following code is part of the power modelling feature of VTR.
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*
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* For support:
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* http://code.google.com/p/vtr-verilog-to-routing/wiki/Power
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*
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* or email:
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* vtr.power.estimation@gmail.com
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*
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* If you are using power estimation for your researach please cite:
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*
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* Jeffrey Goeders and Steven Wilton. VersaPower: Power Estimation
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* for Diverse FPGA Architectures. In International Conference on
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* Field Programmable Technology, 2012.
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*
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********************************************************************/
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/**
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* This file offers functions to estimate power of major components
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* within the FPGA (flip-flops, LUTs, interconnect structures, etc).
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*/
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#ifndef __POWER_COMPONENTS_H__
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#define __POWER_COMPONENTS_H__
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/************************* INCLUDES *********************************/
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#include "power.h"
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/************************* Defines **********************************/
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/* This controlls the level of accuracy used for transition density
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* calculations of internal LUT nodes. The more detailed model
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* looks at SRAM values in deciding if toggles on the inputs will
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* toggle the internal nets. The fast method uses only signal
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* probabilities.
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*/
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#define POWER_LUT_SLOW
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#if (!(defined(POWER_LUT_SLOW) || defined(POWER_LUT_FAST)))
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#define POWER_LUT_SLOW
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#endif
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/************************* ENUMS ************************************/
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typedef enum {
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POWER_COMPONENT_IGNORE = 0, /* */
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POWER_COMPONENT_TOTAL, /* Total power for entire FPGA */
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POWER_COMPONENT_ROUTING, /* Power for routing fabric (not local routing) */
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POWER_COMPONENT_ROUTE_SB, /* Switch-box */
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POWER_COMPONENT_ROUTE_CB, /* Connection box*/
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POWER_COMPONENT_ROUTE_GLB_WIRE, /* Wires */
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POWER_COMPONENT_CLOCK, /* Clock network */
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POWER_COMPONENT_CLOCK_BUFFER, /* Buffers in clock network */
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POWER_COMPONENT_CLOCK_WIRE, /* Wires in clock network */
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POWER_COMPONENT_PB, /* Logic Blocks, and other hard blocks */
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POWER_COMPONENT_PB_PRIMITIVES, /* Primitives (LUTs, FF, etc) */
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POWER_COMPONENT_PB_INTERC_MUXES, /* Local interconnect structures (muxes) */
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POWER_COMPONENT_PB_BUFS_WIRE, /* Local buffers and wire capacitance */
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POWER_COMPONENT_PB_OTHER, /* Power from other estimation methods - not transistor-level */
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POWER_COMPONENT_MAX_NUM
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} e_power_component_type;
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/************************* STRUCTS **********************************/
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typedef struct s_power_breakdown t_power_components;
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struct s_power_breakdown {
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t_power_usage * components;
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};
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/************************* FUNCTION DECLARATIONS ********************/
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extern t_power_components g_power_by_component;
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/************************* FUNCTION DECLARATIONS ********************/
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void power_components_init(void);
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void power_components_uninit(void);
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void power_component_get_usage(t_power_usage * power_usage,
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e_power_component_type component_idx);
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void power_component_add_usage(t_power_usage * power_usage,
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e_power_component_type component_idx);
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float power_component_get_usage_sum(e_power_component_type component_idx);
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void power_usage_ff(t_power_usage * power_usage, float size, float D_prob,
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float D_dens, float Q_prob, float Q_dens, float clk_prob,
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float clk_dens, float period);
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void power_usage_lut(t_power_usage * power_usage, int LUT_size,
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float transistor_size, char * SRAM_values, float * input_densities,
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float * input_probabilities, float period);
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void power_usage_local_interc_mux(t_power_usage * power_usage, t_pb * pb,
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t_interconnect_pins * interc_pins);
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void power_usage_mux_multilevel(t_power_usage * power_usage,
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t_mux_arch * mux_arch, float * in_prob, float * in_dens,
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int selected_input, boolean output_level_restored, float period);
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void power_usage_buffer(t_power_usage * power_usage, float size, float in_prob,
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float in_dens, boolean level_restored, float period);
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#endif
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