23 lines
452 B
Systemverilog
23 lines
452 B
Systemverilog
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module top(input clock, input [3:0] delta, output [3:0] cnt1, cnt2);
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cnt #(1) foo (.clock, .cnt(cnt1), .delta);
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cnt #(2) bar (.clock, .cnt(cnt2));
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endmodule
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module cnt #(
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parameter integer initval = 0
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) (
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input clock,
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output logic [3:0] cnt = initval,
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`ifdef __ICARUS__
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input [3:0] delta
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`else
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input [3:0] delta = 10
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`endif
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);
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`ifdef __ICARUS__
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assign (weak0, weak1) delta = 10;
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`endif
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always @(posedge clock)
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cnt <= cnt + delta;
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endmodule
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