122 lines
3.0 KiB
Plaintext
122 lines
3.0 KiB
Plaintext
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#!/usr/bin/env splrun
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//
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// Test procedure for matching Gates with shorted inputs, as suggested in
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// "SubCircuit Extraction with SubGraph Isomorphism. Zong Ling, Ph. D. IBM
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// Almaden Research Center -- EDA Shape Processing zling@us.ibm.com.":
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//
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// Four NAND gates and a NOR gate. One NAND gate (G1) has no shorted inputs,
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// one (G2) has an input shorted to VSS, one (G3) has an input shorted to VDD,
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// and one (G4) has both inputs shorted together. Th last gate (G5) is a NOR
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// gate.
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var net;
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function makeNAND(id)
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{
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net["${id}_VDD"] = "${id}_pa S";
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net["${id}_VSS"] = "${id}_nb S";
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net["${id}_A"] = "${id}_pa G";
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net["${id}_B"] = "${id}_pb G";
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net["${id}_Y"] = "${id}_pb D";
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return <:>
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: node ${id}_pa pmos S 1 D 1 G 1
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: node ${id}_pb pmos S 1 D 1 G 1
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: node ${id}_na nmos S 1 D 1 G 1
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: node ${id}_nb nmos S 1 D 1 G 1
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: connect ${id}_pa S ${id}_pb S
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: connect ${id}_pa D ${id}_pb D
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: connect ${id}_pa D ${id}_na D
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: connect ${id}_na S ${id}_nb D
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: connect ${id}_pa G ${id}_na G
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: connect ${id}_pb G ${id}_nb G
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</>;
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}
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function makeNOR(id)
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{
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net["${id}_VDD"] = "${id}_pa S";
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net["${id}_VSS"] = "${id}_nb S";
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net["${id}_A"] = "${id}_pa G";
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net["${id}_B"] = "${id}_pb G";
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net["${id}_Y"] = "${id}_pb D";
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return <:>
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: node ${id}_pa pmos S 1 D 1 G 1
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: node ${id}_pb pmos S 1 D 1 G 1
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: node ${id}_na nmos S 1 D 1 G 1
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: node ${id}_nb nmos S 1 D 1 G 1
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: connect ${id}_pa D ${id}_pb S
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: connect ${id}_pb D ${id}_na D
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: connect ${id}_pb D ${id}_nb D
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: connect ${id}_na S ${id}_nb S
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: connect ${id}_pa G ${id}_na G
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: connect ${id}_pb G ${id}_nb G
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</>;
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}
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write(<:>
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: graph nand
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: ${ makeNAND("G0") }
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: extern ${net["G0_VDD"]}
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: extern ${net["G0_VSS"]}
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: extern ${net["G0_A"]}
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: extern ${net["G0_B"]}
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: extern ${net["G0_Y"]}
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: endgraph
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:
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: graph nor
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: ${ makeNOR("G0") }
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: extern ${net["G0_VDD"]}
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: extern ${net["G0_VSS"]}
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: extern ${net["G0_A"]}
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: extern ${net["G0_B"]}
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: extern ${net["G0_Y"]}
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: endgraph
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:
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: graph haystack
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: ${ makeNAND("G1") }
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: ${ makeNAND("G2") }
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: ${ makeNAND("G3") }
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: ${ makeNAND("G4") }
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${ makeNOR("G5") }
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:
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: node vdd vsupply V 1
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: connect vdd V ${net["G1_VDD"]}
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: connect vdd V ${net["G2_VDD"]}
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: connect vdd V ${net["G3_VDD"]}
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: connect vdd V ${net["G4_VDD"]}
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: connect vdd V ${net["G5_VDD"]}
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:
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: node vss vsupply V 1
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: connect vss V ${net["G1_VSS"]}
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: connect vss V ${net["G2_VSS"]}
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: connect vss V ${net["G3_VSS"]}
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: connect vss V ${net["G4_VSS"]}
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: connect vss V ${net["G5_VSS"]}
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:
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: connect ${net["G2_A"]} ${net["G1_A"]}
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: connect ${net["G2_B"]} ${net["G2_VSS"]}
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:
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: connect ${net["G3_A"]} ${net["G1_VDD"]}
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: connect ${net["G3_B"]} ${net["G2_Y"]}
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:
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: connect ${net["G4_A"]} ${net["G1_Y"]}
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: connect ${net["G4_B"]} ${net["G1_Y"]}
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:
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: connect ${net["G5_A"]} ${net["G3_Y"]}
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: connect ${net["G5_B"]} ${net["G4_Y"]}
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: endgraph
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:
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: solve nand haystack false
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: clearoverlap
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: expect 4
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:
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: solve nor haystack false
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: clearoverlap
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: expect 1
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</>);
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