26 lines
1.0 KiB
SourcePawn
26 lines
1.0 KiB
SourcePawn
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* Sub Circuits
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*
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* Static D Flip-flop
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.subckt static_dff set rst clk D Q svdd sgnd size=1
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* Input inverter
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Xinv_clk clk clk_b svdd sgnd inv size=size
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Xinv_set set set_b svdd sgnd inv size=size
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Xinv_rst rst rst_b svdd sgnd inv size=size
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Xinv_d D s1_n1 svdd sgnd inv size=size
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Xcpt0 s1_n1 s1_n2 clk_b clk svdd sgnd cpt nmos_size='size' pmos_size='size*beta'
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Xset0 s1_n2 set_b svdd svdd vpr_pmos L=pl W='size*wp'
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Xrst0 s1_n2 rst sgnd sgnd vpr_nmos L=nl W='size*wn'
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Xinv1 s1_n2 s1_q svdd sgnd inv size=size
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Xinv2 s1_q s1_n3 svdd sgnd inv size=size
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Xcpt1 s1_n3 s1_n2 clk clk_b svdd sgnd cpt nmos_size='size' pmos_size='size*beta'
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* Stage 2
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R3 s1_q s2_n1 0
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Xcpt2 s2_n1 s2_n2 clk clk_b svdd sgnd cpt nmos_size='size' pmos_size='size*beta'
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Xrst1 s2_n2 rst_b svdd svdd vpr_pmos L=pl W='size*wp'
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Xset1 s2_n2 set sgnd sgnd vpr_nmos L=nl W='size*wn'
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Xinv4 s2_n2 Qb svdd sgnd inv size=size
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Xinv5 Qb s2_n3 svdd sgnd inv size=size
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Xcpt3 s2_n3 s2_n2 clk_b clk svdd sgnd cpt nmos_size='size' pmos_size='size*beta'
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Xinv_out Qb Q svdd sgnd inv size=size
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.eom static_dff
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