31 lines
1.5 KiB
SourcePawn
31 lines
1.5 KiB
SourcePawn
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* Sub Circuit
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* 1-Bit Full-Adder circuit netlist
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.subckt adder inA inB Cin Cout Sumout svdd sgnd size=1
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X01 nd1 inA svdd svdd vpr_pmos W='size*beta*wp' L='pl'
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X02 nd1 inB svdd svdd vpr_pmos W='size*beta*wp' L='pl'
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X03 nd2 inB nd1 svdd vpr_pmos W='size*beta*wp' L='pl'
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X04 nco inA nd2 svdd vpr_pmos W='size*beta*wp' L='pl'
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X05 nco Cin nd1 svdd vpr_pmos W='size*beta*wp' L='pl'
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X06 nco Cin nd3 sgnd vpr_nmos W='size*wn' L='nl'
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X07 nd3 inA sgnd sgnd vpr_nmos W='size*wn' L='nl'
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X08 nd3 inB sgnd sgnd vpr_nmos W='size*wn' L='nl'
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X09 nco inA nd4 sgnd vpr_nmos W='size*wn' L='nl'
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X10 nd4 inB sgnd sgnd vpr_nmos W='size*wn' L='nl'
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Xo1 nco Cout svdd sgnd inv size='size'
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X11 nd5 inA svdd svdd vpr_pmos W='size*beta*wp' L='pl'
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X12 nd5 inB svdd svdd vpr_pmos W='size*beta*wp' L='pl'
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X13 nd5 Cin svdd svdd vpr_pmos W='size*beta*wp' L='pl'
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X14 nd6 inA nd5 svdd vpr_pmos W='size*beta*wp' L='pl'
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X15 nd7 inB nd6 svdd vpr_pmos W='size*beta*wp' L='pl'
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X16 ndS Cin nd7 svdd vpr_pmos W='size*beta*wp' L='pl'
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X23 nds nco nd5 svdd vpr_pmos W='size*beta*wp' L='pl'
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X24 nds nco nd8 sgnd vpr_nmos W='size*wn' L='nl'
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X17 nd8 inA sgnd sgnd vpr_nmos W='size*wn' L='nl'
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X18 nd8 inB sgnd sgnd vpr_nmos W='size*wn' L='nl'
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X19 nd8 Cin sgnd sgnd vpr_nmos W='size*wn' L='nl'
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X20 ndS Cin nd9 sgnd vpr_nmos W='size*wn' L='nl'
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X21 nd9 inA n10 sgnd vpr_nmos W='size*wn' L='nl'
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X22 n10 inB sgnd sgnd vpr_nmos W='size*wn' L='nl'
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Xo2 nds Sumout svdd sgnd inv size='size'
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.eom
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