2019-08-17 02:49:49 -05:00
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python3.5 openfpga_flow/scripts/run_fpga_flow.py \
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2019-08-19 20:06:46 -05:00
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./openfpga_flow/arch/template/k6_N10_sram_chain_HC_template.xml \
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2019-08-17 02:49:49 -05:00
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./openfpga_flow/benchmarks/MCNC_Verilog/s298/s298.v \
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--top_module s298 \
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--power \
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2019-08-19 20:06:46 -05:00
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--power_tech ./openfpga_flow/tech/PTM_22nm/22nm.xml \
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2019-08-17 02:49:49 -05:00
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--min_route_chan_width 1.3 \
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--vpr_fpga_verilog \
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2019-08-19 20:06:46 -05:00
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--vpr_fpga_verilog_dir . \
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2019-08-17 02:49:49 -05:00
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--vpr_fpga_x2p_rename_illegal_port \
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2019-08-19 20:06:46 -05:00
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--end_flow_with_test \
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--vpr_fpga_verilog_include_icarus_simulator \
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--vpr_fpga_verilog_formal_verification_top_netlist \
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--vpr_fpga_verilog_include_timing \
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--vpr_fpga_verilog_include_signal_init \
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--vpr_fpga_verilog_print_autocheck_top_testbench
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