24 lines
1000 B
Coq
24 lines
1000 B
Coq
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//-------------------------------------------
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// FPGA Synthesizable Verilog Netlist
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// Description: Header file
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// Author: Xifan TANG
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// Organization: EPFL/IC/LSI
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// Date: Thu Nov 15 14:26:04 2018
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//-------------------------------------------
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//----- Time scale -----
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`timescale 1ns / 1ps
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`include "./verilog_test_example_1/routing/cby_1_1.v"
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`include "./verilog_test_example_1/routing/cby_0_1.v"
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`include "./verilog_test_example_1/routing/cbx_1_1.v"
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`include "./verilog_test_example_1/routing/cbx_1_0.v"
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`include "./verilog_test_example_1/routing/sb_1_1.v"
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`include "./verilog_test_example_1/routing/sb_1_0.v"
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`include "./verilog_test_example_1/routing/sb_0_1.v"
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`include "./verilog_test_example_1/routing/sb_0_0.v"
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`include "./verilog_test_example_1/routing/chany_1_1.v"
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`include "./verilog_test_example_1/routing/chany_0_1.v"
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`include "./verilog_test_example_1/routing/chanx_1_1.v"
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`include "./verilog_test_example_1/routing/chanx_1_0.v"
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