OpenFPGA/vpr7_x2p/vpr/SRC/fpga_spice/verilog/verilog_primitives.h

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2018-07-26 12:28:21 -05:00
void dump_verilog_pb_primitive_ff(FILE* fp,
char* subckt_prefix,
t_logical_block* mapped_logical_block,
t_pb_graph_node* prim_pb_graph_node,
int index,
t_spice_model* spice_model);
void dump_verilog_pb_primitive_hardlogic(FILE* fp,
char* subckt_prefix,
t_logical_block* mapped_logical_block,
t_pb_graph_node* prim_pb_graph_node,
int index,
t_spice_model* spice_model);
void dump_verilog_pb_primitive_io(FILE* fp,
char* subckt_prefix,
t_logical_block* mapped_logical_block,
t_pb_graph_node* prim_pb_graph_node,
int index,
t_spice_model* spice_model);