53 lines
1.7 KiB
C
53 lines
1.7 KiB
C
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/* global parameters for dumping synthesizable verilog */
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extern char* verilog_netlist_file_postfix;
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extern char* verilog_top_postfix;
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extern char* bitstream_verilog_file_postfix;
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extern char* top_testbench_verilog_file_postfix;
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extern char* blif_testbench_verilog_file_postfix;
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extern char* logic_block_verilog_file_name;
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extern char* luts_verilog_file_name;
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extern char* routing_verilog_file_name;
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extern char* muxes_verilog_file_name;
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extern char* wires_verilog_file_name;
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extern char* essentials_verilog_file_name;
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extern char* decoders_verilog_file_name;
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extern char* verilog_mux_basis_posfix;
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extern char* verilog_mux_special_basis_posfix;
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/* Prefix for subckt Verilog netlists */
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extern char* grid_verilog_file_name_prefix;
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extern char* chanx_verilog_file_name_prefix;
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extern char* chany_verilog_file_name_prefix;
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extern char* sb_verilog_file_name_prefix;
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extern char* cbx_verilog_file_name_prefix;
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extern char* cby_verilog_file_name_prefix;
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extern t_spice_model* sram_verilog_model;
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extern enum e_sram_orgz sram_verilog_orgz_type;
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extern t_sram_orgz_info* sram_verilog_orgz_info;
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/* Input and Output Pad spice model. should be set as global */
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extern t_spice_model* inpad_verilog_model;
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extern t_spice_model* outpad_verilog_model;
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extern t_spice_model* iopad_verilog_model;
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/* Linked-list that stores all the configuration bits */
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extern t_llist* conf_bits_head;
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/* Linked-list that stores submodule Verilog file mames */
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extern t_llist* grid_verilog_subckt_file_path_head;
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extern t_llist* routing_verilog_subckt_file_path_head;
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extern int verilog_default_signal_init_value;
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enum e_dump_verilog_port_type {
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VERILOG_PORT_INPUT,
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VERILOG_PORT_OUTPUT,
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VERILOG_PORT_INOUT,
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VERILOG_PORT_WIRE,
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VERILOG_PORT_REG,
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VERILOG_PORT_CONKT
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};
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