OpenFPGA/openfpga_flow/benchmarks/micro_benchmark/counter/counter.v

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2020-07-22 13:33:52 -05:00
module counter_original(clk_counter, q_counter, rst_counter);
input clk_counter;
input rst_counter;
output [7:0] q_counter;
reg [7:0] q_counter;
always @ (posedge clk_counter)
begin
if(rst_counter)
q_counter <= 8'b00000000;
else
q_counter <= q_counter + 1;
end
endmodule