51 lines
1.8 KiB
SourcePawn
51 lines
1.8 KiB
SourcePawn
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*****************************
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* FPGA SPICE Netlist *
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* Description: Wires *
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* Author: Xifan TANG *
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* Organization: EPFL/IC/LSI *
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* Date: Thu Nov 15 14:26:04 2018
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*
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*****************************
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* Wire, spice_model_name=direct_interc
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.subckt direct_interc in out svdd sgnd
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Rshortcut in out 0
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.eom
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* Wire models for segments in routing
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* Wire, spice_model_name=chan_segment
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.subckt chan_segment_seg0 in out mid_out svdd sgnd
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Clvin pie_wire_in0 sgnd 'chan_segment_wire_param_cap_val/2'
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Rlv0_idx0 pie_wire_in0 pie_wire_in0_inter 'chan_segment_wire_param_res_val/2'
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Rlv0_idx1 pie_wire_in0_inter pie_wire_in1 'chan_segment_wire_param_res_val/2'
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Clv0_idx1 pie_wire_in1 sgnd 'chan_segment_wire_param_cap_val/2'
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* Connect the output of middle point
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Vmid_out_ckt pie_wire_in0_inter mid_out 0
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Rin in pie_wire_in0 0
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Rout pie_wire_in1 out 0
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.eom
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* Wire, spice_model_name=chan_segment
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.subckt chan_segment_seg1 in out mid_out svdd sgnd
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Clvin pie_wire_in0 sgnd 'chan_segment_wire_param_cap_val/2'
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Rlv0_idx0 pie_wire_in0 pie_wire_in0_inter 'chan_segment_wire_param_res_val/2'
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Rlv0_idx1 pie_wire_in0_inter pie_wire_in1 'chan_segment_wire_param_res_val/2'
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Clv0_idx1 pie_wire_in1 sgnd 'chan_segment_wire_param_cap_val/2'
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* Connect the output of middle point
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Vmid_out_ckt pie_wire_in0_inter mid_out 0
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Rin in pie_wire_in0 0
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Rout pie_wire_in1 out 0
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.eom
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* Wire, spice_model_name=chan_segment
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.subckt chan_segment_seg2 in out mid_out svdd sgnd
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Clvin pie_wire_in0 sgnd 'chan_segment_wire_param_cap_val/2'
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Rlv0_idx0 pie_wire_in0 pie_wire_in0_inter 'chan_segment_wire_param_res_val/2'
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Rlv0_idx1 pie_wire_in0_inter pie_wire_in1 'chan_segment_wire_param_res_val/2'
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Clv0_idx1 pie_wire_in1 sgnd 'chan_segment_wire_param_cap_val/2'
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* Connect the output of middle point
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Vmid_out_ckt pie_wire_in0_inter mid_out 0
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Rin in pie_wire_in0 0
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Rout pie_wire_in1 out 0
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.eom
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